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From: tkuw584924@gmail.com
To: linux-mtd@lists.infradead.org
Cc: tudor.ambarus@microchip.com, pratyush@kernel.org,
	michael@walle.cc, miquel.raynal@bootlin.com, richard@nod.at,
	vigneshr@ti.com, tkuw584924@gmail.com, Bacem.Daassi@infineon.com,
	Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Subject: [PATCH 6/8] mtd: spi-nor: spansion: Add a new ->ready() hook for multi-chip device
Date: Sat,  6 Aug 2022 15:34:24 +0900	[thread overview]
Message-ID: <058c6966e61ca5eaacfb547f4d55194edfbae61a.1659764848.git.Takahiro.Kuwano@infineon.com> (raw)
In-Reply-To: <cover.1659764848.git.Takahiro.Kuwano@infineon.com>

From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>

For multi-chip devices, we need to make sure the all dice in the device
are ready. The cypress_nor_sr_ready_and_clear() reads SR in each die and
returns true only when all dice are ready. This function also takes care
for program or erase error handling by reusing spansion_nor_clear_sr().
To do that, spansion_nor_clear_sr() is moved to top.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
---
 drivers/mtd/spi-nor/spansion.c | 95 ++++++++++++++++++++++++++--------
 1 file changed, 72 insertions(+), 23 deletions(-)

diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index d7a61ea63139..fc9cc3484aa3 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -14,6 +14,7 @@
 #define SPINOR_OP_CLSR		0x30	/* Clear status register 1 */
 #define SPINOR_OP_RD_ANY_REG			0x65	/* Read any register */
 #define SPINOR_OP_WR_ANY_REG			0x71	/* Write any register */
+#define SPINOR_REG_CYPRESS_STR1			0x0
 #define SPINOR_REG_CYPRESS_CFR1			0x2
 #define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN	BIT(1)	/* Quad Enable */
 #define SPINOR_REG_CYPRESS_CFR2V		0x00800003
@@ -44,6 +45,29 @@
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_NO_DATA)
 
+/**
+ * spansion_nor_clear_sr() - Clear the Status Register.
+ * @nor:	pointer to 'struct spi_nor'.
+ */
+static void spansion_nor_clear_sr(struct spi_nor *nor)
+{
+	int ret;
+
+	if (nor->spimem) {
+		struct spi_mem_op op = SPANSION_CLSR_OP;
+
+		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
+
+		ret = spi_mem_exec_op(nor->spimem, &op);
+	} else {
+		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR,
+						       NULL, 0);
+	}
+
+	if (ret)
+		dev_dbg(nor->dev, "error %d clearing SR\n", ret);
+}
+
 static int cypress_nor_octal_dtr_en(struct spi_nor *nor)
 {
 	struct spi_mem_op op;
@@ -221,6 +245,51 @@ static void cypress_nor_set_page_size(struct spi_nor *nor)
 	params->page_size = 512;
 }
 
+/**
+ * cypress_nor_sr_ready_and_clear() - Query the Status Register of each die by
+ * using Read Any Regiser command to see if the whole flash is ready for new
+ * commands and clear it if there are any errors.
+ * @nor:	pointer to 'struct spi_nor'.
+ *
+ * Return: 1 if ready, 0 if not ready, -errno on errors.
+ */
+static int cypress_nor_sr_ready_and_clear(struct spi_nor *nor)
+{
+	struct spi_mem_op op =
+		CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, 0,
+					  nor->bouncebuf);
+	int ret;
+	u8 i;
+
+	for (i = 0; i < nor->params->num_of_dice; i++) {
+		op.addr.val =
+			nor->params->vreg_offset[i] + SPINOR_REG_CYPRESS_STR1;
+		ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
+		if (ret)
+			return ret;
+
+		if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
+			if (nor->bouncebuf[0] & SR_E_ERR)
+				dev_err(nor->dev, "Erase Error occurred\n");
+			else
+				dev_err(nor->dev, "Programming Error occurred\n");
+
+			spansion_nor_clear_sr(nor);
+
+			ret = spi_nor_write_disable(nor);
+			if (ret)
+				return ret;
+
+			return -EIO;
+		}
+
+		if (nor->bouncebuf[0] & SR_WIP)
+			return 0;
+	}
+
+	return 1;
+}
+
 static int
 s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
 			const struct sfdp_parameter_header *bfpt_header,
@@ -267,6 +336,9 @@ static void s25hx_t_late_init(struct spi_nor *nor)
 
 	/* The writesize should be ECC data unit size */
 	params->writesize = 16;
+
+	if (nor->params->num_of_dice > 1)
+		nor->params->ready = cypress_nor_sr_ready_and_clear;
 }
 
 static struct spi_nor_fixups s25hx_t_fixups = {
@@ -470,29 +542,6 @@ static const struct flash_info spansion_nor_parts[] = {
 	},
 };
 
-/**
- * spansion_nor_clear_sr() - Clear the Status Register.
- * @nor:	pointer to 'struct spi_nor'.
- */
-static void spansion_nor_clear_sr(struct spi_nor *nor)
-{
-	int ret;
-
-	if (nor->spimem) {
-		struct spi_mem_op op = SPANSION_CLSR_OP;
-
-		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
-
-		ret = spi_mem_exec_op(nor->spimem, &op);
-	} else {
-		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR,
-						       NULL, 0);
-	}
-
-	if (ret)
-		dev_dbg(nor->dev, "error %d clearing SR\n", ret);
-}
-
 /**
  * spansion_nor_sr_ready_and_clear() - Query the Status Register to see if the
  * flash is ready for new commands and clear it if there are any errors.
-- 
2.25.1


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http://lists.infradead.org/mailman/listinfo/linux-mtd/

  parent reply	other threads:[~2022-08-06  6:36 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-06  6:34 [PATCH 0/8] mtd: spi-nor: Add support for Infineon SEMPER s25hl02gt and s25hs02gt tkuw584924
2022-08-06  6:34 ` [PATCH 1/8] mtd: spi-nor: core: Introduce number of dice and volatile register offset params tkuw584924
2022-08-06  6:34 ` [PATCH 2/8] mtd: spi-nor: sfdp: Extract volatile register offset from SCCR map tkuw584924
2022-08-06  6:34 ` [PATCH 3/8] mtd: spi-nor: sfdp: Add support for SCCR map for multi-chip device tkuw584924
2022-08-06  6:34 ` [PATCH 4/8] mtd: spi-nor: spansion: Rework cypress_nor_set_page_size() for multi-chip device support tkuw584924
2022-08-06  6:34 ` [PATCH 5/8] mtd: spi-nor: spansion: Rework cypress_nor_quad_enable_volatile() " tkuw584924
2022-08-10 14:40   ` Takahiro Kuwano
2022-08-06  6:34 ` tkuw584924 [this message]
2022-08-06  6:34 ` [PATCH 7/8] mtd: spi-nor: spansion: Introduce DEF_4BAM mfr flag tkuw584924
2022-08-06  6:34 ` [PATCH 8/8] mtd: spi-nor: spansion: Add support for Infineon tkuw584924
2022-08-08  4:47   ` Tudor.Ambarus
2022-08-08  5:42     ` Takahiro Kuwano
2022-08-08  6:08       ` Tudor.Ambarus
2022-08-08  6:41         ` Takahiro Kuwano
2022-08-08  7:34           ` Tudor.Ambarus
2022-08-08  8:09             ` Takahiro Kuwano
2022-08-08  8:26               ` Tudor.Ambarus
2022-08-08  8:31                 ` Takahiro Kuwano
2022-08-12  8:15                   ` Takahiro Kuwano

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