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From: Takahiro Kuwano <tkuw584924@gmail.com>
To: Tudor.Ambarus@microchip.com, linux-mtd@lists.infradead.org
Cc: pratyush@kernel.org, michael@walle.cc, miquel.raynal@bootlin.com,
	richard@nod.at, vigneshr@ti.com, Bacem.Daassi@infineon.com,
	Takahiro.Kuwano@infineon.com
Subject: Re: [PATCH 8/8] mtd: spi-nor: spansion: Add support for Infineon
Date: Mon, 8 Aug 2022 17:31:39 +0900	[thread overview]
Message-ID: <aa5ac961-7943-2a56-2994-b45de983d55e@gmail.com> (raw)
In-Reply-To: <7c67ed6d-584f-61fd-a532-b7ff00a6a39f@microchip.com>

On 8/8/2022 5:26 PM, Tudor.Ambarus@microchip.com wrote:
> On 8/8/22 11:09, Takahiro Kuwano wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 8/8/2022 4:34 PM, Tudor.Ambarus@microchip.com wrote:
>>> On 8/8/22 09:41, Takahiro Kuwano wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On 8/8/2022 3:08 PM, Tudor.Ambarus@microchip.com wrote:
>>>>> On 8/8/22 08:42, Takahiro Kuwano wrote:
>>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>>
>>>>>> On 8/8/2022 1:47 PM, Tudor.Ambarus@microchip.com wrote:
>>>>>>> On 8/6/22 09:34, tkuw584924@gmail.com wrote:
>>>>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>>>>
>>>>>>>> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>>>>>>>
>>>>>>> Hi!
>>>>>>>
>>>>>>>>
>>>>>>>> s25hl02gt and s25hs02gt
>>>>>>>>
>>>>>>>> Add ID, flags, and fixup for s25hl02gt and s25hs02gt.
>>>>>>>> These parts are
>>>>>>>>   - Dual-die package parts
>>>>>>>>   - Not support chip erase
>>>>>>>>   - 4-byte addressing mode by default
>>>>>>>
>>>>>>> CFR2N[7] CFR2V[7] says that: "For the DDP or QDP devices, if ADRBYT = 0
>>>>>>> only the first 128 Mb of die 1 can be accessed."
>>>>>>> So there are flashes of the same family that are by default in 3 byte address
>>>>>>> mode. You added support just for a subset of them and used a generic name,
>>>>>>> which is not accurate, right?
>>>>>>>
>>>>>> We added model #15 (3-byte address mode by default) to address special
>>>>>> requirement from a customer who needs to use bootrom with 3-byte addressing.
>>>>>> Anyway, I overlooked model # difference. Thanks for pointing out this.
>>>>>>
>>>>>>> Can we instead make an algorithm to determine the current address mode?
>>>>>>>
>>>>>> I have just found that we can distinguish model # via BFPT DWORD16.
>>>>>> If Hardware reset, Software reset, or Power cycle can exit 4-byte address
>>>>>> mode, that means the device is 3-byte address mode by default.
>>>>>
>>>>> I don't think this will help us. It doesn't matter the default mode if you
>>>>> have a non volatile register that can be updated and changes the default
>>>>> mode.
>>>>>
>>>>> Are there any registers/data that can be read successively in 3 byte addr mode
>>>>> and then in 4 byte addr mode? We'll then compare what we receive from the flash
>>>>> with a known value and determine the mode.
>>>>>
>>>> As we discussed before [0], if address mode in the controller and device are
>>>
>>> I remember, yes, but without determining the mode, the driver will work only
>>> with flashes that come with the factory settings. The driver will be unusable
>>> if someone changes the address mode in a non volatile way, right?
>>>
>> Yes, right.
>>
>>>> different, the read data will be undetermined.
>>>>
>>>> But if we really want...
>>>> Compare SR1 data read by RDSR1(05h - No Addr) and RDAR(65h - Addr 0).
>>>> In most cases (without block protection), SR1=00h. The value of 00h would be
>>>> awkward to determine if this is 'real' output from Flash or not. So, use> WREN(06h) and WRDI(04h) that flips BIT(1) in SR1.
>>>
>>> Would be good to have more fixed/OPT-like bits, or if we could change more bits
>>> to increase the chances to not hit just some undetermined data.
>>>>
>>>> Therefore, something like:
>>>> 1) RDSR1
>>>> 2) RDAR with 3-byte addr (000000h)
>>>> 3) If #1 == #2
>>>>         4) WREN
>>>>         5) RDAR with 3-byte addr (000000h)
>>>>         6) BIT(1) is SR1==1?
>>>>         ...
>>>>
>>>> Or simply WREN -> RDAR -> WRDI -> RDAR then check if only BIT(1) is toggled.
>>>
>>> Both may work, yes, but making the assumption on only one bit is fragile.
>>> Can we use the Read Any Register Command with 3 and 4 byte address modes and
>>> compare the values? Are there any registers with fixed values?
>>>
>> Register values can vary because it's register:)
>>
>> So... let's use Data Integrity Check CRC registers. These registers do not
>> have fixed values but we can calculate expected values by offline. Read
>> several bytes (>=4) from Flash array with Read(03h) then calculate CRC by
>> crc32(). Issue Data integrity Check command (5Bh) followed by start and
>> end address (4-byte for each), wait till ready. Read calculated CRC by
>> Read Any Register in 3 and 4 byte address (00800095h~0080098h) then compare
>> the crc32() result and register read result.
> 
> Much better, yes. I think it is worth it. What's your opinion, Takahiro?
> Others, Michael, Pratyush?
> 
OK, I will prototype and test it.

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  reply	other threads:[~2022-08-08  8:31 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-06  6:34 [PATCH 0/8] mtd: spi-nor: Add support for Infineon SEMPER s25hl02gt and s25hs02gt tkuw584924
2022-08-06  6:34 ` [PATCH 1/8] mtd: spi-nor: core: Introduce number of dice and volatile register offset params tkuw584924
2022-08-06  6:34 ` [PATCH 2/8] mtd: spi-nor: sfdp: Extract volatile register offset from SCCR map tkuw584924
2022-08-06  6:34 ` [PATCH 3/8] mtd: spi-nor: sfdp: Add support for SCCR map for multi-chip device tkuw584924
2022-08-06  6:34 ` [PATCH 4/8] mtd: spi-nor: spansion: Rework cypress_nor_set_page_size() for multi-chip device support tkuw584924
2022-08-06  6:34 ` [PATCH 5/8] mtd: spi-nor: spansion: Rework cypress_nor_quad_enable_volatile() " tkuw584924
2022-08-10 14:40   ` Takahiro Kuwano
2022-08-06  6:34 ` [PATCH 6/8] mtd: spi-nor: spansion: Add a new ->ready() hook for multi-chip device tkuw584924
2022-08-06  6:34 ` [PATCH 7/8] mtd: spi-nor: spansion: Introduce DEF_4BAM mfr flag tkuw584924
2022-08-06  6:34 ` [PATCH 8/8] mtd: spi-nor: spansion: Add support for Infineon tkuw584924
2022-08-08  4:47   ` Tudor.Ambarus
2022-08-08  5:42     ` Takahiro Kuwano
2022-08-08  6:08       ` Tudor.Ambarus
2022-08-08  6:41         ` Takahiro Kuwano
2022-08-08  7:34           ` Tudor.Ambarus
2022-08-08  8:09             ` Takahiro Kuwano
2022-08-08  8:26               ` Tudor.Ambarus
2022-08-08  8:31                 ` Takahiro Kuwano [this message]
2022-08-12  8:15                   ` Takahiro Kuwano

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