From: <Tudor.Ambarus@microchip.com>
To: <tkuw584924@gmail.com>, <linux-mtd@lists.infradead.org>
Cc: <pratyush@kernel.org>, <michael@walle.cc>,
<miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>,
<Bacem.Daassi@infineon.com>, <Takahiro.Kuwano@infineon.com>
Subject: Re: [PATCH 8/8] mtd: spi-nor: spansion: Add support for Infineon
Date: Mon, 8 Aug 2022 06:08:44 +0000 [thread overview]
Message-ID: <80b5e707-23b3-e357-c7ae-f78b6c75f2f6@microchip.com> (raw)
In-Reply-To: <ecf3906e-a3c4-328e-09b8-1e801896ce81@gmail.com>
On 8/8/22 08:42, Takahiro Kuwano wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 8/8/2022 1:47 PM, Tudor.Ambarus@microchip.com wrote:
>> On 8/6/22 09:34, tkuw584924@gmail.com wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>>
>> Hi!
>>
>>>
>>> s25hl02gt and s25hs02gt
>>>
>>> Add ID, flags, and fixup for s25hl02gt and s25hs02gt.
>>> These parts are
>>> - Dual-die package parts
>>> - Not support chip erase
>>> - 4-byte addressing mode by default
>>
>> CFR2N[7] CFR2V[7] says that: "For the DDP or QDP devices, if ADRBYT = 0
>> only the first 128 Mb of die 1 can be accessed."
>> So there are flashes of the same family that are by default in 3 byte address
>> mode. You added support just for a subset of them and used a generic name,
>> which is not accurate, right?
>>
> We added model #15 (3-byte address mode by default) to address special
> requirement from a customer who needs to use bootrom with 3-byte addressing.
> Anyway, I overlooked model # difference. Thanks for pointing out this.
>
>> Can we instead make an algorithm to determine the current address mode?
>>
> I have just found that we can distinguish model # via BFPT DWORD16.
> If Hardware reset, Software reset, or Power cycle can exit 4-byte address
> mode, that means the device is 3-byte address mode by default.
I don't think this will help us. It doesn't matter the default mode if you
have a non volatile register that can be updated and changes the default
mode.
Are there any registers/data that can be read successively in 3 byte addr mode
and then in 4 byte addr mode? We'll then compare what we receive from the flash
with a known value and determine the mode.
> The questions is can we implement in spi_nor_parse_bfpt() in sfdp.c or
> post_bfpt_fixup() in manufacturer code?
>
--
Cheers,
ta
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next prev parent reply other threads:[~2022-08-08 6:09 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-06 6:34 [PATCH 0/8] mtd: spi-nor: Add support for Infineon SEMPER s25hl02gt and s25hs02gt tkuw584924
2022-08-06 6:34 ` [PATCH 1/8] mtd: spi-nor: core: Introduce number of dice and volatile register offset params tkuw584924
2022-08-06 6:34 ` [PATCH 2/8] mtd: spi-nor: sfdp: Extract volatile register offset from SCCR map tkuw584924
2022-08-06 6:34 ` [PATCH 3/8] mtd: spi-nor: sfdp: Add support for SCCR map for multi-chip device tkuw584924
2022-08-06 6:34 ` [PATCH 4/8] mtd: spi-nor: spansion: Rework cypress_nor_set_page_size() for multi-chip device support tkuw584924
2022-08-06 6:34 ` [PATCH 5/8] mtd: spi-nor: spansion: Rework cypress_nor_quad_enable_volatile() " tkuw584924
2022-08-10 14:40 ` Takahiro Kuwano
2022-08-06 6:34 ` [PATCH 6/8] mtd: spi-nor: spansion: Add a new ->ready() hook for multi-chip device tkuw584924
2022-08-06 6:34 ` [PATCH 7/8] mtd: spi-nor: spansion: Introduce DEF_4BAM mfr flag tkuw584924
2022-08-06 6:34 ` [PATCH 8/8] mtd: spi-nor: spansion: Add support for Infineon tkuw584924
2022-08-08 4:47 ` Tudor.Ambarus
2022-08-08 5:42 ` Takahiro Kuwano
2022-08-08 6:08 ` Tudor.Ambarus [this message]
2022-08-08 6:41 ` Takahiro Kuwano
2022-08-08 7:34 ` Tudor.Ambarus
2022-08-08 8:09 ` Takahiro Kuwano
2022-08-08 8:26 ` Tudor.Ambarus
2022-08-08 8:31 ` Takahiro Kuwano
2022-08-12 8:15 ` Takahiro Kuwano
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