* [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options
@ 2019-04-01 21:13 Maxime Ripard
2019-04-01 21:13 ` [PATCH 2/4] dt-bindings: mtd: sunxi-nand: Add YAML schemas Maxime Ripard
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Maxime Ripard @ 2019-04-01 21:13 UTC (permalink / raw)
To: Boris Brezillon, Mark Rutland, Rob Herring, Frank Rowand, Miquel Raynal
Cc: Maxime Ripard, devicetree, Chen-Yu Tsai, linux-mtd, linux-arm-kernel
The NAND chips in MTD have a bunch of generic options that are needed in a
device tree. Add a YAML schemas for those.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
Documentation/devicetree/bindings/mtd/nand-controller.yaml | 131 +++++++-
1 file changed, 131 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/nand-controller.yaml
diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
new file mode 100644
index 000000000000..05b1afb34972
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NAND Chip and NAND Controller Generic Binding
+
+maintainers:
+ - Boris Brezillon <bbrezillon@kernel.org>
+ - Miquel Raynal <miquel.raynal@bootlin.com>
+ - Richard Weinberger <richard@nod.at>
+
+description: |
+ The NAND controller should be represented with its own DT node, and
+ all NAND chips attached to this controller should be defined as
+ children nodes of the NAND controller. This representation should be
+ enforced even for simple controllers supporting only one chip.
+
+ The ECC strength and ECC step size properties define the correction
+ capability of a controller. Together, they say a controller can
+ correct {strength} bit errors per {size} bytes.
+
+ The interpretation of these parameters is implementation-defined, so
+ not all implementations must support all possible
+ combinations. However, implementations are encouraged to further
+ specify the value(s) they support.
+
+properties:
+ $nodename:
+ pattern: "^nand-controller(@.*)?"
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ ranges: true
+
+patternProperties:
+ "^nand@[a-z0-9]$":
+ properties:
+ reg:
+ description:
+ Contains the native Ready/Busy IDs.
+
+ nand-ecc-mode:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/string
+ - enum: [ none, soft, hw, hw_syndrome, hw_oob_first, on-die ]
+ description:
+ Operation mode of the NAND ecc mode. soft_bch is deprecated
+ and should be replaced by soft and nand-ecc-algo
+
+ nand-ecc-algo:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/string
+ - enum: [ hamming, bch, rs ]
+ description:
+ Algorithm of NAND ECC.
+
+ nand-bus-width:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [ 8, 16 ]
+ - default: 8
+ description:
+ Bus width to the NAND chip
+
+ nand-on-flash-bbt:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Enable the on-flash Bad Block Table
+
+ nand-ecc-strength:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Number of bits to correct per ECC step.
+
+ nand-ecc-step-size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Number of data bytes covered by a single ECC step.
+
+ nand-ecc-maximize:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Whether or not the ECC strength should be maximized. The
+ maximum ECC strength is both controller and chip
+ dependent. The controller side has to select the ECC config
+ providing the best strength and taking the OOB area size
+ constraint into account. This is particularly useful when
+ only the in-band area is used by the upper layers, and you
+ want to make your NAND as reliable as possible.
+
+ nand-is-boot-medium:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Whether or not the NAND chip is a boot medium. Drivers might
+ use this information to select ECC algorithms supported by
+ the boot ROM or similar restrictions.
+
+ nand-rb:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ Contains the native Ready/Busy IDs.
+
+ required:
+ - reg
+
+required:
+ - "#address-cells"
+ - "#size-cells"
+
+examples:
+ - |
+ nand-controller {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* controller specific properties */
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-mode = "soft";
+ nand-ecc-algo = "bch";
+
+ /* controller specific properties */
+ };
+ };
base-commit: aa63f222af3e5991099ebcecca7c474d8285c7c4
--
git-series 0.9.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/4] dt-bindings: mtd: sunxi-nand: Add YAML schemas
2019-04-01 21:13 [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options Maxime Ripard
@ 2019-04-01 21:13 ` Maxime Ripard
2019-04-02 2:02 ` Rob Herring
2019-04-01 21:13 ` [PATCH 3/4] ARM: dts: sunxi: Conform to DT spec for NAND controller Maxime Ripard
` (3 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Maxime Ripard @ 2019-04-01 21:13 UTC (permalink / raw)
To: Boris Brezillon, Mark Rutland, Rob Herring, Frank Rowand, Miquel Raynal
Cc: Maxime Ripard, devicetree, Chen-Yu Tsai, linux-mtd, linux-arm-kernel
Switch the DT binding to a YAML schema to enable the DT validation.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
Documentation/devicetree/bindings/mtd/sunxi-nand.txt | 48 +-------------------------------------------
2 files changed, 81 insertions(+), 48 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml
delete mode 100644 Documentation/devicetree/bindings/mtd/sunxi-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml b/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml
new file mode 100644
index 000000000000..174294b9e9c6
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A10 NAND Controller Device Tree Bindings
+
+allOf:
+ - $ref: "nand-controller.yaml"
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+ - Maxime Ripard <maxime.ripard@bootlin.com>
+
+properties:
+ "#address-cells": true
+ "#size-cells": true
+
+ compatible:
+ const: allwinner,sun4i-a10-nand
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+ items:
+ - const: ahb
+ - const: mod
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: ahb
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ const: rxtx
+
+ pinctrl-names: true
+
+patternProperties:
+ "^pinctrl-[0-9]+$": true
+
+ "^nand@[a-z0-9]+$":
+ properties:
+ reg:
+ maxItems: 1
+
+ nand-ecc-mode: true
+ nand-ecc-step-size: true
+ nand-ecc-strength: true
+
+ allwinner,rb:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ Contains the native Ready/Busy IDs.
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+...
diff --git a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
deleted file mode 100644
index dcd5a5d80dc0..000000000000
--- a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-Allwinner NAND Flash Controller (NFC)
-
-Required properties:
-- compatible : "allwinner,sun4i-a10-nand".
-- reg : shall contain registers location and length for data and reg.
-- interrupts : shall define the nand controller interrupt.
-- #address-cells: shall be set to 1. Encode the nand CS.
-- #size-cells : shall be set to 0.
-- clocks : shall reference nand controller clocks.
-- clock-names : nand controller internal clock names. Shall contain :
- * "ahb" : AHB gating clock
- * "mod" : nand controller clock
-
-Optional properties:
-- dmas : shall reference DMA channel associated to the NAND controller.
-- dma-names : shall be "rxtx".
-
-Optional children nodes:
-Children nodes represent the available nand chips.
-
-Optional properties:
-- reset : phandle + reset specifier pair
-- reset-names : must contain "ahb"
-- allwinner,rb : shall contain the native Ready/Busy ids.
-- nand-ecc-mode : one of the supported ECC modes ("hw", "soft", "soft_bch" or
- "none")
-
-see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
-
-
-Examples:
-nfc: nand@1c03000 {
- compatible = "allwinner,sun4i-a10-nand";
- reg = <0x01c03000 0x1000>;
- interrupts = <0 37 1>;
- clocks = <&ahb_gates 13>, <&nand_clk>;
- clock-names = "ahb", "mod";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
-
- nand@0 {
- reg = <0>;
- allwinner,rb = <0>;
- nand-ecc-mode = "soft_bch";
- };
-};
--
git-series 0.9.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/4] ARM: dts: sunxi: Conform to DT spec for NAND controller
2019-04-01 21:13 [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options Maxime Ripard
2019-04-01 21:13 ` [PATCH 2/4] dt-bindings: mtd: sunxi-nand: Add YAML schemas Maxime Ripard
@ 2019-04-01 21:13 ` Maxime Ripard
2019-04-02 8:19 ` Miquel Raynal
2019-04-01 21:13 ` [PATCH 4/4] ARM: dts: sunxi: Remove useless address and size cells Maxime Ripard
` (2 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Maxime Ripard @ 2019-04-01 21:13 UTC (permalink / raw)
To: Boris Brezillon, Mark Rutland, Rob Herring, Frank Rowand, Miquel Raynal
Cc: Maxime Ripard, devicetree, Chen-Yu Tsai, linux-mtd, linux-arm-kernel
The NAND controller node name should be nand-controller and not nand as we
used previously according to the devicetree specification. Let's fix our
DTs.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 2 +-
arch/arm/boot/dts/sun5i.dtsi | 2 +-
arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index b16595a69cba..ef6ec526f394 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -267,7 +267,7 @@
#dma-cells = <2>;
};
- nfc: nand@1c03000 {
+ nfc: nand-controller@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <37>;
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index f69ab288678b..8dd49016eb1e 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -189,7 +189,7 @@
#dma-cells = <2>;
};
- nfc: nand@1c03000 {
+ nfc: nand-controller@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <37>;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 28e1045853fc..794c915f504b 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -333,7 +333,7 @@
#dma-cells = <2>;
};
- nfc: nand@1c03000 {
+ nfc: nand-controller@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index a0247b4b5a1e..c17bd7677ffb 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -161,7 +161,7 @@
#dma-cells = <1>;
};
- nfc: nand@1c03000 {
+ nfc: nand-controller@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
--
git-series 0.9.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/4] ARM: dts: sunxi: Remove useless address and size cells
2019-04-01 21:13 [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options Maxime Ripard
2019-04-01 21:13 ` [PATCH 2/4] dt-bindings: mtd: sunxi-nand: Add YAML schemas Maxime Ripard
2019-04-01 21:13 ` [PATCH 3/4] ARM: dts: sunxi: Conform to DT spec for NAND controller Maxime Ripard
@ 2019-04-01 21:13 ` Maxime Ripard
2019-04-02 8:19 ` Miquel Raynal
2019-04-02 1:58 ` [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options Rob Herring
2019-04-02 8:19 ` Miquel Raynal
4 siblings, 1 reply; 14+ messages in thread
From: Maxime Ripard @ 2019-04-01 21:13 UTC (permalink / raw)
To: Boris Brezillon, Mark Rutland, Rob Herring, Frank Rowand, Miquel Raynal
Cc: Maxime Ripard, devicetree, Chen-Yu Tsai, linux-mtd, linux-arm-kernel
The NAND chips in our DTs have address and size cells, even though they
don't have any child nodes. Remove them.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
arch/arm/boot/dts/sun5i-gr8-chip-pro.dts | 2 --
arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts | 2 --
2 files changed, 4 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
index 533a4ecc05e2..a32cde3e32eb 100644
--- a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
+++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
@@ -133,8 +133,6 @@
status = "okay";
nand@0 {
- #address-cells = <2>;
- #size-cells = <2>;
reg = <0>;
allwinner,rb = <0>;
nand-ecc-mode = "hw";
diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts b/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts
index 32cf1ab33aab..246dec5846a4 100644
--- a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts
+++ b/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts
@@ -34,8 +34,6 @@
/* 2Gb Macronix MX30LF2G18AC (3V) */
nand@0 {
- #address-cells = <1>;
- #size-cells = <1>;
reg = <0>;
allwinner,rb = <0>;
nand-ecc-mode = "hw";
--
git-series 0.9.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options
2019-04-01 21:13 [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options Maxime Ripard
` (2 preceding siblings ...)
2019-04-01 21:13 ` [PATCH 4/4] ARM: dts: sunxi: Remove useless address and size cells Maxime Ripard
@ 2019-04-02 1:58 ` Rob Herring
2019-04-02 6:15 ` Maxime Ripard
2019-04-02 8:19 ` Miquel Raynal
4 siblings, 1 reply; 14+ messages in thread
From: Rob Herring @ 2019-04-02 1:58 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, Chen-Yu Tsai, Boris Brezillon,
MTD Maling List, Miquel Raynal, Frank Rowand,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Mon, Apr 1, 2019 at 4:14 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> The NAND chips in MTD have a bunch of generic options that are needed in a
> device tree. Add a YAML schemas for those.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
> Documentation/devicetree/bindings/mtd/nand-controller.yaml | 131 +++++++-
> 1 file changed, 131 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/nand-controller.yaml
>
> diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
> new file mode 100644
> index 000000000000..05b1afb34972
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
> @@ -0,0 +1,131 @@
> +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NAND Chip and NAND Controller Generic Binding
> +
> +maintainers:
> + - Boris Brezillon <bbrezillon@kernel.org>
> + - Miquel Raynal <miquel.raynal@bootlin.com>
> + - Richard Weinberger <richard@nod.at>
> +
> +description: |
> + The NAND controller should be represented with its own DT node, and
> + all NAND chips attached to this controller should be defined as
> + children nodes of the NAND controller. This representation should be
> + enforced even for simple controllers supporting only one chip.
> +
> + The ECC strength and ECC step size properties define the correction
> + capability of a controller. Together, they say a controller can
> + correct {strength} bit errors per {size} bytes.
> +
> + The interpretation of these parameters is implementation-defined, so
> + not all implementations must support all possible
> + combinations. However, implementations are encouraged to further
> + specify the value(s) they support.
> +
> +properties:
> + $nodename:
> + pattern: "^nand-controller(@.*)?"
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> + ranges: true
'ranges' should not be here as nand chip addresses are not translatable.
> +
> +patternProperties:
> + "^nand@[a-z0-9]$":
> + properties:
> + reg:
> + description:
> + Contains the native Ready/Busy IDs.
> +
> + nand-ecc-mode:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/string
> + - enum: [ none, soft, hw, hw_syndrome, hw_oob_first, on-die ]
> + description:
> + Operation mode of the NAND ecc mode. soft_bch is deprecated
> + and should be replaced by soft and nand-ecc-algo
> +
> + nand-ecc-algo:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/string
> + - enum: [ hamming, bch, rs ]
> + description:
> + Algorithm of NAND ECC.
> +
> + nand-bus-width:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [ 8, 16 ]
> + - default: 8
> + description:
> + Bus width to the NAND chip
> +
> + nand-on-flash-bbt:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + Enable the on-flash Bad Block Table
> +
> + nand-ecc-strength:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Number of bits to correct per ECC step.
Is there a range we can define here? Certainly there's a minimum
values of at least 1.
> +
> + nand-ecc-step-size:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Number of data bytes covered by a single ECC step.
Same here.
> +
> + nand-ecc-maximize:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + Whether or not the ECC strength should be maximized. The
> + maximum ECC strength is both controller and chip
> + dependent. The controller side has to select the ECC config
> + providing the best strength and taking the OOB area size
> + constraint into account. This is particularly useful when
> + only the in-band area is used by the upper layers, and you
> + want to make your NAND as reliable as possible.
> +
> + nand-is-boot-medium:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + Whether or not the NAND chip is a boot medium. Drivers might
> + use this information to select ECC algorithms supported by
> + the boot ROM or similar restrictions.
> +
> + nand-rb:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description:
> + Contains the native Ready/Busy IDs.
> +
> + required:
> + - reg
> +
> +required:
> + - "#address-cells"
> + - "#size-cells"
> +
> +examples:
> + - |
> + nand-controller {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* controller specific properties */
> +
> + nand@0 {
> + reg = <0>;
> + nand-ecc-mode = "soft";
> + nand-ecc-algo = "bch";
> +
> + /* controller specific properties */
> + };
> + };
>
> base-commit: aa63f222af3e5991099ebcecca7c474d8285c7c4
> --
> git-series 0.9.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/4] dt-bindings: mtd: sunxi-nand: Add YAML schemas
2019-04-01 21:13 ` [PATCH 2/4] dt-bindings: mtd: sunxi-nand: Add YAML schemas Maxime Ripard
@ 2019-04-02 2:02 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2019-04-02 2:02 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, Chen-Yu Tsai, Boris Brezillon,
MTD Maling List, Miquel Raynal, Frank Rowand,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Mon, Apr 1, 2019 at 4:14 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> Switch the DT binding to a YAML schema to enable the DT validation.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
> Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
> Documentation/devicetree/bindings/mtd/sunxi-nand.txt | 48 +-------------------------------------------
> 2 files changed, 81 insertions(+), 48 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml
> delete mode 100644 Documentation/devicetree/bindings/mtd/sunxi-nand.txt
>
> diff --git a/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml b/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml
> new file mode 100644
> index 000000000000..174294b9e9c6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml
> @@ -0,0 +1,81 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Allwinner A10 NAND Controller Device Tree Bindings
> +
> +allOf:
> + - $ref: "nand-controller.yaml"
> +
> +maintainers:
> + - Chen-Yu Tsai <wens@csie.org>
> + - Maxime Ripard <maxime.ripard@bootlin.com>
> +
> +properties:
> + "#address-cells": true
> + "#size-cells": true
> +
> + compatible:
> + const: allwinner,sun4i-a10-nand
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Bus Clock
> + - description: Module Clock
> +
> + clock-names:
> + items:
> + - const: ahb
> + - const: mod
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + const: ahb
> +
> + dmas:
> + maxItems: 1
> +
> + dma-names:
> + const: rxtx
> +
> + pinctrl-names: true
> +
> +patternProperties:
> + "^pinctrl-[0-9]+$": true
> +
> + "^nand@[a-z0-9]+$":
> + properties:
> + reg:
> + maxItems: 1
min/max value of reg values?
> +
> + nand-ecc-mode: true
> + nand-ecc-step-size: true
> + nand-ecc-strength: true
Surely the h/w has further constraints on possible values?
> +
> + allwinner,rb:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description:
> + Contains the native Ready/Busy IDs.
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +...
> diff --git a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
> deleted file mode 100644
> index dcd5a5d80dc0..000000000000
> --- a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt
> +++ /dev/null
> @@ -1,48 +0,0 @@
> -Allwinner NAND Flash Controller (NFC)
> -
> -Required properties:
> -- compatible : "allwinner,sun4i-a10-nand".
> -- reg : shall contain registers location and length for data and reg.
> -- interrupts : shall define the nand controller interrupt.
> -- #address-cells: shall be set to 1. Encode the nand CS.
> -- #size-cells : shall be set to 0.
> -- clocks : shall reference nand controller clocks.
> -- clock-names : nand controller internal clock names. Shall contain :
> - * "ahb" : AHB gating clock
> - * "mod" : nand controller clock
> -
> -Optional properties:
> -- dmas : shall reference DMA channel associated to the NAND controller.
> -- dma-names : shall be "rxtx".
> -
> -Optional children nodes:
> -Children nodes represent the available nand chips.
> -
> -Optional properties:
> -- reset : phandle + reset specifier pair
> -- reset-names : must contain "ahb"
> -- allwinner,rb : shall contain the native Ready/Busy ids.
> -- nand-ecc-mode : one of the supported ECC modes ("hw", "soft", "soft_bch" or
> - "none")
> -
> -see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
> -
> -
> -Examples:
> -nfc: nand@1c03000 {
> - compatible = "allwinner,sun4i-a10-nand";
> - reg = <0x01c03000 0x1000>;
> - interrupts = <0 37 1>;
> - clocks = <&ahb_gates 13>, <&nand_clk>;
> - clock-names = "ahb", "mod";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
> -
> - nand@0 {
> - reg = <0>;
> - allwinner,rb = <0>;
> - nand-ecc-mode = "soft_bch";
> - };
> -};
> --
> git-series 0.9.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options
2019-04-02 1:58 ` [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options Rob Herring
@ 2019-04-02 6:15 ` Maxime Ripard
2019-04-02 7:59 ` Miquel Raynal
0 siblings, 1 reply; 14+ messages in thread
From: Maxime Ripard @ 2019-04-02 6:15 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree, Chen-Yu Tsai, Boris Brezillon,
MTD Maling List, Miquel Raynal, Frank Rowand,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Rob,
On Mon, Apr 01, 2019 at 08:58:49PM -0500, Rob Herring wrote:
> On Mon, Apr 1, 2019 at 4:14 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > The NAND chips in MTD have a bunch of generic options that are needed in a
> > device tree. Add a YAML schemas for those.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> > ---
> > Documentation/devicetree/bindings/mtd/nand-controller.yaml | 131 +++++++-
> > 1 file changed, 131 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mtd/nand-controller.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
> > new file mode 100644
> > index 000000000000..05b1afb34972
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
> > @@ -0,0 +1,131 @@
> > +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NAND Chip and NAND Controller Generic Binding
> > +
> > +maintainers:
> > + - Boris Brezillon <bbrezillon@kernel.org>
> > + - Miquel Raynal <miquel.raynal@bootlin.com>
> > + - Richard Weinberger <richard@nod.at>
> > +
> > +description: |
> > + The NAND controller should be represented with its own DT node, and
> > + all NAND chips attached to this controller should be defined as
> > + children nodes of the NAND controller. This representation should be
> > + enforced even for simple controllers supporting only one chip.
> > +
> > + The ECC strength and ECC step size properties define the correction
> > + capability of a controller. Together, they say a controller can
> > + correct {strength} bit errors per {size} bytes.
> > +
> > + The interpretation of these parameters is implementation-defined, so
> > + not all implementations must support all possible
> > + combinations. However, implementations are encouraged to further
> > + specify the value(s) they support.
> > +
> > +properties:
> > + $nodename:
> > + pattern: "^nand-controller(@.*)?"
> > +
> > + "#address-cells":
> > + const: 1
> > +
> > + "#size-cells":
> > + const: 0
> > +
> > + ranges: true
>
> 'ranges' should not be here as nand chip addresses are not translatable.
Apparently, some are. It was part of the original binding, hence why
it's there.
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/mtd/nand.txt#L16
> > +
> > +patternProperties:
> > + "^nand@[a-z0-9]$":
> > + properties:
> > + reg:
> > + description:
> > + Contains the native Ready/Busy IDs.
> > +
> > + nand-ecc-mode:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/string
> > + - enum: [ none, soft, hw, hw_syndrome, hw_oob_first, on-die ]
> > + description:
> > + Operation mode of the NAND ecc mode. soft_bch is deprecated
> > + and should be replaced by soft and nand-ecc-algo
> > +
> > + nand-ecc-algo:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/string
> > + - enum: [ hamming, bch, rs ]
> > + description:
> > + Algorithm of NAND ECC.
> > +
> > + nand-bus-width:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - enum: [ 8, 16 ]
> > + - default: 8
> > + description:
> > + Bus width to the NAND chip
> > +
> > + nand-on-flash-bbt:
> > + $ref: /schemas/types.yaml#/definitions/flag
> > + description:
> > + Enable the on-flash Bad Block Table
> > +
> > + nand-ecc-strength:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description:
> > + Number of bits to correct per ECC step.
>
> Is there a range we can define here? Certainly there's a minimum
> values of at least 1.
It doesn't look like there is from a quick grep. The DT seems to be in
the 4 - 32 range, but I'm not sure if it would make sense to have
something higher.
I'll let Miquel and Boris comment.
> > +
> > + nand-ecc-step-size:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description:
> > + Number of data bytes covered by a single ECC step.
>
> Same here.
Thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options
2019-04-02 6:15 ` Maxime Ripard
@ 2019-04-02 7:59 ` Miquel Raynal
0 siblings, 0 replies; 14+ messages in thread
From: Miquel Raynal @ 2019-04-02 7:59 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, Chen-Yu Tsai, Rob Herring,
MTD Maling List, Boris Brezillon, Frank Rowand,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Maxime,
> > > + nand-ecc-strength:
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + description:
> > > + Number of bits to correct per ECC step.
> >
> > Is there a range we can define here? Certainly there's a minimum
> > values of at least 1.
>
> It doesn't look like there is from a quick grep. The DT seems to be in
> the 4 - 32 range, but I'm not sure if it would make sense to have
> something higher.
>
> I'll let Miquel and Boris comment.
A value of zero would not have any meaning IMHO. 1 is definitely the
minimum (ECC Hamming algorithm). There is technically no maximum.
Thanks,
Miquèl
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options
2019-04-01 21:13 [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options Maxime Ripard
` (3 preceding siblings ...)
2019-04-02 1:58 ` [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options Rob Herring
@ 2019-04-02 8:19 ` Miquel Raynal
2019-04-02 8:49 ` Rob Herring
4 siblings, 1 reply; 14+ messages in thread
From: Miquel Raynal @ 2019-04-02 8:19 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, Rob Herring, Chen-Yu Tsai,
Boris Brezillon, linux-mtd, Frank Rowand, linux-arm-kernel
Hi Maxime,
Maxime Ripard <maxime.ripard@bootlin.com> wrote on Mon, 1 Apr 2019
23:13:53 +0200:
> The NAND chips in MTD have a bunch of generic options that are needed in a
> device tree. Add a YAML schemas for those.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
> Documentation/devicetree/bindings/mtd/nand-controller.yaml | 131 +++++++-
> 1 file changed, 131 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/nand-controller.yaml
>
> diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
> new file mode 100644
> index 000000000000..05b1afb34972
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
> @@ -0,0 +1,131 @@
> +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NAND Chip and NAND Controller Generic Binding
> +
> +maintainers:
> + - Boris Brezillon <bbrezillon@kernel.org>
Unfortunately Boris is leaving.
> + - Miquel Raynal <miquel.raynal@bootlin.com>
> + - Richard Weinberger <richard@nod.at>
Is this really needed? There is already a section for that purpose in
MAINTAINERS.
> +
> +description: |
> + The NAND controller should be represented with its own DT node, and
> + all NAND chips attached to this controller should be defined as
> + children nodes of the NAND controller. This representation should be
> + enforced even for simple controllers supporting only one chip.
> +
> + The ECC strength and ECC step size properties define the correction
> + capability of a controller. Together, they say a controller can
> + correct {strength} bit errors per {size} bytes.
Not exactly. The driver knows what the controller's ECC engine is
capable of.
The NAND chip has some minimum requirements in terms of correction. One
may use a softer correction, at his own risks though. The controller
has a range of possible corrections too which are not part of the DT
neither. These two properties are set to force the user desired
correction.
> +
> + The interpretation of these parameters is implementation-defined, so
> + not all implementations must support all possible
> + combinations. However, implementations are encouraged to further
> + specify the value(s) they support.
> +
> +properties:
> + $nodename:
> + pattern: "^nand-controller(@.*)?"
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> + ranges: true
> +
> +patternProperties:
> + "^nand@[a-z0-9]$":
> + properties:
> + reg:
> + description:
> + Contains the native Ready/Busy IDs.
> +
> + nand-ecc-mode:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/string
> + - enum: [ none, soft, hw, hw_syndrome, hw_oob_first, on-die ]
> + description:
> + Operation mode of the NAND ecc mode. soft_bch is deprecated
> + and should be replaced by soft and nand-ecc-algo
What about "Desired ECC engine, either hardware (most of the time embedded in the NAND controller) or software correction (Linux will handle the calculations)."
> +
> + nand-ecc-algo:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/string
> + - enum: [ hamming, bch, rs ]
> + description:
> + Algorithm of NAND ECC.
This is also a user desire more than a hardware limitation.
And this is not needed if nand-ecc-mode = "none" or when the ECC engine
does not handle more than one algorithm (ie. old engines only support
Hamming correction, if one chooses nand-ecc-mode = 'hw', there is no
need for a nand-ecc-algo property).
> +
> + nand-bus-width:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [ 8, 16 ]
> + - default: 8
> + description:
> + Bus width to the NAND chip
> +
> + nand-on-flash-bbt:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + Enable the on-flash Bad Block Table
It is not actually enabling anything, but Linux will search the device
for a a bad block table and if it does not find it, will create one and
update it.
> +
> + nand-ecc-strength:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Number of bits to correct per ECC step.
Maximum number of bits that can be corrected per ECC step ?
> +
> + nand-ecc-step-size:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Number of data bytes covered by a single ECC step.
> +
> + nand-ecc-maximize:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + Whether or not the ECC strength should be maximized. The
> + maximum ECC strength is both controller and chip
> + dependent. The controller side has to select the ECC config
> + providing the best strength and taking the OOB area size
s/The controller side/The ECC engine/ ?
> + constraint into account. This is particularly useful when
Double space here?
> + only the in-band area is used by the upper layers, and you
> + want to make your NAND as reliable as possible.
> +
> + nand-is-boot-medium:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + Whether or not the NAND chip is a boot medium. Drivers might
> + use this information to select ECC algorithms supported by
> + the boot ROM or similar restrictions.
> +
> + nand-rb:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description:
> + Contains the native Ready/Busy IDs.
> +
> + required:
> + - reg
> +
> +required:
> + - "#address-cells"
> + - "#size-cells"
> +
> +examples:
> + - |
> + nand-controller {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* controller specific properties */
> +
> + nand@0 {
> + reg = <0>;
> + nand-ecc-mode = "soft";
> + nand-ecc-algo = "bch";
> +
> + /* controller specific properties */
> + };
What about partitions? Shall they be described here?
> + };
>
> base-commit: aa63f222af3e5991099ebcecca7c474d8285c7c4
Thanks for doing that!
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/4] ARM: dts: sunxi: Conform to DT spec for NAND controller
2019-04-01 21:13 ` [PATCH 3/4] ARM: dts: sunxi: Conform to DT spec for NAND controller Maxime Ripard
@ 2019-04-02 8:19 ` Miquel Raynal
0 siblings, 0 replies; 14+ messages in thread
From: Miquel Raynal @ 2019-04-02 8:19 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, Rob Herring, Chen-Yu Tsai,
Boris Brezillon, linux-mtd, Frank Rowand, linux-arm-kernel
Hi Maxime,
Maxime Ripard <maxime.ripard@bootlin.com> wrote on Mon, 1 Apr 2019
23:13:55 +0200:
> The NAND controller node name should be nand-controller and not nand as we
> used previously according to the devicetree specification. Let's fix our
> DTs.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Thanks,
Miquèl
______________________________________________________
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 4/4] ARM: dts: sunxi: Remove useless address and size cells
2019-04-01 21:13 ` [PATCH 4/4] ARM: dts: sunxi: Remove useless address and size cells Maxime Ripard
@ 2019-04-02 8:19 ` Miquel Raynal
2019-04-02 11:11 ` Maxime Ripard
0 siblings, 1 reply; 14+ messages in thread
From: Miquel Raynal @ 2019-04-02 8:19 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, Rob Herring, Chen-Yu Tsai,
Boris Brezillon, linux-mtd, Frank Rowand, linux-arm-kernel
Hi Maxime,
Maxime Ripard <maxime.ripard@bootlin.com> wrote on Mon, 1 Apr 2019
23:13:56 +0200:
> The NAND chips in our DTs have address and size cells, even though they
> don't have any child nodes. Remove them.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
> arch/arm/boot/dts/sun5i-gr8-chip-pro.dts | 2 --
> arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts | 2 --
> 2 files changed, 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
> index 533a4ecc05e2..a32cde3e32eb 100644
> --- a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
> +++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
> @@ -133,8 +133,6 @@
> status = "okay";
>
> nand@0 {
> - #address-cells = <2>;
> - #size-cells = <2>;
> reg = <0>;
> allwinner,rb = <0>;
> nand-ecc-mode = "hw";
> diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts b/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts
> index 32cf1ab33aab..246dec5846a4 100644
> --- a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts
> +++ b/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts
> @@ -34,8 +34,6 @@
>
> /* 2Gb Macronix MX30LF2G18AC (3V) */
> nand@0 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> reg = <0>;
> allwinner,rb = <0>;
> nand-ecc-mode = "hw";
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Thanks,
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options
2019-04-02 8:19 ` Miquel Raynal
@ 2019-04-02 8:49 ` Rob Herring
2019-04-02 8:56 ` Miquel Raynal
0 siblings, 1 reply; 14+ messages in thread
From: Rob Herring @ 2019-04-02 8:49 UTC (permalink / raw)
To: Miquel Raynal
Cc: Mark Rutland, devicetree, Maxime Ripard, Chen-Yu Tsai,
Boris Brezillon, MTD Maling List, Frank Rowand,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Tue, Apr 2, 2019 at 3:19 AM Miquel Raynal <miquel.raynal@bootlin.com> wrote:
>
> Hi Maxime,
>
> Maxime Ripard <maxime.ripard@bootlin.com> wrote on Mon, 1 Apr 2019
> 23:13:53 +0200:
>
> > The NAND chips in MTD have a bunch of generic options that are needed in a
> > device tree. Add a YAML schemas for those.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> > ---
> > Documentation/devicetree/bindings/mtd/nand-controller.yaml | 131 +++++++-
> > 1 file changed, 131 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mtd/nand-controller.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
> > new file mode 100644
> > index 000000000000..05b1afb34972
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
> > @@ -0,0 +1,131 @@
> > +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NAND Chip and NAND Controller Generic Binding
> > +
> > +maintainers:
> > + - Boris Brezillon <bbrezillon@kernel.org>
>
> Unfortunately Boris is leaving.
>
> > + - Miquel Raynal <miquel.raynal@bootlin.com>
> > + - Richard Weinberger <richard@nod.at>
>
> Is this really needed? There is already a section for that purpose in
> MAINTAINERS.
Yes, because MAINTAINERS is a kernel file and bindings are somewhat
independent. And I found most binding files don't have a maintainer
(other than me as default).
If we ever go to per subsystem/directory MAiNTAiNERS files, then we
can easily generate one from bindings for the kernel.
Rob
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options
2019-04-02 8:49 ` Rob Herring
@ 2019-04-02 8:56 ` Miquel Raynal
0 siblings, 0 replies; 14+ messages in thread
From: Miquel Raynal @ 2019-04-02 8:56 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree, Maxime Ripard, Chen-Yu Tsai,
Boris Brezillon, MTD Maling List, Frank Rowand,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Rob,
Rob Herring <robh+dt@kernel.org> wrote on Tue, 2 Apr 2019 03:49:41
-0500:
> On Tue, Apr 2, 2019 at 3:19 AM Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> >
> > Hi Maxime,
> >
> > Maxime Ripard <maxime.ripard@bootlin.com> wrote on Mon, 1 Apr 2019
> > 23:13:53 +0200:
> >
> > > The NAND chips in MTD have a bunch of generic options that are needed in a
> > > device tree. Add a YAML schemas for those.
> > >
> > > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> > > ---
> > > Documentation/devicetree/bindings/mtd/nand-controller.yaml | 131 +++++++-
> > > 1 file changed, 131 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/mtd/nand-controller.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
> > > new file mode 100644
> > > index 000000000000..05b1afb34972
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
> > > @@ -0,0 +1,131 @@
> > > +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: NAND Chip and NAND Controller Generic Binding
> > > +
> > > +maintainers:
> > > + - Boris Brezillon <bbrezillon@kernel.org>
> >
> > Unfortunately Boris is leaving.
> >
> > > + - Miquel Raynal <miquel.raynal@bootlin.com>
> > > + - Richard Weinberger <richard@nod.at>
> >
> > Is this really needed? There is already a section for that purpose in
> > MAINTAINERS.
>
> Yes, because MAINTAINERS is a kernel file and bindings are somewhat
> independent. And I found most binding files don't have a maintainer
> (other than me as default).
I know DT and bindings are a bit specific but they are still in the
kernel sources and right now in MAINTAINERS, under the MTD subsystem
entry there is:
F: Documentation/devicetree/bindings/mtd/
What I am saying is that this list is a duplicate and people will
simply forget about it so it won't be updated naturally.
>
> If we ever go to per subsystem/directory MAiNTAiNERS files, then we
> can easily generate one from bindings for the kernel.
>
> Rob
Thanks,
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 4/4] ARM: dts: sunxi: Remove useless address and size cells
2019-04-02 8:19 ` Miquel Raynal
@ 2019-04-02 11:11 ` Maxime Ripard
0 siblings, 0 replies; 14+ messages in thread
From: Maxime Ripard @ 2019-04-02 11:11 UTC (permalink / raw)
To: Miquel Raynal
Cc: Mark Rutland, devicetree, Rob Herring, Chen-Yu Tsai,
Boris Brezillon, linux-mtd, Frank Rowand, linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 1663 bytes --]
On Tue, Apr 02, 2019 at 10:19:52AM +0200, Miquel Raynal wrote:
> Hi Maxime,
>
> Maxime Ripard <maxime.ripard@bootlin.com> wrote on Mon, 1 Apr 2019
> 23:13:56 +0200:
>
> > The NAND chips in our DTs have address and size cells, even though they
> > don't have any child nodes. Remove them.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> > ---
> > arch/arm/boot/dts/sun5i-gr8-chip-pro.dts | 2 --
> > arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts | 2 --
> > 2 files changed, 4 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
> > index 533a4ecc05e2..a32cde3e32eb 100644
> > --- a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
> > +++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
> > @@ -133,8 +133,6 @@
> > status = "okay";
> >
> > nand@0 {
> > - #address-cells = <2>;
> > - #size-cells = <2>;
> > reg = <0>;
> > allwinner,rb = <0>;
> > nand-ecc-mode = "hw";
> > diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts b/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts
> > index 32cf1ab33aab..246dec5846a4 100644
> > --- a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts
> > +++ b/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts
> > @@ -34,8 +34,6 @@
> >
> > /* 2Gb Macronix MX30LF2G18AC (3V) */
> > nand@0 {
> > - #address-cells = <1>;
> > - #size-cells = <1>;
> > reg = <0>;
> > allwinner,rb = <0>;
> > nand-ecc-mode = "hw";
>
>
> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Applied 3 and 4, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2019-04-02 11:12 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-01 21:13 [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options Maxime Ripard
2019-04-01 21:13 ` [PATCH 2/4] dt-bindings: mtd: sunxi-nand: Add YAML schemas Maxime Ripard
2019-04-02 2:02 ` Rob Herring
2019-04-01 21:13 ` [PATCH 3/4] ARM: dts: sunxi: Conform to DT spec for NAND controller Maxime Ripard
2019-04-02 8:19 ` Miquel Raynal
2019-04-01 21:13 ` [PATCH 4/4] ARM: dts: sunxi: Remove useless address and size cells Maxime Ripard
2019-04-02 8:19 ` Miquel Raynal
2019-04-02 11:11 ` Maxime Ripard
2019-04-02 1:58 ` [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options Rob Herring
2019-04-02 6:15 ` Maxime Ripard
2019-04-02 7:59 ` Miquel Raynal
2019-04-02 8:19 ` Miquel Raynal
2019-04-02 8:49 ` Rob Herring
2019-04-02 8:56 ` Miquel Raynal
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