From: Kishon Vijay Abraham I <kishon@ti.com>
To: <devicetree@vger.kernel.org>, <linux-doc@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-omap@vger.kernel.org>, <linux-pci@vger.kernel.org>
Cc: <rogerq@ti.com>, <balajitk@ti.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
Bjorn Helgaas <bhelgaas@google.com>, Marek Vasut <marex@denx.de>
Subject: [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU
Date: Tue, 6 May 2014 19:03:52 +0530 [thread overview]
Message-ID: <1399383244-14556-7-git-send-email-kishon@ti.com> (raw)
In-Reply-To: <1399383244-14556-1-git-send-email-kishon@ti.com>
In DRA7, the cpu sees 32bit address, but the pcie controller can see only 28bit
address. So whenever the cpu issues a read/write request, the 4 most
significant bits are used by L3 to determine the target controller.
For example, the cpu reserves 0x2000_0000 - 0x2FFF_FFFF for PCIe controller but
the PCIe controller will see only (0x000_0000 - 0xFFF_FFF). So for programming
the outbound translation window the *base* should be programmed as 0x000_0000.
Whenever we try to write to say 0x2000_0000, it will be translated to whatever
we have programmed in the translation window with base as 0x000_0000.
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
---
.../devicetree/bindings/pci/designware-pcie.txt | 1 +
drivers/pci/host/pcie-designware.c | 39 ++++++++++++++------
drivers/pci/host/pcie-designware.h | 1 +
3 files changed, 29 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index d6fae13..c574dd3 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -27,6 +27,7 @@ Optional properties for fsl,imx6q-pcie
- power-on-gpio: gpio pin number of power-enable signal
- wake-up-gpio: gpio pin number of incoming wakeup signal
- disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal
+- base-mask: address mask for the PCIe controller target port
Example:
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index c4e3732..243f148 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -463,6 +463,9 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
return -EINVAL;
}
+ if (of_property_read_u64(np, "base-mask", &pp->base_mask))
+ pp->base_mask = ~0x0ULL;
+
if (IS_ENABLED(CONFIG_PCI_MSI)) {
pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
MAX_MSI_IRQS, &msi_domain_ops,
@@ -502,12 +505,15 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
{
+ u64 cfg0_base;
+
+ cfg0_base = pp->cfg0_base & pp->base_mask;
/* Program viewport 0 : OUTBOUND : CFG0 */
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
PCIE_ATU_VIEWPORT);
- dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
+ dw_pcie_writel_rc(pp, cfg0_base, PCIE_ATU_LOWER_BASE);
+ dw_pcie_writel_rc(pp, (cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
+ dw_pcie_writel_rc(pp, cfg0_base + pp->config.cfg0_size - 1,
PCIE_ATU_LIMIT);
dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
@@ -517,13 +523,16 @@ static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
{
+ u64 cfg1_base;
+
+ cfg1_base = pp->cfg1_base & pp->base_mask;
/* Program viewport 1 : OUTBOUND : CFG1 */
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
PCIE_ATU_VIEWPORT);
dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
+ dw_pcie_writel_rc(pp, cfg1_base, PCIE_ATU_LOWER_BASE);
+ dw_pcie_writel_rc(pp, (cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
+ dw_pcie_writel_rc(pp, cfg1_base + pp->config.cfg1_size - 1,
PCIE_ATU_LIMIT);
dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
@@ -532,13 +541,16 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
{
+ u64 mem_base;
+
+ mem_base = pp->mem_base & pp->base_mask;
/* Program viewport 0 : OUTBOUND : MEM */
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
PCIE_ATU_VIEWPORT);
dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
+ dw_pcie_writel_rc(pp, mem_base, PCIE_ATU_LOWER_BASE);
+ dw_pcie_writel_rc(pp, (mem_base >> 32), PCIE_ATU_UPPER_BASE);
+ dw_pcie_writel_rc(pp, mem_base + pp->config.mem_size - 1,
PCIE_ATU_LIMIT);
dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
@@ -548,13 +560,16 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
{
+ u64 io_base;
+
+ io_base = pp->io_base & pp->base_mask;
/* Program viewport 1 : OUTBOUND : IO */
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
PCIE_ATU_VIEWPORT);
dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
+ dw_pcie_writel_rc(pp, io_base, PCIE_ATU_LOWER_BASE);
+ dw_pcie_writel_rc(pp, (io_base >> 32), PCIE_ATU_UPPER_BASE);
+ dw_pcie_writel_rc(pp, io_base + pp->config.io_size - 1,
PCIE_ATU_LIMIT);
dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index 3063b35..3fa12a6 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -35,6 +35,7 @@ struct pcie_port {
struct device *dev;
u8 root_bus_nr;
void __iomem *dbi_base;
+ u64 base_mask;
u64 cfg0_base;
void __iomem *va_cfg0_base;
u64 cfg1_base;
--
1.7.9.5
next prev parent reply other threads:[~2014-05-06 13:35 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-06 13:33 [PATCH 00/17] PCIe support for DRA7xx Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 01/17] phy: phy-omap-pipe3: Add support for PCIe PHY Kishon Vijay Abraham I
2014-05-14 12:57 ` Roger Quadros
2014-05-06 13:33 ` [PATCH 03/17] phy: ti-pipe3: add external clock " Kishon Vijay Abraham I
2014-05-14 13:16 ` Roger Quadros
2014-05-14 15:19 ` Kishon Vijay Abraham I
2014-05-14 15:34 ` Nishanth Menon
2014-05-15 9:15 ` Kishon Vijay Abraham I
2014-05-15 9:25 ` Roger Quadros
2014-05-15 11:46 ` Nishanth Menon
2014-05-15 11:59 ` Kishon Vijay Abraham I
2014-05-15 12:12 ` Nishanth Menon
2014-05-15 12:18 ` Kishon Vijay Abraham I
2014-05-15 12:33 ` Nishanth Menon
2014-05-15 12:42 ` Kishon Vijay Abraham I
2014-05-27 6:11 ` Kishon Vijay Abraham I
2014-05-28 1:54 ` Mike Turquette
2014-05-28 15:52 ` Nishanth Menon
2014-05-06 13:33 ` [PATCH 05/17] pci: host: pcie-dra7xx: add support for pcie-dra7xx controller Kishon Vijay Abraham I
2014-05-06 13:44 ` Marek Vasut
2014-05-07 8:21 ` Kishon Vijay Abraham I
2014-05-09 9:43 ` Pavel Machek
2014-05-06 13:54 ` Arnd Bergmann
2014-05-07 8:44 ` Kishon Vijay Abraham I
2014-05-07 9:30 ` Arnd Bergmann
2014-05-09 11:29 ` Kishon Vijay Abraham I
2014-05-06 16:35 ` Jason Gunthorpe
2014-05-07 9:22 ` Kishon Vijay Abraham I
2014-05-07 9:25 ` Arnd Bergmann
2014-05-08 8:56 ` Jingoo Han
2014-05-08 9:16 ` Arnd Bergmann
2014-05-06 13:33 ` Kishon Vijay Abraham I [this message]
2014-05-06 13:59 ` [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU Arnd Bergmann
2014-05-08 9:05 ` Jingoo Han
2014-05-08 9:18 ` Arnd Bergmann
2014-05-09 11:50 ` Kishon Vijay Abraham I
2014-05-12 1:44 ` Jingoo Han
2014-05-13 12:31 ` Kishon Vijay Abraham I
2014-05-13 12:47 ` Arnd Bergmann
2014-05-13 13:26 ` Kishon Vijay Abraham I
2014-05-13 13:27 ` Arnd Bergmann
2014-05-13 13:34 ` Arnd Bergmann
2014-05-14 5:44 ` Kishon Vijay Abraham I
2014-05-14 12:45 ` Arnd Bergmann
2014-05-14 15:04 ` Kishon Vijay Abraham I
2014-05-16 9:00 ` Kishon Vijay Abraham I
2014-05-19 12:45 ` Arnd Bergmann
2014-05-06 13:33 ` [PATCH 07/17] ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 08/17] ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 09/17] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 10/17] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 11/17] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY Kishon Vijay Abraham I
2014-05-14 13:23 ` Roger Quadros
2014-05-14 15:19 ` Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 12/17] ARM: dts: dra7: Add dt data for PCIe PHY control module Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 13/17] ARM: dts: dra7: Add dt data for PCIe PHY Kishon Vijay Abraham I
2014-05-06 13:34 ` [PATCH 14/17] ARM: dts: dra7: Add dt data for PCIe controller Kishon Vijay Abraham I
2014-05-06 13:34 ` [PATCH 15/17] ARM: OMAP: Enable PCI for DRA7 Kishon Vijay Abraham I
2014-05-06 13:34 ` [TEMP PATCH 16/17] pci: host: pcie-dra7xx: use reset framework APIs to reset PCIe Kishon Vijay Abraham I
2014-05-06 13:41 ` Dan Murphy
2014-05-06 13:34 ` [TEMP PATCH 17/17] ARM: dts: dra7: Add *resets* property for PCIe dt node Kishon Vijay Abraham I
2014-05-06 13:40 ` Dan Murphy
[not found] ` <1399383244-14556-3-git-send-email-kishon@ti.com>
2014-05-14 13:02 ` [PATCH 02/17] phy: omap-control: add external clock support for PCIe PHY Roger Quadros
[not found] ` <1399383244-14556-5-git-send-email-kishon@ti.com>
2014-05-14 13:20 ` [PATCH 04/17] phy: pipe3: insert delay to enumerate in GEN2 mode Roger Quadros
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