From: Kishon Vijay Abraham I <kishon@ti.com>
To: Marek Vasut <marex@denx.de>
Cc: <devicetree@vger.kernel.org>, <linux-doc@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-omap@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<rogerq@ti.com>, <balajitk@ti.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Mohit Kumar <mohit.kumar@st.com>,
Jingoo Han <jg1.han@samsung.com>
Subject: Re: [PATCH 05/17] pci: host: pcie-dra7xx: add support for pcie-dra7xx controller
Date: Wed, 7 May 2014 13:51:57 +0530 [thread overview]
Message-ID: <5369ED25.70101@ti.com> (raw)
In-Reply-To: <201405061544.28738.marex@denx.de>
Hi,
On Tuesday 06 May 2014 07:14 PM, Marek Vasut wrote:
> On Tuesday, May 06, 2014 at 03:33:51 PM, Kishon Vijay Abraham I wrote:
>> Added support for pcie controller in dra7xx. This driver re-uses
>> the designware core code that is already present in kernel.
>
> [...]
>
>> +#define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp)
>> +
>> +static inline u32 dra7xx_pcie_readl(void __iomem *base, u32 offset)
>
> Just pass struct dra7xx_pcie * instead of *base here , it will make the code
> below shorter.
>
>> +{
>> + return readl(base + offset);
>> +}
>> +
>> +static inline void dra7xx_pcie_writel(void __iomem *base, u32 offset, u32
>> value) +{
>
> DTTO.
>
>> + writel(value, base + offset);
>> +}
>> +
>> +static int dra7xx_pcie_link_up(struct pcie_port *pp)
>> +{
>> + struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
>> + u32 reg = dra7xx_pcie_readl(dra7xx->base, PCIECTRL_DRA7XX_CONF_PHY_CS);
>> +
>> + if (reg & LINK_UP)
>> + return true;
>> + return false;
>
> return reg & LINK_UP;
>
>> +}
>> +
>> +static int dra7xx_pcie_establish_link(struct pcie_port *pp)
>> +{
>> + u32 reg;
>> + int retries = 1000;
>> + struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
>> +
>> + if (dw_pcie_link_up(pp)) {
>> + dev_err(pp->dev, "link is already up\n");
>
> This will spew, since the .link_up (and thus this function) can be called
> repeatedly. The subsystem will query if the link is up via this function.
*dra7xx_pcie_establish_link* is not the callback for link_up function, so it's
actually called only once.
>
>> + return 0;
>> + }
>> +
>> + reg = dra7xx_pcie_readl(dra7xx->base, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
>> + reg |= LTSSM_EN;
>> + dra7xx_pcie_writel(dra7xx->base, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
>> +
>> + while (--retries) {
>
> Use retries--
>
>> + reg = dra7xx_pcie_readl(dra7xx->base,
>> + PCIECTRL_DRA7XX_CONF_PHY_CS);
>> + if (reg & LINK_UP)
>> + break;
>> + usleep_range(10, 20);
>> + }
>> +
>> + if (retries <= 0) {
>
> Then check if retries == 0 and retries can be unsigned int.
>
>> + dev_err(pp->dev, "link is not up\n");
>> + return -ETIMEDOUT;
>> + }
>> +
>> + return 0;
>> +}
> [...]
>> +static int __init dra7xx_pcie_probe(struct platform_device *pdev)
>> +{
>> + u32 reg;
>> + int ret;
>> + int irq;
>> + struct phy *phy;
>> + void __iomem *base;
>> + struct resource *res;
>> + struct dra7xx_pcie *dra7xx;
>> + struct device *dev = &pdev->dev;
>> +
>> + dra7xx = devm_kzalloc(&pdev->dev, sizeof(*dra7xx), GFP_KERNEL);
>> + if (!dra7xx)
>> + return -ENOMEM;
>> +
>> + irq = platform_get_irq(pdev, 0);
>> + if (irq < 0) {
>> + dev_err(dev, "missing IRQ resource\n");
>> + return -EINVAL;
>> + }
>> +
>> + ret = devm_request_irq(&pdev->dev, irq, dra7xx_pcie_irq_handler,
>> + IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
>> + if (ret) {
>> + dev_err(&pdev->dev, "failed to request irq\n");
>> + return ret;
>> + }
>> +
>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
>> + base = devm_ioremap_nocache(dev, res->start, resource_size(res));
>> + if (!base)
>> + return -ENOMEM;
>> +
>> + phy = devm_phy_get(dev, "pcie-phy");
>> + if (IS_ERR(phy))
>> + return PTR_ERR(phy);
>> +
>> + ret = phy_init(phy);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = phy_power_on(phy);
>> + if (ret < 0)
>> + goto err_power_on;
>> +
>> + dra7xx->base = base;
>> + dra7xx->phy = phy;
>> + dra7xx->dev = dev;
>> +
>> + pm_runtime_enable(&pdev->dev);
>> + ret = pm_runtime_get_sync(&pdev->dev);
>> + if (IS_ERR_VALUE(ret)) {
>> + dev_err(dev, "pm_runtime_get_sync failed\n");
>> + goto err_runtime_get;
>> + }
>> +
>> + reg = dra7xx_pcie_readl(dra7xx->base, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
>> + reg &= ~LTSSM_EN;
>> + dra7xx_pcie_writel(dra7xx->base, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
>
> platform_set_drvdata() should be here, before you add the port.
>
>> + ret = add_pcie_port(dra7xx, pdev);
>> + if (ret < 0)
>> + goto err_add_port;
>> +
>> + platform_set_drvdata(pdev, dra7xx);
Al-right. Will fix this and all your other comments.
Thanks
Kishon
next prev parent reply other threads:[~2014-05-07 8:22 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-06 13:33 [PATCH 00/17] PCIe support for DRA7xx Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 01/17] phy: phy-omap-pipe3: Add support for PCIe PHY Kishon Vijay Abraham I
2014-05-14 12:57 ` Roger Quadros
2014-05-06 13:33 ` [PATCH 03/17] phy: ti-pipe3: add external clock " Kishon Vijay Abraham I
2014-05-14 13:16 ` Roger Quadros
2014-05-14 15:19 ` Kishon Vijay Abraham I
2014-05-14 15:34 ` Nishanth Menon
2014-05-15 9:15 ` Kishon Vijay Abraham I
2014-05-15 9:25 ` Roger Quadros
2014-05-15 11:46 ` Nishanth Menon
2014-05-15 11:59 ` Kishon Vijay Abraham I
2014-05-15 12:12 ` Nishanth Menon
2014-05-15 12:18 ` Kishon Vijay Abraham I
2014-05-15 12:33 ` Nishanth Menon
2014-05-15 12:42 ` Kishon Vijay Abraham I
2014-05-27 6:11 ` Kishon Vijay Abraham I
2014-05-28 1:54 ` Mike Turquette
2014-05-28 15:52 ` Nishanth Menon
2014-05-06 13:33 ` [PATCH 05/17] pci: host: pcie-dra7xx: add support for pcie-dra7xx controller Kishon Vijay Abraham I
2014-05-06 13:44 ` Marek Vasut
2014-05-07 8:21 ` Kishon Vijay Abraham I [this message]
2014-05-09 9:43 ` Pavel Machek
2014-05-06 13:54 ` Arnd Bergmann
2014-05-07 8:44 ` Kishon Vijay Abraham I
2014-05-07 9:30 ` Arnd Bergmann
2014-05-09 11:29 ` Kishon Vijay Abraham I
2014-05-06 16:35 ` Jason Gunthorpe
2014-05-07 9:22 ` Kishon Vijay Abraham I
2014-05-07 9:25 ` Arnd Bergmann
2014-05-08 8:56 ` Jingoo Han
2014-05-08 9:16 ` Arnd Bergmann
2014-05-06 13:33 ` [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU Kishon Vijay Abraham I
2014-05-06 13:59 ` Arnd Bergmann
2014-05-08 9:05 ` Jingoo Han
2014-05-08 9:18 ` Arnd Bergmann
2014-05-09 11:50 ` Kishon Vijay Abraham I
2014-05-12 1:44 ` Jingoo Han
2014-05-13 12:31 ` Kishon Vijay Abraham I
2014-05-13 12:47 ` Arnd Bergmann
2014-05-13 13:26 ` Kishon Vijay Abraham I
2014-05-13 13:27 ` Arnd Bergmann
2014-05-13 13:34 ` Arnd Bergmann
2014-05-14 5:44 ` Kishon Vijay Abraham I
2014-05-14 12:45 ` Arnd Bergmann
2014-05-14 15:04 ` Kishon Vijay Abraham I
2014-05-16 9:00 ` Kishon Vijay Abraham I
2014-05-19 12:45 ` Arnd Bergmann
2014-05-06 13:33 ` [PATCH 07/17] ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 08/17] ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 09/17] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 10/17] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 11/17] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY Kishon Vijay Abraham I
2014-05-14 13:23 ` Roger Quadros
2014-05-14 15:19 ` Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 12/17] ARM: dts: dra7: Add dt data for PCIe PHY control module Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 13/17] ARM: dts: dra7: Add dt data for PCIe PHY Kishon Vijay Abraham I
2014-05-06 13:34 ` [PATCH 14/17] ARM: dts: dra7: Add dt data for PCIe controller Kishon Vijay Abraham I
2014-05-06 13:34 ` [PATCH 15/17] ARM: OMAP: Enable PCI for DRA7 Kishon Vijay Abraham I
2014-05-06 13:34 ` [TEMP PATCH 16/17] pci: host: pcie-dra7xx: use reset framework APIs to reset PCIe Kishon Vijay Abraham I
2014-05-06 13:41 ` Dan Murphy
2014-05-06 13:34 ` [TEMP PATCH 17/17] ARM: dts: dra7: Add *resets* property for PCIe dt node Kishon Vijay Abraham I
2014-05-06 13:40 ` Dan Murphy
[not found] ` <1399383244-14556-3-git-send-email-kishon@ti.com>
2014-05-14 13:02 ` [PATCH 02/17] phy: omap-control: add external clock support for PCIe PHY Roger Quadros
[not found] ` <1399383244-14556-5-git-send-email-kishon@ti.com>
2014-05-14 13:20 ` [PATCH 04/17] phy: pipe3: insert delay to enumerate in GEN2 mode Roger Quadros
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