From: Kishon Vijay Abraham I <kishon@ti.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Jingoo Han <jg1.han@samsung.com>,
"'Santosh Shilimkar'" <santosh.shilimkar@ti.com>,
<devicetree@vger.kernel.org>, <linux-doc@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-omap@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<rogerq@ti.com>, <balajitk@ti.com>,
"'Bjorn Helgaas'" <bhelgaas@google.com>,
"'Marek Vasut'" <marex@denx.de>
Subject: Re: [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU
Date: Wed, 14 May 2014 20:34:10 +0530 [thread overview]
Message-ID: <537385EA.2070302@ti.com> (raw)
In-Reply-To: <5281007.CFRjW0Yeu2@wuerfel>
Hi Arnd,
On Wednesday 14 May 2014 06:15 PM, Arnd Bergmann wrote:
> On Wednesday 14 May 2014 11:14:45 Kishon Vijay Abraham I wrote:
>> hi Arnd,
>>
>> On Tuesday 13 May 2014 07:04 PM, Arnd Bergmann wrote:
>>> On Tuesday 13 May 2014 15:27:46 Arnd Bergmann wrote:
>>>> On Tuesday 13 May 2014 18:56:23 Kishon Vijay Abraham I wrote:
>>>>>> If you have a case where the outbound translation is a 256MB (i.e. 28bit)
>>>>>> section of the CPU address space, that could be represented as
>>>>>>
>>>>>> ranges = <0x82000000 0 0 0xb0000000 0 0x10000000>;
>>>>>>
>>>>>> or
>>>>>>
>>>>>> ranges = <0x82000000 0 0xb0000000 0xb0000000 0 0x10000000>;
>>>>>>
>>>>>> depending on whether you want the BARs to be programmed using a low
>>>>>> address 0x0-0x0fffffff or an address matching the window
>>>>>> 0xb0000000-0xbfffffff.
>>>>>
>>>>> The problem is, for configuring the window starting at 0xb0000000, the ATU
>>>>> should be programmed 0x0000000 (the cpu address for it will be 0xb0000000 though).
>>>>>
>>>>
>>>> Then use the first of the two?
>>>>
>>>
>>> To clarify: using <0x82000000 0 0 0xb0000000 0 0x10000000> will give you
>>> a mem_offset of 0xb0000000, which should work just fine for this case.
>>>
>>> What I don't understand is why the ATU cares about whether the outbound
>>> address is 0x0000000 or 0xb0000000 if it just decodes the lower 28 bit
>>> anyway. Did you mean that we have to program the BARs using low addresses
>>> regardless of what is programmed in the ATU? That would make more sense,
>>> and it also matches what I suggested.
>>
>> No, It's not like it decodes only the lower 28bits. The BARs is programmed with
>> 32 bit value.
>>
>> My pcie dt node has
>> ranges = <0x00000800 0 0x20001000 0x20001000 0 0x00002000 /* CONFIG */
>> 0x81000000 0 0 0x20003000 0 0x00010000 /* IO */
>> 0x82000000 0 0x20013000 0x20013000 0 0xffed000>; /* MEM */
>>
>> Consider MEM address space..
>>
>> Here both PCI address and CPU address is 0x20013000. So when there is a write
>> to cpu addr 0x20013000 [writel(virt_addr(0x20013000)], we want it to be
>> translated to PCI addr 0x20013000. So in 'ATU', we would expect *base* to be
>> programmed to *0x20013000* and target to be programmed to *0x20013000*. But
>> that's not the case for DRA7xx. For DRA7xx *base* should be programmed to
>> *0x0013000* and target should be programmed to *0x20013000*.
>
> Ok, got it, thanks for your patience.
>
> I think this would best be modeled as a separate bus node that contains the
> restriction, like this:
>
> / {
> #address-cells = <1>; // or <2> if you support > 4GB address space
> #size-cells = <1>;
>
> soc {
> #address-cells <1>;
> #size-cells = <1>;
> ranges;
> dma-ranges;
>
> ... // all normal devices
>
> axi@20000000 {
> #size-cells = <1>;
> #address-cells = <1>;
> dma-ranges; // can access all 4GB outbound
> ranges = <0 0x20000000 0x10000000>; // 28-bit bus
>
> pci@0 {
> reg = <0x0 0x1000>, // internal regs
> <0x1000 0x2000>; // config space
> dma-ranges; // 32-bit outbound
> ranges = <0x81000000 0 0 0x3000 0 0x00010000 /* IO */
> 0x82000000 0 0x20013000 0x13000 0 0xffed000>; /* MEM */
> };
> };
> };
> };
Nice :-)
Thanks
Kishon
next prev parent reply other threads:[~2014-05-14 15:04 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-06 13:33 [PATCH 00/17] PCIe support for DRA7xx Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 01/17] phy: phy-omap-pipe3: Add support for PCIe PHY Kishon Vijay Abraham I
2014-05-14 12:57 ` Roger Quadros
2014-05-06 13:33 ` [PATCH 03/17] phy: ti-pipe3: add external clock " Kishon Vijay Abraham I
2014-05-14 13:16 ` Roger Quadros
2014-05-14 15:19 ` Kishon Vijay Abraham I
2014-05-14 15:34 ` Nishanth Menon
2014-05-15 9:15 ` Kishon Vijay Abraham I
2014-05-15 9:25 ` Roger Quadros
2014-05-15 11:46 ` Nishanth Menon
2014-05-15 11:59 ` Kishon Vijay Abraham I
2014-05-15 12:12 ` Nishanth Menon
2014-05-15 12:18 ` Kishon Vijay Abraham I
2014-05-15 12:33 ` Nishanth Menon
2014-05-15 12:42 ` Kishon Vijay Abraham I
2014-05-27 6:11 ` Kishon Vijay Abraham I
2014-05-28 1:54 ` Mike Turquette
2014-05-28 15:52 ` Nishanth Menon
2014-05-06 13:33 ` [PATCH 05/17] pci: host: pcie-dra7xx: add support for pcie-dra7xx controller Kishon Vijay Abraham I
2014-05-06 13:44 ` Marek Vasut
2014-05-07 8:21 ` Kishon Vijay Abraham I
2014-05-09 9:43 ` Pavel Machek
2014-05-06 13:54 ` Arnd Bergmann
2014-05-07 8:44 ` Kishon Vijay Abraham I
2014-05-07 9:30 ` Arnd Bergmann
2014-05-09 11:29 ` Kishon Vijay Abraham I
2014-05-06 16:35 ` Jason Gunthorpe
2014-05-07 9:22 ` Kishon Vijay Abraham I
2014-05-07 9:25 ` Arnd Bergmann
2014-05-08 8:56 ` Jingoo Han
2014-05-08 9:16 ` Arnd Bergmann
2014-05-06 13:33 ` [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU Kishon Vijay Abraham I
2014-05-06 13:59 ` Arnd Bergmann
2014-05-08 9:05 ` Jingoo Han
2014-05-08 9:18 ` Arnd Bergmann
2014-05-09 11:50 ` Kishon Vijay Abraham I
2014-05-12 1:44 ` Jingoo Han
2014-05-13 12:31 ` Kishon Vijay Abraham I
2014-05-13 12:47 ` Arnd Bergmann
2014-05-13 13:26 ` Kishon Vijay Abraham I
2014-05-13 13:27 ` Arnd Bergmann
2014-05-13 13:34 ` Arnd Bergmann
2014-05-14 5:44 ` Kishon Vijay Abraham I
2014-05-14 12:45 ` Arnd Bergmann
2014-05-14 15:04 ` Kishon Vijay Abraham I [this message]
2014-05-16 9:00 ` Kishon Vijay Abraham I
2014-05-19 12:45 ` Arnd Bergmann
2014-05-06 13:33 ` [PATCH 07/17] ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 08/17] ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 09/17] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 10/17] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 11/17] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY Kishon Vijay Abraham I
2014-05-14 13:23 ` Roger Quadros
2014-05-14 15:19 ` Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 12/17] ARM: dts: dra7: Add dt data for PCIe PHY control module Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 13/17] ARM: dts: dra7: Add dt data for PCIe PHY Kishon Vijay Abraham I
2014-05-06 13:34 ` [PATCH 14/17] ARM: dts: dra7: Add dt data for PCIe controller Kishon Vijay Abraham I
2014-05-06 13:34 ` [PATCH 15/17] ARM: OMAP: Enable PCI for DRA7 Kishon Vijay Abraham I
2014-05-06 13:34 ` [TEMP PATCH 16/17] pci: host: pcie-dra7xx: use reset framework APIs to reset PCIe Kishon Vijay Abraham I
2014-05-06 13:41 ` Dan Murphy
2014-05-06 13:34 ` [TEMP PATCH 17/17] ARM: dts: dra7: Add *resets* property for PCIe dt node Kishon Vijay Abraham I
2014-05-06 13:40 ` Dan Murphy
[not found] ` <1399383244-14556-3-git-send-email-kishon@ti.com>
2014-05-14 13:02 ` [PATCH 02/17] phy: omap-control: add external clock support for PCIe PHY Roger Quadros
[not found] ` <1399383244-14556-5-git-send-email-kishon@ti.com>
2014-05-14 13:20 ` [PATCH 04/17] phy: pipe3: insert delay to enumerate in GEN2 mode Roger Quadros
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