From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Gregory Clement <gregory.clement@bootlin.com>,
Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: <devicetree@vger.kernel.org>, Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
linux-pci@vger.kernel.org, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Antoine Tenart <antoine.tenart@bootlin.com>,
Maxime Chevallier <maxime.chevallier@bootlin.com>,
Nadav Haklai <nadavh@marvell.com>,
Miquel Raynal <miquel.raynal@bootlin.com>
Subject: [PATCH v3 09/15] dt-bindings: PCI: aardvark: Describe the PHY property
Date: Tue, 8 Jan 2019 17:24:34 +0100 [thread overview]
Message-ID: <20190108162441.5278-10-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20190108162441.5278-1-miquel.raynal@bootlin.com>
Document the possibility to reference a PHY.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/aardvark-pci.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/aardvark-pci.txt b/Documentation/devicetree/bindings/pci/aardvark-pci.txt
index 9d19ebfea189..a440f182ccf8 100644
--- a/Documentation/devicetree/bindings/pci/aardvark-pci.txt
+++ b/Documentation/devicetree/bindings/pci/aardvark-pci.txt
@@ -21,6 +21,10 @@ contain the following properties:
define the mapping of the PCIe interface to interrupt numbers.
- bus-range: PCI bus numbers covered
+The following are optional properties:
+
+ - phys: the PCIe PHY handle
+
In addition, the Device Tree describing an Aardvark PCIe controller
must include a sub-node that describes the legacy interrupt controller
built into the PCIe controller. This sub-node must have the following
@@ -50,6 +54,7 @@ Example:
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
+ phys = <&comphy1 0>;
pcie_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
--
2.19.1
next prev parent reply other threads:[~2019-01-08 16:25 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-08 16:24 [PATCH v3 00/15] Bring suspend to RAM support to PCIe Aardvark driver Miquel Raynal
2019-01-08 16:24 ` [PATCH v3 01/15] PCI: aardvark: Enlarge PIO timeout Miquel Raynal
2019-01-08 16:24 ` [PATCH v3 02/15] PCI: aardvark: Configure more registers in the configuration helper Miquel Raynal
2019-01-08 16:24 ` [PATCH v3 03/15] PCI: aardvark: Add clock support Miquel Raynal
2019-01-08 16:24 ` [PATCH v3 04/15] PCI: aardvark: Add PHY support Miquel Raynal
2019-01-08 16:24 ` [PATCH v3 05/15] PCI: aardvark: Add PCIe warm reset support Miquel Raynal
2019-01-08 16:24 ` [PATCH v3 06/15] PCI: aardvark: Add external reset GPIO support Miquel Raynal
2019-01-08 16:24 ` [PATCH v3 07/15] PCI: aardvark: Add suspend to RAM support Miquel Raynal
2019-01-08 16:24 ` [PATCH v3 08/15] dt-bindings: PCI: aardvark: Describe the clocks property Miquel Raynal
2019-01-08 16:24 ` Miquel Raynal [this message]
2019-01-08 16:24 ` [PATCH v3 10/15] dt-bindings: PCI: aardvark: Describe the PCIe endpoint card reset pins Miquel Raynal
2019-01-15 20:13 ` Rob Herring
2019-01-08 16:24 ` [PATCH v3 11/15] dt-bindings: PCI: aardvark: Describe the reset-gpios property Miquel Raynal
2019-01-08 16:24 ` [PATCH v3 12/15] ARM64: dts: marvell: armada-37xx: declare PCIe clock Miquel Raynal
2019-01-08 16:24 ` [PATCH v3 13/15] ARM64: dts: marvell: armada-3720-espressobin: declare PCIe PHY Miquel Raynal
2019-02-06 14:17 ` Gregory CLEMENT
2019-01-08 16:24 ` [PATCH v3 14/15] ARM64: dts: marvell: armada-37xx: declare PCIe reset pin Miquel Raynal
2019-02-06 11:11 ` Gregory CLEMENT
2019-01-08 16:24 ` [PATCH v3 15/15] ARM64: dts: marvell: armada-3720-espressobin: declare PCIe warm " Miquel Raynal
2019-02-06 11:12 ` Gregory CLEMENT
2019-01-18 16:51 ` [PATCH v3 00/15] Bring suspend to RAM support to PCIe Aardvark driver Gregory CLEMENT
2019-01-20 15:16 ` Miquel Raynal
2019-01-23 17:05 ` Lorenzo Pieralisi
2019-01-25 10:05 ` Miquel Raynal
2019-01-25 12:40 ` Lorenzo Pieralisi
2019-01-25 12:57 ` Miquel Raynal
2019-01-25 17:38 ` Lorenzo Pieralisi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190108162441.5278-10-miquel.raynal@bootlin.com \
--to=miquel.raynal@bootlin.com \
--cc=andrew@lunn.ch \
--cc=antoine.tenart@bootlin.com \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=gregory.clement@bootlin.com \
--cc=jason@lakedaemon.net \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mark.rutland@arm.com \
--cc=maxime.chevallier@bootlin.com \
--cc=nadavh@marvell.com \
--cc=robh+dt@kernel.org \
--cc=sebastian.hesselbarth@gmail.com \
--cc=thomas.petazzoni@bootlin.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).