From: Bjorn Helgaas <helgaas@kernel.org>
To: Dilip Kota <eswara.kota@linux.intel.com>
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lorenzo.pieralisi@arm.com, andrew.murray@arm.com,
robh@kernel.org, martin.blumenstingl@googlemail.com,
linux-pci@vger.kernel.org, hch@infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
andriy.shevchenko@intel.com, cheol.yong.kim@intel.com,
chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com
Subject: Re: [PATCH v4 2/3] dwc: PCI: intel: PCIe RC controller driver
Date: Mon, 21 Oct 2019 12:17:36 -0500 [thread overview]
Message-ID: <20191021171736.GA233393@google.com> (raw)
In-Reply-To: <c46ba3f4187fe53807948b4f10996b89a75c492c.1571638827.git.eswara.kota@linux.intel.com>
On Mon, Oct 21, 2019 at 02:39:19PM +0800, Dilip Kota wrote:
> Add support to PCIe RC controller on Intel Gateway SoCs.
> PCIe controller is based of Synopsys DesignWare pci core.
>
> Intel PCIe driver requires Upconfig support, fast training
> sequence configuration and link speed change. So adding the
> respective helper functions in the pcie DesignWare framework.
> It also programs hardware autonomous speed during speed
> configuration so defining it in pci_regs.h.
>
> +static void intel_pcie_link_setup(struct intel_pcie_port *lpp)
> +{
> + u32 val;
> +
> + val = pcie_rc_cfg_rd(lpp, PCIE_CAP_OFST + PCI_EXP_LNKCAP);
> + lpp->max_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, val);
> + lpp->max_width = FIELD_GET(PCI_EXP_LNKCAP_MLW, val);
> +
> + val = pcie_rc_cfg_rd(lpp, PCIE_CAP_OFST + PCI_EXP_LNKCTL);
> +
> + val &= ~(PCI_EXP_LNKCTL_LD | PCI_EXP_LNKCTL_ASPMC);
> + val |= (PCI_EXP_LNKSTA_SLC << 16) | PCI_EXP_LNKCTL_CCC |
> + PCI_EXP_LNKCTL_RCB;
Link Control is only 16 bits wide, so "PCI_EXP_LNKSTA_SLC << 16"
wouldn't make sense. But I guess you're writing a device-specific
register that is not actually the Link Control as documented in PCIe
r5.0, sec 7.5.3.7, even though the bits are similar?
Likewise, PCI_EXP_LNKCTL_RCB is RO for Root Ports, but maybe you're
telling the device what it should advertise in its Link Control?
PCI_EXP_LNKCTL_CCC is RW. But doesn't it depend on the components on
both ends of the link? Do you know what device is at the other end?
I would have assumed that you'd have to start with CCC==0, which
should be most conservative, then set CCC=1 only if you know both ends
have a common clock.
> + pcie_rc_cfg_wr(lpp, val, PCIE_CAP_OFST + PCI_EXP_LNKCTL);
> +}
> +
> +static void intel_pcie_max_speed_setup(struct intel_pcie_port *lpp)
> +{
> + u32 reg, val;
> +
> + reg = pcie_rc_cfg_rd(lpp, PCIE_CAP_OFST + PCI_EXP_LNKCTL2);
> + switch (lpp->link_gen) {
> + case PCIE_LINK_SPEED_GEN1:
> + reg &= ~PCI_EXP_LNKCTL2_TLS;
> + reg |= PCI_EXP_LNKCTL2_HASD|
> + PCI_EXP_LNKCTL2_TLS_2_5GT;
> + break;
> + case PCIE_LINK_SPEED_GEN2:
> + reg &= ~PCI_EXP_LNKCTL2_TLS;
> + reg |= PCI_EXP_LNKCTL2_HASD|
> + PCI_EXP_LNKCTL2_TLS_5_0GT;
> + break;
> + case PCIE_LINK_SPEED_GEN3:
> + reg &= ~PCI_EXP_LNKCTL2_TLS;
> + reg |= PCI_EXP_LNKCTL2_HASD|
> + PCI_EXP_LNKCTL2_TLS_8_0GT;
> + break;
> + case PCIE_LINK_SPEED_GEN4:
> + reg &= ~PCI_EXP_LNKCTL2_TLS;
> + reg |= PCI_EXP_LNKCTL2_HASD|
> + PCI_EXP_LNKCTL2_TLS_16_0GT;
> + break;
> + default:
> + /* Use hardware capability */
> + val = pcie_rc_cfg_rd(lpp, PCIE_CAP_OFST + PCI_EXP_LNKCAP);
> + val = FIELD_GET(PCI_EXP_LNKCAP_SLS, val);
> + reg &= ~PCI_EXP_LNKCTL2_HASD;
> + reg |= val;
> + break;
> + }
> +
> + pcie_rc_cfg_wr(lpp, reg, PCIE_CAP_OFST + PCI_EXP_LNKCTL2);
> + dw_pcie_link_set_n_fts(&lpp->pci, lpp->n_fts);
There are other users of of_pci_get_max_link_speed() that look sort of
similar to this (dra7xx_pcie_establish_link(),
ks_pcie_set_link_speed(), tegra_pcie_prepare_host()). Do these *need*
to be different, or is there something that could be factored out?
> +}
> +
> +
> +
Remove extra blank lines here.
> +static void intel_pcie_port_logic_setup(struct intel_pcie_port *lpp)
> ...
> + /* Intel PCIe doesn't configure IO region, so configure
> + * viewport to not to access IO region during register
> + * read write operations.
> + */
This comment doesn't describe the code. Is there supposed to be some
code here that configures the viewport? Where do we tell the viewport
not to access IO?
I guess maybe this means something like "tell
dw_pcie_access_other_conf() not to program an outbound ATU for I/O"?
I don't know that structure well enough to write this in a way that
makes sense, but this code doesn't look like it's configuring any
viewports.
Please use usual multi-line comment style, i.e.,
/*
* Intel PCIe ...
*/
> + pci->num_viewport = data->num_viewport;
> + dev_info(dev, "Intel PCIe Root Complex Port %d init done\n", lpp->id);
> +
> + return ret;
> +}
next prev parent reply other threads:[~2019-10-21 17:17 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-21 6:39 [PATCH v4 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file Dilip Kota
2019-10-21 6:39 ` [PATCH v4 1/3] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller Dilip Kota
2019-10-21 11:19 ` Andrew Murray
2019-10-22 10:15 ` Dilip Kota
2019-10-24 20:31 ` Martin Blumenstingl
2019-10-29 7:53 ` Dilip Kota
2019-10-25 16:53 ` Rob Herring
2019-10-29 8:34 ` Dilip Kota
2019-10-31 10:51 ` Dilip Kota
2019-10-31 18:35 ` Rob Herring
2019-10-21 6:39 ` [PATCH v4 2/3] dwc: PCI: intel: PCIe RC controller driver Dilip Kota
2019-10-21 8:29 ` Gustavo Pimentel
2019-10-21 10:44 ` Dilip Kota
2019-10-22 10:18 ` Dilip Kota
2019-10-22 11:44 ` andriy.shevchenko
2019-10-25 9:01 ` Andrew Murray
2019-10-29 6:14 ` Dilip Kota
2019-10-21 13:03 ` Andrew Murray
2019-10-22 9:04 ` Dilip Kota
2019-10-25 9:09 ` Andrew Murray
2019-10-29 8:59 ` Dilip Kota
2019-11-01 10:59 ` Andrew Murray
2019-11-04 9:34 ` Dilip Kota
2019-11-04 10:47 ` Andrew Murray
2019-10-21 17:17 ` Bjorn Helgaas [this message]
2019-10-22 9:07 ` Dilip Kota
2019-10-22 13:09 ` Bjorn Helgaas
2019-10-29 7:45 ` Dilip Kota
2019-10-25 13:11 ` kbuild test robot
2019-10-25 13:11 ` [RFC PATCH] dwc: PCI: intel: intel_pcie_msi_init() can be static kbuild test robot
2019-10-21 6:39 ` [PATCH v4 3/3] pci: intel: Add sysfs attributes to configure pcie link Dilip Kota
2019-10-21 8:40 ` Gustavo Pimentel
2019-10-21 10:34 ` Dilip Kota
2019-10-21 13:38 ` Andrew Murray
2019-10-21 17:18 ` Bjorn Helgaas
2019-10-22 9:27 ` Dilip Kota
2019-10-22 12:59 ` Bjorn Helgaas
2019-10-29 9:31 ` Dilip Kota
2019-10-30 22:14 ` Bjorn Helgaas
2019-10-30 23:31 ` Rafael J. Wysocki
2019-10-31 2:56 ` Bjorn Helgaas
2019-10-31 9:13 ` Rafael J. Wysocki
2019-10-31 13:01 ` Bjorn Helgaas
2019-10-31 10:47 ` Dilip Kota
2019-10-31 13:22 ` Bjorn Helgaas
2019-11-01 5:47 ` Dilip Kota
2019-11-01 11:30 ` Andrew Murray
2019-10-29 10:42 ` Rafael J. Wysocki
2019-10-29 12:36 ` Bjorn Helgaas
2019-10-22 9:20 ` Dilip Kota
2019-10-25 9:34 ` Andrew Murray
2019-10-29 9:51 ` Dilip Kota
2019-10-21 8:08 ` [PATCH v4 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file Gustavo Pimentel
2019-10-21 8:31 ` Dilip Kota
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191021171736.GA233393@google.com \
--to=helgaas@kernel.org \
--cc=andrew.murray@arm.com \
--cc=andriy.shevchenko@intel.com \
--cc=cheol.yong.kim@intel.com \
--cc=chuanhua.lei@linux.intel.com \
--cc=devicetree@vger.kernel.org \
--cc=eswara.kota@linux.intel.com \
--cc=gustavo.pimentel@synopsys.com \
--cc=hch@infradead.org \
--cc=jingoohan1@gmail.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=martin.blumenstingl@googlemail.com \
--cc=qi-ming.wu@intel.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).