From: Rob Herring <robh@kernel.org> To: Bjorn Helgaas <bhelgaas@google.com>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: linux-pci@vger.kernel.org, Andy Gross <agross@kernel.org>, Binghui Wang <wangbinghui@hisilicon.com>, Bjorn Andersson <bjorn.andersson@linaro.org>, Dilip Kota <eswara.kota@linux.intel.com>, Fabio Estevam <festevam@gmail.com>, Gustavo Pimentel <gustavo.pimentel@synopsys.com>, Jerome Brunet <jbrunet@baylibre.com>, Jesper Nilsson <jesper.nilsson@axis.com>, Jingoo Han <jingoohan1@gmail.com>, Jonathan Chocron <jonnyc@amazon.com>, Jonathan Hunter <jonathanh@nvidia.com>, Kevin Hilman <khilman@baylibre.com>, Kishon Vijay Abraham I <kishon@ti.com>, Krzysztof Kozlowski <krzk@kernel.org>, Kukjin Kim <kgene@kernel.org>, Kunihiko Hayashi <hayashi.kunihiko@socionext.com>, Lucas Stach <l.stach@pengutronix.de>, Martin Blumenstingl <martin.blumenstingl@googlemail.com>, Masahiro Yamada <yamada.masahiro@socionext.com>, Murali Karicheri <m-karicheri2@ti.com>, Neil Armstrong <narmstrong@baylibre.com>, NXP Linux Team <linux-imx@nxp.com>, Pengutronix Kernel Team <kernel@pengutronix.de>, Pratyush Anand <pratyush.anand@gmail.com>, Richard Zhu <hongxing.zhu@nxp.com>, Sascha Hauer <s.hauer@pengutronix.de>, Shawn Guo <shawnguo@kernel.org>, Shawn Guo <shawn.guo@linaro.org>, Stanimir Varbanov <svarbanov@mm-sol.com>, Thierry Reding <thierry.reding@gmail.com>, Xiaowei Song <songxiaowei@hisilicon.com>, Yue Wang <yue.wang@Amlogic.com>, Marc Zyngier <maz@kernel.org>, linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 18/40] PCI: dwc: Remove storing of PCI resources Date: Thu, 20 Aug 2020 21:53:58 -0600 [thread overview] Message-ID: <20200821035420.380495-19-robh@kernel.org> (raw) In-Reply-To: <20200821035420.380495-1-robh@kernel.org> The PCI bridge resources are stored in pci_host_bridge.windows, so there's no need to store them in a DWC specific struct. There's also no need to parse the resources and store them a 2nd time as they are mainly used for one time setup of iATU windows. Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Jonathan Chocron <jonnyc@amazon.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Rob Herring <robh@kernel.org> --- drivers/pci/controller/dwc/pci-keystone.c | 8 ++++-- drivers/pci/controller/dwc/pcie-al.c | 7 ++--- .../pci/controller/dwc/pcie-designware-host.c | 27 +++++++------------ drivers/pci/controller/dwc/pcie-designware.h | 6 ----- 4 files changed, 19 insertions(+), 29 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index fd000384fd2a..d306914a1f93 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -400,10 +400,14 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) u32 num_viewport = ks_pcie->num_viewport; struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; - u64 start = pp->mem->start; - u64 end = pp->mem->end; + u64 start, end; + struct resource *mem; int i; + mem = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM)->res; + start = mem->start; + end = mem->end; + /* Disable BARs for inbound access */ ks_pcie_set_dbi_mode(ks_pcie); dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); diff --git a/drivers/pci/controller/dwc/pcie-al.c b/drivers/pci/controller/dwc/pcie-al.c index 59e33d3a8380..f973fbca90cf 100644 --- a/drivers/pci/controller/dwc/pcie-al.c +++ b/drivers/pci/controller/dwc/pcie-al.c @@ -260,6 +260,7 @@ static void al_pcie_config_prepare(struct al_pcie *pcie) u8 secondary_bus; u32 cfg_control; u32 reg; + struct resource *bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res; target_bus_cfg = &pcie->target_bus_cfg; @@ -273,13 +274,13 @@ static void al_pcie_config_prepare(struct al_pcie *pcie) target_bus_cfg->ecam_mask = ecam_bus_mask; /* This portion is taken from the cfg_target_bus reg */ target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask; - target_bus_cfg->reg_val = pp->busn->start & target_bus_cfg->reg_mask; + target_bus_cfg->reg_val = bus->start & target_bus_cfg->reg_mask; al_pcie_target_bus_set(pcie, target_bus_cfg->reg_val, target_bus_cfg->reg_mask); - secondary_bus = pp->busn->start + 1; - subordinate_bus = pp->busn->end; + secondary_bus = bus->start + 1; + subordinate_bus = bus->end; /* Set the valid values of secondary and subordinate buses */ cfg_control_offset = AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl + diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 0f348b951ec3..1e42345922d5 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -326,17 +326,9 @@ int dw_pcie_host_init(struct pcie_port *pp) resource_list_for_each_entry(win, &bridge->windows) { switch (resource_type(win->res)) { case IORESOURCE_IO: - pp->io = win->res; - pp->io->name = "I/O"; - pp->io_size = resource_size(pp->io); - pp->io_bus_addr = pp->io->start - win->offset; - pp->io_base = pci_pio_to_address(pp->io->start); - break; - case IORESOURCE_MEM: - pp->mem = win->res; - pp->mem->name = "MEM"; - pp->mem_size = resource_size(pp->mem); - pp->mem_bus_addr = pp->mem->start - win->offset; + pp->io_size = resource_size(win->res); + pp->io_bus_addr = win->res->start - win->offset; + pp->io_base = pci_pio_to_address(win->res->start); break; case 0: pp->cfg = win->res; @@ -345,9 +337,6 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->cfg0_base = pp->cfg->start; pp->cfg1_base = pp->cfg->start + pp->cfg0_size; break; - case IORESOURCE_BUS: - pp->busn = win->res; - break; } } @@ -361,8 +350,6 @@ int dw_pcie_host_init(struct pcie_port *pp) } } - pp->mem_base = pp->mem->start; - if (!pp->va_cfg0_base) { pp->va_cfg0_base = devm_pci_remap_cfgspace(dev, pp->cfg0_base, pp->cfg0_size); @@ -601,9 +588,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp) * ATU, so we should not program the ATU here. */ if (pp->bridge->child_ops == &dw_child_pcie_ops) { + struct resource_entry *entry = + resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); + dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, - PCIE_ATU_TYPE_MEM, pp->mem_base, - pp->mem_bus_addr, pp->mem_size); + PCIE_ATU_TYPE_MEM, entry->res->start, + entry->res->start - entry->offset, + resource_size(entry->res)); if (pci->num_viewport > 2) dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2, PCIE_ATU_TYPE_IO, pp->io_base, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 78243909d2c5..50225bf6a2b5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -175,13 +175,7 @@ struct pcie_port { resource_size_t io_base; phys_addr_t io_bus_addr; u32 io_size; - u64 mem_base; - phys_addr_t mem_bus_addr; - u32 mem_size; struct resource *cfg; - struct resource *io; - struct resource *mem; - struct resource *busn; int irq; const struct dw_pcie_host_ops *ops; int msi_irq; -- 2.25.1
next prev parent reply other threads:[~2020-08-21 3:55 UTC|newest] Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-08-21 3:53 [PATCH v2 00/40] PCI: dwc: Driver clean-ups Rob Herring 2020-08-21 3:53 ` [PATCH v2 01/40] PCI: Allow root and child buses to have different pci_ops Rob Herring 2020-08-21 3:53 ` [PATCH v2 02/40] PCI: dwc: Use DBI accessors instead of own config accessors Rob Herring 2020-08-21 3:53 ` [PATCH v2 03/40] PCI: dwc: Allow overriding bridge pci_ops Rob Herring 2021-08-08 15:13 ` Vidya Sagar 2021-08-09 14:52 ` Rob Herring 2020-08-21 3:53 ` [PATCH v2 04/40] PCI: dwc: Add a default pci_ops.map_bus for root port Rob Herring 2020-08-21 3:53 ` [PATCH v2 05/40] PCI: dwc: al: Use pci_ops for child config space accessors Rob Herring 2020-08-21 3:53 ` [PATCH v2 06/40] PCI: dwc: keystone: Use pci_ops for " Rob Herring 2020-08-21 3:53 ` [PATCH v2 07/40] PCI: dwc: tegra: Use pci_ops for root " Rob Herring 2020-08-21 3:53 ` [PATCH v2 08/40] PCI: dwc: meson: " Rob Herring 2020-08-21 3:53 ` [PATCH v2 09/40] PCI: dwc: kirin: " Rob Herring 2020-08-21 3:53 ` [PATCH v2 10/40] PCI: dwc: exynos: " Rob Herring 2020-08-21 3:53 ` [PATCH v2 11/40] PCI: dwc: histb: " Rob Herring 2020-08-21 3:53 ` [PATCH v2 12/40] PCI: dwc: Remove dwc specific config accessor ops Rob Herring 2020-08-21 3:53 ` [PATCH v2 13/40] PCI: dwc: Use generic config accessors Rob Herring 2020-08-21 3:53 ` [PATCH v2 14/40] PCI: Also call .add_bus() callback for root bus Rob Herring 2020-08-21 3:53 ` [PATCH v2 15/40] PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus Rob Herring 2020-08-21 3:53 ` [PATCH v2 16/40] PCI: dwc: Convert to use pci_host_probe() Rob Herring 2020-08-21 3:53 ` [PATCH v2 17/40] PCI: dwc: Remove root_bus pointer Rob Herring 2020-08-21 3:53 ` Rob Herring [this message] 2020-08-21 3:53 ` [PATCH v2 19/40] PCI: dwc: Simplify config space handling Rob Herring 2020-08-21 3:54 ` [PATCH v2 20/40] PCI: dwc/keystone: Drop duplicated 'num-viewport' Rob Herring 2020-08-21 3:54 ` [PATCH v2 21/40] PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() Rob Herring 2020-08-21 3:54 ` [PATCH v2 22/40] PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL Rob Herring 2020-08-21 3:54 ` [PATCH v2 23/40] PCI: dwc: Add a 'num_lanes' field to struct dw_pcie Rob Herring 2020-08-21 3:54 ` [PATCH v2 24/40] PCI: dwc: Ensure FAST_LINK_MODE is cleared Rob Herring 2020-08-21 3:54 ` [PATCH v2 25/40] PCI: dwc/meson: Drop the duplicate number of lanes setup Rob Herring 2020-08-21 3:54 ` [PATCH v2 26/40] PCI: dwc/meson: Drop unnecessary RC config space initialization Rob Herring 2020-08-21 3:54 ` [PATCH v2 27/40] PCI: dwc/meson: Rework PCI config and DW port logic register accesses Rob Herring 2020-08-21 3:54 ` [PATCH v2 28/40] PCI: dwc/imx6: Use common PCI register definitions Rob Herring 2020-08-21 3:54 ` [PATCH v2 29/40] PCI: dwc/qcom: " Rob Herring 2020-08-21 3:54 ` [PATCH v2 30/40] PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset Rob Herring 2020-08-21 3:54 ` [PATCH v2 31/40] PCI: dwc/tegra: Use common Designware port logic register definitions Rob Herring 2020-08-21 3:54 ` [PATCH v2 32/40] PCI: dwc: Remove read_dbi2 code Rob Herring 2020-08-21 3:54 ` [PATCH v2 33/40] PCI: dwc: Make ATU accessors private Rob Herring 2020-08-21 3:54 ` [PATCH v2 34/40] PCI: dwc: Centralize link gen setting Rob Herring 2020-08-21 3:54 ` [PATCH v2 35/40] PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code Rob Herring 2020-08-21 3:54 ` [PATCH v2 36/40] PCI: dwc/intel-gw: Drop unnecessary checking of DT 'device_type' property Rob Herring 2020-08-21 3:54 ` [PATCH v2 37/40] PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup() Rob Herring 2020-08-21 3:54 ` [PATCH v2 38/40] PCI: dwc/intel-gw: Drop unused max_width Rob Herring 2020-08-21 3:54 ` [PATCH v2 39/40] PCI: dwc: Move N_FTS setup to common setup Rob Herring 2021-08-08 15:01 ` Vidya Sagar 2021-08-09 15:02 ` Rob Herring 2020-08-21 3:54 ` [PATCH v2 40/40] PCI: dwc: Use DBI accessors Rob Herring 2020-09-07 9:35 ` [PATCH v2 00/40] PCI: dwc: Driver clean-ups Lorenzo Pieralisi 2020-09-15 9:12 ` Michael Walle 2020-09-15 22:02 ` Rob Herring 2020-09-16 7:54 ` Michael Walle 2020-09-29 5:23 ` Kishon Vijay Abraham I 2020-09-29 14:32 ` Rob Herring
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20200821035420.380495-19-robh@kernel.org \ --to=robh@kernel.org \ --cc=agross@kernel.org \ --cc=bhelgaas@google.com \ --cc=bjorn.andersson@linaro.org \ --cc=eswara.kota@linux.intel.com \ --cc=festevam@gmail.com \ --cc=gustavo.pimentel@synopsys.com \ --cc=hayashi.kunihiko@socionext.com \ --cc=hongxing.zhu@nxp.com \ --cc=jbrunet@baylibre.com \ --cc=jesper.nilsson@axis.com \ --cc=jingoohan1@gmail.com \ --cc=jonathanh@nvidia.com \ --cc=jonnyc@amazon.com \ --cc=kernel@pengutronix.de \ --cc=kgene@kernel.org \ --cc=khilman@baylibre.com \ --cc=kishon@ti.com \ --cc=krzk@kernel.org \ --cc=l.stach@pengutronix.de \ --cc=linux-amlogic@lists.infradead.org \ --cc=linux-arm-kernel@axis.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-arm-msm@vger.kernel.org \ --cc=linux-imx@nxp.com \ --cc=linux-omap@vger.kernel.org \ --cc=linux-pci@vger.kernel.org \ --cc=linux-samsung-soc@vger.kernel.org \ --cc=linux-tegra@vger.kernel.org \ --cc=lorenzo.pieralisi@arm.com \ --cc=m-karicheri2@ti.com \ --cc=martin.blumenstingl@googlemail.com \ --cc=maz@kernel.org \ --cc=narmstrong@baylibre.com \ --cc=pratyush.anand@gmail.com \ --cc=s.hauer@pengutronix.de \ --cc=shawn.guo@linaro.org \ --cc=shawnguo@kernel.org \ --cc=songxiaowei@hisilicon.com \ --cc=svarbanov@mm-sol.com \ --cc=thierry.reding@gmail.com \ --cc=wangbinghui@hisilicon.com \ --cc=yamada.masahiro@socionext.com \ --cc=yue.wang@Amlogic.com \ --subject='Re: [PATCH v2 18/40] PCI: dwc: Remove storing of PCI resources' \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: link
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).