linux-pci.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Rob Herring <robh@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: linux-pci@vger.kernel.org, Andy Gross <agross@kernel.org>,
	Binghui Wang <wangbinghui@hisilicon.com>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Dilip Kota <eswara.kota@linux.intel.com>,
	Fabio Estevam <festevam@gmail.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Jesper Nilsson <jesper.nilsson@axis.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Jonathan Chocron <jonnyc@amazon.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Kevin Hilman <khilman@baylibre.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Kukjin Kim <kgene@kernel.org>,
	Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
	Lucas Stach <l.stach@pengutronix.de>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Masahiro Yamada <yamada.masahiro@socionext.com>,
	Murali Karicheri <m-karicheri2@ti.com>,
	Neil Armstrong <narmstrong@baylibre.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Pratyush Anand <pratyush.anand@gmail.com>,
	Richard Zhu <hongxing.zhu@nxp.com>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Shawn Guo <shawnguo@kernel.org>, Shawn Guo <shawn.guo@linaro.org>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	Xiaowei Song <songxiaowei@hisilicon.com>,
	Yue Wang <yue.wang@Amlogic.com>, Marc Zyngier <maz@kernel.org>,
	linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com,
	linux-arm-kernel@lists.infradead.org,
	linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: [PATCH v2 30/40] PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset
Date: Thu, 20 Aug 2020 21:54:10 -0600	[thread overview]
Message-ID: <20200821035420.380495-31-robh@kernel.org> (raw)
In-Reply-To: <20200821035420.380495-1-robh@kernel.org>

While the Designware controller appears to hard code the PCI_CAP_ID_EXP
capability register at 0x70, there's no need to hard code this in the
driver as it is discoverable.

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Cc: linux-omap@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pci-dra7xx.c     |  4 +---
 drivers/pci/controller/dwc/pci-keystone.c   | 11 +++++------
 drivers/pci/controller/dwc/pcie-spear13xx.c |  4 +---
 3 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index dc387724cf08..d42e0664f378 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -73,8 +73,6 @@
 #define	LINK_UP						BIT(16)
 #define	DRA7XX_CPU_TO_BUS_ADDR				0x0FFFFFFF
 
-#define EXP_CAP_ID_OFFSET				0x70
-
 #define	PCIECTRL_TI_CONF_INTX_ASSERT			0x0124
 #define	PCIECTRL_TI_CONF_INTX_DEASSERT			0x0128
 
@@ -142,7 +140,7 @@ static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
 	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
 	struct device *dev = pci->dev;
 	u32 reg;
-	u32 exp_cap_off = EXP_CAP_ID_OFFSET;
+	u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 
 	if (dw_pcie_link_up(pci)) {
 		dev_err(dev, "link is already up\n");
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index 0fe792f6c253..39a5a72de340 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -96,8 +96,6 @@
 #define LEG_EP				0x1
 #define RC				0x2
 
-#define EXP_CAP_ID_OFFSET		0x70
-
 #define KS_PCIE_SYSCLOCKOUTEN		BIT(0)
 
 #define AM654_PCIE_DEV_TYPE_MASK	0x3
@@ -1125,22 +1123,23 @@ static int ks_pcie_am654_set_mode(struct device *dev,
 static void ks_pcie_set_link_speed(struct dw_pcie *pci, int link_speed)
 {
 	u32 val;
+	u32 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 
 	dw_pcie_dbi_ro_wr_en(pci);
 
-	val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP);
+	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
 	if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) {
 		val &= ~((u32)PCI_EXP_LNKCAP_SLS);
 		val |= link_speed;
-		dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP,
+		dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP,
 				   val);
 	}
 
-	val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2);
+	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
 	if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) {
 		val &= ~((u32)PCI_EXP_LNKCAP_SLS);
 		val |= link_speed;
-		dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2,
+		dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2,
 				   val);
 	}
 
diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c
index 62846562da0b..056c94541a22 100644
--- a/drivers/pci/controller/dwc/pcie-spear13xx.c
+++ b/drivers/pci/controller/dwc/pcie-spear13xx.c
@@ -65,8 +65,6 @@ struct pcie_app_reg {
 /* CR6 */
 #define MSI_CTRL_INT				(1 << 26)
 
-#define EXP_CAP_ID_OFFSET			0x70
-
 #define to_spear13xx_pcie(x)	dev_get_drvdata((x)->dev)
 
 static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
@@ -75,7 +73,7 @@ static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
 	struct pcie_port *pp = &pci->pp;
 	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
 	u32 val;
-	u32 exp_cap_off = EXP_CAP_ID_OFFSET;
+	u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 
 	if (dw_pcie_link_up(pci)) {
 		dev_err(pci->dev, "link already up\n");
-- 
2.25.1


  parent reply	other threads:[~2020-08-21  3:56 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-21  3:53 [PATCH v2 00/40] PCI: dwc: Driver clean-ups Rob Herring
2020-08-21  3:53 ` [PATCH v2 01/40] PCI: Allow root and child buses to have different pci_ops Rob Herring
2020-08-21  3:53 ` [PATCH v2 02/40] PCI: dwc: Use DBI accessors instead of own config accessors Rob Herring
2020-08-21  3:53 ` [PATCH v2 03/40] PCI: dwc: Allow overriding bridge pci_ops Rob Herring
2021-08-08 15:13   ` Vidya Sagar
2021-08-09 14:52     ` Rob Herring
2020-08-21  3:53 ` [PATCH v2 04/40] PCI: dwc: Add a default pci_ops.map_bus for root port Rob Herring
2020-08-21  3:53 ` [PATCH v2 05/40] PCI: dwc: al: Use pci_ops for child config space accessors Rob Herring
2020-08-21  3:53 ` [PATCH v2 06/40] PCI: dwc: keystone: Use pci_ops for " Rob Herring
2020-08-21  3:53 ` [PATCH v2 07/40] PCI: dwc: tegra: Use pci_ops for root " Rob Herring
2020-08-21  3:53 ` [PATCH v2 08/40] PCI: dwc: meson: " Rob Herring
2020-08-21  3:53 ` [PATCH v2 09/40] PCI: dwc: kirin: " Rob Herring
2020-08-21  3:53 ` [PATCH v2 10/40] PCI: dwc: exynos: " Rob Herring
2020-08-21  3:53 ` [PATCH v2 11/40] PCI: dwc: histb: " Rob Herring
2020-08-21  3:53 ` [PATCH v2 12/40] PCI: dwc: Remove dwc specific config accessor ops Rob Herring
2020-08-21  3:53 ` [PATCH v2 13/40] PCI: dwc: Use generic config accessors Rob Herring
2020-08-21  3:53 ` [PATCH v2 14/40] PCI: Also call .add_bus() callback for root bus Rob Herring
2020-08-21  3:53 ` [PATCH v2 15/40] PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus Rob Herring
2020-08-21  3:53 ` [PATCH v2 16/40] PCI: dwc: Convert to use pci_host_probe() Rob Herring
2020-08-21  3:53 ` [PATCH v2 17/40] PCI: dwc: Remove root_bus pointer Rob Herring
2020-08-21  3:53 ` [PATCH v2 18/40] PCI: dwc: Remove storing of PCI resources Rob Herring
2020-08-21  3:53 ` [PATCH v2 19/40] PCI: dwc: Simplify config space handling Rob Herring
2020-08-21  3:54 ` [PATCH v2 20/40] PCI: dwc/keystone: Drop duplicated 'num-viewport' Rob Herring
2020-08-21  3:54 ` [PATCH v2 21/40] PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() Rob Herring
2020-08-21  3:54 ` [PATCH v2 22/40] PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL Rob Herring
2020-08-21  3:54 ` [PATCH v2 23/40] PCI: dwc: Add a 'num_lanes' field to struct dw_pcie Rob Herring
2020-08-21  3:54 ` [PATCH v2 24/40] PCI: dwc: Ensure FAST_LINK_MODE is cleared Rob Herring
2020-08-21  3:54 ` [PATCH v2 25/40] PCI: dwc/meson: Drop the duplicate number of lanes setup Rob Herring
2020-08-21  3:54 ` [PATCH v2 26/40] PCI: dwc/meson: Drop unnecessary RC config space initialization Rob Herring
2020-08-21  3:54 ` [PATCH v2 27/40] PCI: dwc/meson: Rework PCI config and DW port logic register accesses Rob Herring
2020-08-21  3:54 ` [PATCH v2 28/40] PCI: dwc/imx6: Use common PCI register definitions Rob Herring
2020-08-21  3:54 ` [PATCH v2 29/40] PCI: dwc/qcom: " Rob Herring
2020-08-21  3:54 ` Rob Herring [this message]
2020-08-21  3:54 ` [PATCH v2 31/40] PCI: dwc/tegra: Use common Designware port logic " Rob Herring
2020-08-21  3:54 ` [PATCH v2 32/40] PCI: dwc: Remove read_dbi2 code Rob Herring
2020-08-21  3:54 ` [PATCH v2 33/40] PCI: dwc: Make ATU accessors private Rob Herring
2020-08-21  3:54 ` [PATCH v2 34/40] PCI: dwc: Centralize link gen setting Rob Herring
2020-08-21  3:54 ` [PATCH v2 35/40] PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code Rob Herring
2020-08-21  3:54 ` [PATCH v2 36/40] PCI: dwc/intel-gw: Drop unnecessary checking of DT 'device_type' property Rob Herring
2020-08-21  3:54 ` [PATCH v2 37/40] PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup() Rob Herring
2020-08-21  3:54 ` [PATCH v2 38/40] PCI: dwc/intel-gw: Drop unused max_width Rob Herring
2020-08-21  3:54 ` [PATCH v2 39/40] PCI: dwc: Move N_FTS setup to common setup Rob Herring
2021-08-08 15:01   ` Vidya Sagar
2021-08-09 15:02     ` Rob Herring
2020-08-21  3:54 ` [PATCH v2 40/40] PCI: dwc: Use DBI accessors Rob Herring
2020-09-07  9:35 ` [PATCH v2 00/40] PCI: dwc: Driver clean-ups Lorenzo Pieralisi
2020-09-15  9:12 ` Michael Walle
2020-09-15 22:02   ` Rob Herring
2020-09-16  7:54     ` Michael Walle
2020-09-29  5:23       ` Kishon Vijay Abraham I
2020-09-29 14:32         ` Rob Herring

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200821035420.380495-31-robh@kernel.org \
    --to=robh@kernel.org \
    --cc=agross@kernel.org \
    --cc=bhelgaas@google.com \
    --cc=bjorn.andersson@linaro.org \
    --cc=eswara.kota@linux.intel.com \
    --cc=festevam@gmail.com \
    --cc=gustavo.pimentel@synopsys.com \
    --cc=hayashi.kunihiko@socionext.com \
    --cc=hongxing.zhu@nxp.com \
    --cc=jbrunet@baylibre.com \
    --cc=jesper.nilsson@axis.com \
    --cc=jingoohan1@gmail.com \
    --cc=jonathanh@nvidia.com \
    --cc=jonnyc@amazon.com \
    --cc=kernel@pengutronix.de \
    --cc=kgene@kernel.org \
    --cc=khilman@baylibre.com \
    --cc=kishon@ti.com \
    --cc=krzk@kernel.org \
    --cc=l.stach@pengutronix.de \
    --cc=linux-amlogic@lists.infradead.org \
    --cc=linux-arm-kernel@axis.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-imx@nxp.com \
    --cc=linux-omap@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-samsung-soc@vger.kernel.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=m-karicheri2@ti.com \
    --cc=martin.blumenstingl@googlemail.com \
    --cc=maz@kernel.org \
    --cc=narmstrong@baylibre.com \
    --cc=pratyush.anand@gmail.com \
    --cc=s.hauer@pengutronix.de \
    --cc=shawn.guo@linaro.org \
    --cc=shawnguo@kernel.org \
    --cc=songxiaowei@hisilicon.com \
    --cc=svarbanov@mm-sol.com \
    --cc=thierry.reding@gmail.com \
    --cc=wangbinghui@hisilicon.com \
    --cc=yamada.masahiro@socionext.com \
    --cc=yue.wang@Amlogic.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).