From: Rob Herring <robh@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: linux-pci@vger.kernel.org, Andy Gross <agross@kernel.org>,
Binghui Wang <wangbinghui@hisilicon.com>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Dilip Kota <eswara.kota@linux.intel.com>,
Fabio Estevam <festevam@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Jesper Nilsson <jesper.nilsson@axis.com>,
Jingoo Han <jingoohan1@gmail.com>,
Jonathan Chocron <jonnyc@amazon.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Kevin Hilman <khilman@baylibre.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Kukjin Kim <kgene@kernel.org>,
Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
Lucas Stach <l.stach@pengutronix.de>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
Murali Karicheri <m-karicheri2@ti.com>,
Neil Armstrong <narmstrong@baylibre.com>,
NXP Linux Team <linux-imx@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Pratyush Anand <pratyush.anand@gmail.com>,
Richard Zhu <hongxing.zhu@nxp.com>,
Sascha Hauer <s.hauer@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>, Shawn Guo <shawn.guo@linaro.org>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Thierry Reding <thierry.reding@gmail.com>,
Xiaowei Song <songxiaowei@hisilicon.com>,
Yue Wang <yue.wang@Amlogic.com>, Marc Zyngier <maz@kernel.org>,
linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com,
linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org,
linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: [PATCH v2 02/40] PCI: dwc: Use DBI accessors instead of own config accessors
Date: Thu, 20 Aug 2020 21:53:42 -0600 [thread overview]
Message-ID: <20200821035420.380495-3-robh@kernel.org> (raw)
In-Reply-To: <20200821035420.380495-1-robh@kernel.org>
The Designware DBI space contains the root bus bridge config space.
Platforms needing custom {rd,wr}_own_conf functions are also the ones
needing custom {read,write}_dbi ops functions and the access sequences
are the same.
Replace all dw_pcie_{rd,wr}_own_conf() calls with the DBI variants in
preparation to remove dw_pcie_{rd,wr}_own_conf().
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../pci/controller/dwc/pcie-designware-host.c | 55 +++++++------------
1 file changed, 19 insertions(+), 36 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 9dafecba347f..1d98554db009 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -82,13 +82,13 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
unsigned long val;
u32 status, num_ctrls;
irqreturn_t ret = IRQ_NONE;
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
for (i = 0; i < num_ctrls; i++) {
- dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS +
- (i * MSI_REG_CTRL_BLOCK_SIZE),
- 4, &status);
+ status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
+ (i * MSI_REG_CTRL_BLOCK_SIZE));
if (!status)
continue;
@@ -148,6 +148,7 @@ static int dw_pci_msi_set_affinity(struct irq_data *d,
static void dw_pci_bottom_mask(struct irq_data *d)
{
struct pcie_port *pp = irq_data_get_irq_chip_data(d);
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
unsigned int res, bit, ctrl;
unsigned long flags;
@@ -158,8 +159,7 @@ static void dw_pci_bottom_mask(struct irq_data *d)
bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
pp->irq_mask[ctrl] |= BIT(bit);
- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
- pp->irq_mask[ctrl]);
+ dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
raw_spin_unlock_irqrestore(&pp->lock, flags);
}
@@ -167,6 +167,7 @@ static void dw_pci_bottom_mask(struct irq_data *d)
static void dw_pci_bottom_unmask(struct irq_data *d)
{
struct pcie_port *pp = irq_data_get_irq_chip_data(d);
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
unsigned int res, bit, ctrl;
unsigned long flags;
@@ -177,8 +178,7 @@ static void dw_pci_bottom_unmask(struct irq_data *d)
bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
pp->irq_mask[ctrl] &= ~BIT(bit);
- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
- pp->irq_mask[ctrl]);
+ dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
raw_spin_unlock_irqrestore(&pp->lock, flags);
}
@@ -186,13 +186,14 @@ static void dw_pci_bottom_unmask(struct irq_data *d)
static void dw_pci_bottom_ack(struct irq_data *d)
{
struct pcie_port *pp = irq_data_get_irq_chip_data(d);
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
unsigned int res, bit, ctrl;
ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit));
+ dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
}
static struct irq_chip dw_pci_msi_bottom_irq_chip = {
@@ -310,10 +311,8 @@ void dw_pcie_msi_init(struct pcie_port *pp)
msi_target = (u64)pp->msi_data;
/* Program the msi_data */
- dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
- lower_32_bits(msi_target));
- dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
- upper_32_bits(msi_target));
+ dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
+ dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
}
EXPORT_SYMBOL_GPL(dw_pcie_msi_init);
@@ -327,7 +326,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
struct pci_bus *child;
struct pci_host_bridge *bridge;
struct resource *cfg_res;
- u32 hdr_type;
int ret;
raw_spin_lock_init(&pci->pp.lock);
@@ -453,21 +451,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
goto err_free_msi;
}
- ret = dw_pcie_rd_own_conf(pp, PCI_HEADER_TYPE, 1, &hdr_type);
- if (ret != PCIBIOS_SUCCESSFUL) {
- dev_err(pci->dev, "Failed reading PCI_HEADER_TYPE cfg space reg (ret: 0x%x)\n",
- ret);
- ret = pcibios_err_to_errno(ret);
- goto err_free_msi;
- }
- if (hdr_type != PCI_HEADER_TYPE_BRIDGE) {
- dev_err(pci->dev,
- "PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n",
- hdr_type);
- ret = -EIO;
- goto err_free_msi;
- }
-
bridge->sysdata = pp;
bridge->ops = &dw_pcie_ops;
@@ -638,12 +621,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
/* Initialize IRQ Status array */
for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
pp->irq_mask[ctrl] = ~0;
- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK +
+ dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
(ctrl * MSI_REG_CTRL_BLOCK_SIZE),
- 4, pp->irq_mask[ctrl]);
- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
+ pp->irq_mask[ctrl]);
+ dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
(ctrl * MSI_REG_CTRL_BLOCK_SIZE),
- 4, ~0);
+ ~0);
}
}
@@ -685,14 +668,14 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
pp->io_bus_addr, pp->io_size);
}
- dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
+ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
/* Program correct class for RC */
- dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+ dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
- dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
+ val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
val |= PORT_LOGIC_SPEED_CHANGE;
- dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
+ dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
dw_pcie_dbi_ro_wr_dis(pci);
}
--
2.25.1
next prev parent reply other threads:[~2020-08-21 3:54 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-21 3:53 [PATCH v2 00/40] PCI: dwc: Driver clean-ups Rob Herring
2020-08-21 3:53 ` [PATCH v2 01/40] PCI: Allow root and child buses to have different pci_ops Rob Herring
2020-08-21 3:53 ` Rob Herring [this message]
2020-08-21 3:53 ` [PATCH v2 03/40] PCI: dwc: Allow overriding bridge pci_ops Rob Herring
2021-08-08 15:13 ` Vidya Sagar
2021-08-09 14:52 ` Rob Herring
2020-08-21 3:53 ` [PATCH v2 04/40] PCI: dwc: Add a default pci_ops.map_bus for root port Rob Herring
2020-08-21 3:53 ` [PATCH v2 05/40] PCI: dwc: al: Use pci_ops for child config space accessors Rob Herring
2020-08-21 3:53 ` [PATCH v2 06/40] PCI: dwc: keystone: Use pci_ops for " Rob Herring
2020-08-21 3:53 ` [PATCH v2 07/40] PCI: dwc: tegra: Use pci_ops for root " Rob Herring
2020-08-21 3:53 ` [PATCH v2 08/40] PCI: dwc: meson: " Rob Herring
2020-08-21 3:53 ` [PATCH v2 09/40] PCI: dwc: kirin: " Rob Herring
2020-08-21 3:53 ` [PATCH v2 10/40] PCI: dwc: exynos: " Rob Herring
2020-08-21 3:53 ` [PATCH v2 11/40] PCI: dwc: histb: " Rob Herring
2020-08-21 3:53 ` [PATCH v2 12/40] PCI: dwc: Remove dwc specific config accessor ops Rob Herring
2020-08-21 3:53 ` [PATCH v2 13/40] PCI: dwc: Use generic config accessors Rob Herring
2020-08-21 3:53 ` [PATCH v2 14/40] PCI: Also call .add_bus() callback for root bus Rob Herring
2020-08-21 3:53 ` [PATCH v2 15/40] PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus Rob Herring
2020-08-21 3:53 ` [PATCH v2 16/40] PCI: dwc: Convert to use pci_host_probe() Rob Herring
2020-08-21 3:53 ` [PATCH v2 17/40] PCI: dwc: Remove root_bus pointer Rob Herring
2020-08-21 3:53 ` [PATCH v2 18/40] PCI: dwc: Remove storing of PCI resources Rob Herring
2020-08-21 3:53 ` [PATCH v2 19/40] PCI: dwc: Simplify config space handling Rob Herring
2020-08-21 3:54 ` [PATCH v2 20/40] PCI: dwc/keystone: Drop duplicated 'num-viewport' Rob Herring
2020-08-21 3:54 ` [PATCH v2 21/40] PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() Rob Herring
2020-08-21 3:54 ` [PATCH v2 22/40] PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL Rob Herring
2020-08-21 3:54 ` [PATCH v2 23/40] PCI: dwc: Add a 'num_lanes' field to struct dw_pcie Rob Herring
2020-08-21 3:54 ` [PATCH v2 24/40] PCI: dwc: Ensure FAST_LINK_MODE is cleared Rob Herring
2020-08-21 3:54 ` [PATCH v2 25/40] PCI: dwc/meson: Drop the duplicate number of lanes setup Rob Herring
2020-08-21 3:54 ` [PATCH v2 26/40] PCI: dwc/meson: Drop unnecessary RC config space initialization Rob Herring
2020-08-21 3:54 ` [PATCH v2 27/40] PCI: dwc/meson: Rework PCI config and DW port logic register accesses Rob Herring
2020-08-21 3:54 ` [PATCH v2 28/40] PCI: dwc/imx6: Use common PCI register definitions Rob Herring
2020-08-21 3:54 ` [PATCH v2 29/40] PCI: dwc/qcom: " Rob Herring
2020-08-21 3:54 ` [PATCH v2 30/40] PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset Rob Herring
2020-08-21 3:54 ` [PATCH v2 31/40] PCI: dwc/tegra: Use common Designware port logic register definitions Rob Herring
2020-08-21 3:54 ` [PATCH v2 32/40] PCI: dwc: Remove read_dbi2 code Rob Herring
2020-08-21 3:54 ` [PATCH v2 33/40] PCI: dwc: Make ATU accessors private Rob Herring
2020-08-21 3:54 ` [PATCH v2 34/40] PCI: dwc: Centralize link gen setting Rob Herring
2020-08-21 3:54 ` [PATCH v2 35/40] PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code Rob Herring
2020-08-21 3:54 ` [PATCH v2 36/40] PCI: dwc/intel-gw: Drop unnecessary checking of DT 'device_type' property Rob Herring
2020-08-21 3:54 ` [PATCH v2 37/40] PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup() Rob Herring
2020-08-21 3:54 ` [PATCH v2 38/40] PCI: dwc/intel-gw: Drop unused max_width Rob Herring
2020-08-21 3:54 ` [PATCH v2 39/40] PCI: dwc: Move N_FTS setup to common setup Rob Herring
2021-08-08 15:01 ` Vidya Sagar
2021-08-09 15:02 ` Rob Herring
2020-08-21 3:54 ` [PATCH v2 40/40] PCI: dwc: Use DBI accessors Rob Herring
2020-09-07 9:35 ` [PATCH v2 00/40] PCI: dwc: Driver clean-ups Lorenzo Pieralisi
2020-09-15 9:12 ` Michael Walle
2020-09-15 22:02 ` Rob Herring
2020-09-16 7:54 ` Michael Walle
2020-09-29 5:23 ` Kishon Vijay Abraham I
2020-09-29 14:32 ` Rob Herring
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