From: "David E. Box" <david.e.box@linux.intel.com>
To: lee.jones@linaro.org, hdegoede@redhat.com,
mgross@linux.intel.com, bhelgaas@google.com,
gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com,
srinivas.pandruvada@intel.com
Cc: "David E. Box" <david.e.box@linux.intel.com>,
linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
platform-driver-x86@vger.kernel.org, linux-pci@vger.kernel.org
Subject: [PATCH 3/5] platform/x86/intel: extended_caps: Add support for PCIe VSEC structures
Date: Thu, 30 Sep 2021 18:28:13 -0700 [thread overview]
Message-ID: <20211001012815.1999501-4-david.e.box@linux.intel.com> (raw)
In-Reply-To: <20211001012815.1999501-1-david.e.box@linux.intel.com>
Adds support for discovering Intel extended capability features from
Vendor Specific Extended Capability (VSEC) registers in PCIe config space.
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
---
V1: - Modified version of [1] applied to auxiliary bus driver.
- Use bool instead of int to track whether any device has been added.
[1] https://lore.kernel.org/all/20210922213007.2738388-4-david.e.box@linux.intel.com/
drivers/platform/x86/intel/extended_caps.c | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/platform/x86/intel/extended_caps.c b/drivers/platform/x86/intel/extended_caps.c
index 03acea20b675..eca47d693b14 100644
--- a/drivers/platform/x86/intel/extended_caps.c
+++ b/drivers/platform/x86/intel/extended_caps.c
@@ -294,6 +294,54 @@ static bool extended_caps_walk_dvsec(struct pci_dev *pdev, unsigned long quirks)
return have_devices;
}
+static bool extended_caps_walk_vsec(struct pci_dev *pdev, unsigned long quirks)
+{
+ bool have_devices = false;
+ int pos = 0;
+
+ do {
+ struct extended_caps_header header;
+ u32 table, hdr;
+ int ret;
+
+ pos = pci_find_next_ext_capability(pdev, pos, PCI_EXT_CAP_ID_VNDR);
+ if (!pos)
+ break;
+
+ pci_read_config_dword(pdev, pos + PCI_VNDR_HEADER, &hdr);
+
+ /* Support only revision 1 */
+ header.rev = PCI_VNDR_HEADER_REV(hdr);
+ if (header.rev != 1) {
+ dev_warn(&pdev->dev, "Unsupported VSEC revision %d\n",
+ header.rev);
+ continue;
+ }
+
+ header.id = PCI_VNDR_HEADER_ID(hdr);
+ header.length = PCI_VNDR_HEADER_LEN(hdr);
+
+ /* entry, size, and table offset are the same as DVSEC */
+ pci_read_config_byte(pdev, pos + INTEL_DVSEC_ENTRIES,
+ &header.num_entries);
+ pci_read_config_byte(pdev, pos + INTEL_DVSEC_SIZE,
+ &header.entry_size);
+ pci_read_config_dword(pdev, pos + INTEL_DVSEC_TABLE,
+ &table);
+
+ header.tbir = INTEL_DVSEC_TABLE_BAR(table);
+ header.offset = INTEL_DVSEC_TABLE_OFFSET(table);
+
+ ret = extended_caps_add_dev(pdev, &header, quirks);
+ if (ret)
+ continue;
+
+ have_devices = true;
+ } while (true);
+
+ return have_devices;
+}
+
static int extended_caps_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct extended_caps_platform_info *info;
@@ -310,6 +358,7 @@ static int extended_caps_pci_probe(struct pci_dev *pdev, const struct pci_device
quirks = info->quirks;
have_devices |= extended_caps_walk_dvsec(pdev, quirks);
+ have_devices |= extended_caps_walk_vsec(pdev, quirks);
if (info && (info->quirks & EXT_CAPS_QUIRK_NO_DVSEC))
have_devices |= extended_caps_walk_header(pdev, quirks, info->capabilities);
--
2.25.1
next prev parent reply other threads:[~2021-10-01 1:28 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-01 1:28 [PATCH 0/5] Move intel_pm from MFD to Auxiliary bus David E. Box
2021-10-01 1:28 ` [PATCH 1/5] PCI: Add #defines for accessing PCIe DVSEC fields David E. Box
2021-10-01 1:28 ` [PATCH 2/5] platform/x86/intel: Move intel_pmt from MFD to Auxiliary Bus David E. Box
2021-10-06 8:58 ` Leon Romanovsky
2021-10-06 20:58 ` David E. Box
2021-10-10 6:59 ` Leon Romanovsky
2021-10-01 1:28 ` David E. Box [this message]
2021-10-01 1:28 ` [PATCH 4/5] Documentation: Update ioctl-number.rst for Intel Software Defined Silicon interface David E. Box
2021-10-01 1:28 ` [PATCH 5/5] platform/x86: Add Intel Software Defined Silicon driver David E. Box
2021-10-01 7:14 ` Greg KH
2021-10-01 10:38 ` David E. Box
2021-10-01 11:29 ` Greg KH
2021-10-01 7:15 ` Greg KH
2021-10-01 7:16 ` Greg KH
2021-10-01 10:47 ` David E. Box
2021-10-01 11:27 ` Greg KH
2021-10-01 7:29 ` Greg KH
2021-10-01 11:13 ` David E. Box
2021-10-01 11:26 ` Greg KH
2021-10-01 20:43 ` David E. Box
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