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From: Greg KH <gregkh@linuxfoundation.org>
To: "David E. Box" <david.e.box@linux.intel.com>
Cc: lee.jones@linaro.org, hdegoede@redhat.com,
	mgross@linux.intel.com, bhelgaas@google.com,
	andriy.shevchenko@linux.intel.com, srinivas.pandruvada@intel.com,
	linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
	platform-driver-x86@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH 5/5] platform/x86: Add Intel Software Defined Silicon driver
Date: Fri, 1 Oct 2021 09:16:47 +0200	[thread overview]
Message-ID: <YVa13/iTdZR6xkiq@kroah.com> (raw)
In-Reply-To: <20211001012815.1999501-6-david.e.box@linux.intel.com>

On Thu, Sep 30, 2021 at 06:28:15PM -0700, David E. Box wrote:
> Intel Software Defined Silicon (SDSi) is a post manufacturing mechanism for
> activating additional silicon features. Features are enabled through a
> license activation process.  The SDSi driver provides a per socket, ioctl
> interface for applications to perform 3 main provisioning functions:
> 
> 1. Provision an Authentication Key Certificate (AKC), a key written to
>    internal NVRAM that is used to authenticate a capability specific
>    activation payload.
> 
> 2. Provision a Capability Activation Payload (CAP), a token authenticated
>    using the AKC and applied to the CPU configuration to activate a new
>    feature.
> 
> 3. Read the SDSi State Certificate, containing the CPU configuration
>    state.
> 
> The ioctl operations perform function specific mailbox commands that
> forward the requests to SDSi hardware to perform authentication of the
> payloads and enable the silicon configuration (to be made available after
> power cycling).
> 
> The SDSi device itself is enumerated as an auxiliary device from the
> intel_extended_caps driver and as such has a build dependency on
> CONFIG_INTEL_EXTENDED_CAPS.
> 
> Link: https://github.com/intel/intel-sdsi
> Signed-off-by: David E. Box <david.e.box@linux.intel.com>

I do not see the "required" review that Intel developers need when
sending stuff to me.  What happened here?

thanks,

greg k-h

  parent reply	other threads:[~2021-10-01  7:16 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-01  1:28 [PATCH 0/5] Move intel_pm from MFD to Auxiliary bus David E. Box
2021-10-01  1:28 ` [PATCH 1/5] PCI: Add #defines for accessing PCIe DVSEC fields David E. Box
2021-10-01  1:28 ` [PATCH 2/5] platform/x86/intel: Move intel_pmt from MFD to Auxiliary Bus David E. Box
2021-10-06  8:58   ` Leon Romanovsky
2021-10-06 20:58     ` David E. Box
2021-10-10  6:59       ` Leon Romanovsky
2021-10-01  1:28 ` [PATCH 3/5] platform/x86/intel: extended_caps: Add support for PCIe VSEC structures David E. Box
2021-10-01  1:28 ` [PATCH 4/5] Documentation: Update ioctl-number.rst for Intel Software Defined Silicon interface David E. Box
2021-10-01  1:28 ` [PATCH 5/5] platform/x86: Add Intel Software Defined Silicon driver David E. Box
2021-10-01  7:14   ` Greg KH
2021-10-01 10:38     ` David E. Box
2021-10-01 11:29       ` Greg KH
2021-10-01  7:15   ` Greg KH
2021-10-01  7:16   ` Greg KH [this message]
2021-10-01 10:47     ` David E. Box
2021-10-01 11:27       ` Greg KH
2021-10-01  7:29   ` Greg KH
2021-10-01 11:13     ` David E. Box
2021-10-01 11:26       ` Greg KH
2021-10-01 20:43         ` David E. Box

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