From: Manivannan Sadhasivam <mani@kernel.org>
To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
fancer.lancer@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v18 07/20] PCI: dwc: endpoint: Add multiple PFs support for dbi2
Date: Mon, 24 Jul 2023 14:54:54 +0530 [thread overview]
Message-ID: <20230724092454.GF6291@thinkpad> (raw)
In-Reply-To: <20230721074452.65545-8-yoshihiro.shimoda.uh@renesas.com>
On Fri, Jul 21, 2023 at 04:44:39PM +0900, Yoshihiro Shimoda wrote:
> The commit 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support
> for DWC") added .func_conf_select() to get the configuration space of
> different PFs and assumed that the offsets between dbi and dbi2 would
> be the same. However, Renesas R-Car Gen4 PCIe controllers have different
> offsets of function 1: dbi (+0x1000) and dbi2 (+0x800). To get
> the offset for dbi2, add .func_conf_select2() and
> dw_pcie_ep_func_select2().
>
How about,
.get_dbi2_offset() and dw_pcie_ep_get_dbi2_offset()?
This would've been much simpler if dw_pcie_writeX_{dbi/dbi2} APIs accepted the
func_no argument, so that these offset calculations are contained in the API
definitions itself as it should. Then the APIs could just do "func_offset *
func_no" to get DBI base and "(func_offset * func_no) + dbi2_offset" to get DBI2
base, provided these offsets are passed by the vendor drivers.
It can be done in a separate cleanup series later.
> Notes that dw_pcie_ep_func_select2() will call .func_conf_select()
s/Notes/Note
> if .func_conf_select2() doesn't exist for backward compatibility.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
> .../pci/controller/dwc/pcie-designware-ep.c | 32 ++++++++++++++-----
> drivers/pci/controller/dwc/pcie-designware.h | 3 +-
> 2 files changed, 26 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 1d24ebf9686f..bd57516d5313 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -54,21 +54,35 @@ static unsigned int dw_pcie_ep_func_select(struct dw_pcie_ep *ep, u8 func_no)
> return func_offset;
> }
>
> +static unsigned int dw_pcie_ep_func_select2(struct dw_pcie_ep *ep, u8 func_no)
> +{
> + unsigned int func_offset = 0;
> +
> + if (ep->ops->func_conf_select2)
> + func_offset = ep->ops->func_conf_select2(ep, func_no);
> + else if (ep->ops->func_conf_select) /* for backward compatibility */
> + func_offset = ep->ops->func_conf_select(ep, func_no);
> +
> + return func_offset;
> +}
> +
> static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no,
> enum pci_barno bar, int flags)
> {
> - u32 reg;
> - unsigned int func_offset = 0;
> + u32 reg, reg_dbi2;
> + unsigned int func_offset, func_offset_dbi2;
Please maitain reverse Xmas tree order.
- Mani
> struct dw_pcie_ep *ep = &pci->ep;
>
> func_offset = dw_pcie_ep_func_select(ep, func_no);
> + func_offset_dbi2 = dw_pcie_ep_func_select2(ep, func_no);
>
> reg = func_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
> + reg_dbi2 = func_offset_dbi2 + PCI_BASE_ADDRESS_0 + (4 * bar);
> dw_pcie_dbi_ro_wr_en(pci);
> - dw_pcie_writel_dbi2(pci, reg, 0x0);
> + dw_pcie_writel_dbi2(pci, reg_dbi2, 0x0);
> dw_pcie_writel_dbi(pci, reg, 0x0);
> if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> - dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
> + dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, 0x0);
> dw_pcie_writel_dbi(pci, reg + 4, 0x0);
> }
> dw_pcie_dbi_ro_wr_dis(pci);
> @@ -232,13 +246,15 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> enum pci_barno bar = epf_bar->barno;
> size_t size = epf_bar->size;
> int flags = epf_bar->flags;
> - unsigned int func_offset = 0;
> + unsigned int func_offset, func_offset_dbi2;
> int ret, type;
> - u32 reg;
> + u32 reg, reg_dbi2;
>
> func_offset = dw_pcie_ep_func_select(ep, func_no);
> + func_offset_dbi2 = dw_pcie_ep_func_select2(ep, func_no);
>
> reg = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset;
> + reg_dbi2 = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset_dbi2;
>
> if (!(flags & PCI_BASE_ADDRESS_SPACE))
> type = PCIE_ATU_TYPE_MEM;
> @@ -254,11 +270,11 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>
> dw_pcie_dbi_ro_wr_en(pci);
>
> - dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
> + dw_pcie_writel_dbi2(pci, reg_dbi2, lower_32_bits(size - 1));
> dw_pcie_writel_dbi(pci, reg, flags);
>
> if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> - dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
> + dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, upper_32_bits(size - 1));
> dw_pcie_writel_dbi(pci, reg + 4, 0);
> }
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 812c221b3f7c..94bc20f5f600 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -340,9 +340,10 @@ struct dw_pcie_ep_ops {
> * access for different platform, if different func have different
> * offset, return the offset of func. if use write a register way
> * return a 0, and implement code in callback function of platform
> - * driver.
> + * driver. The func_conf_select2 is for dbi2.
> */
> unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
> + unsigned int (*func_conf_select2)(struct dw_pcie_ep *ep, u8 func_no);
> };
>
> struct dw_pcie_ep_func {
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2023-07-24 9:25 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 01/20] PCI: Add INTx Mechanism Messages macros Yoshihiro Shimoda
2023-07-24 7:25 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 02/20] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX Yoshihiro Shimoda
2023-07-21 8:10 ` Damien Le Moal
2023-07-24 7:32 ` Manivannan Sadhasivam
2023-07-29 1:35 ` Serge Semin
2023-07-29 1:55 ` Damien Le Moal
2023-07-29 1:58 ` Damien Le Moal
2023-07-29 2:02 ` Serge Semin
2023-07-29 15:32 ` Bjorn Helgaas
2023-07-30 4:58 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 03/20] PCI: dwc: Rename "legacy_irq" to "INTx_irq" Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu() Yoshihiro Shimoda
2023-07-24 7:45 ` Manivannan Sadhasivam
2023-07-26 5:02 ` Serge Semin
2023-07-26 13:00 ` Manivannan Sadhasivam
2023-07-26 23:38 ` Serge Semin
2023-07-27 1:06 ` Yoshihiro Shimoda
2023-07-27 11:03 ` Manivannan Sadhasivam
2023-07-27 12:21 ` Serge Semin
2023-07-29 2:06 ` Serge Semin
2023-07-31 1:24 ` Yoshihiro Shimoda
2023-07-31 21:33 ` Serge Semin
2023-08-01 1:29 ` Yoshihiro Shimoda
2023-08-01 1:44 ` Serge Semin
2023-08-01 7:02 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 05/20] PCI: dwc: Add outbound MSG TLPs support Yoshihiro Shimoda
2023-07-24 8:12 ` Manivannan Sadhasivam
2023-07-29 1:40 ` Serge Semin
2023-07-31 1:18 ` Yoshihiro Shimoda
2023-07-31 22:11 ` Serge Semin
2023-08-01 1:31 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 06/20] PCI: designware-ep: Add INTx IRQs support Yoshihiro Shimoda
2023-07-24 8:34 ` Manivannan Sadhasivam
2023-07-26 3:03 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 07/20] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Yoshihiro Shimoda
2023-07-24 9:24 ` Manivannan Sadhasivam [this message]
2023-07-25 11:57 ` Yoshihiro Shimoda
2023-07-28 2:34 ` Manivannan Sadhasivam
2023-07-28 4:18 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width() Yoshihiro Shimoda
2023-07-31 23:53 ` Serge Semin
2023-08-01 1:50 ` Yoshihiro Shimoda
2023-08-07 22:53 ` Serge Semin
2023-08-07 23:40 ` Bjorn Helgaas
2023-08-08 0:15 ` Serge Semin
2023-08-08 15:08 ` Bjorn Helgaas
2023-08-08 21:16 ` Serge Semin
2023-07-21 7:44 ` [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling Yoshihiro Shimoda
2023-07-24 11:03 ` Manivannan Sadhasivam
2023-07-26 2:12 ` Yoshihiro Shimoda
2023-07-28 2:51 ` Manivannan Sadhasivam
2023-07-28 4:19 ` Yoshihiro Shimoda
2023-07-28 16:07 ` Serge Semin
2023-07-31 1:15 ` Yoshihiro Shimoda
2023-08-01 0:00 ` Serge Semin
2023-08-01 6:26 ` Yoshihiro Shimoda
2023-08-02 10:46 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 10/20] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting Yoshihiro Shimoda
2023-07-24 11:29 ` Manivannan Sadhasivam
2023-07-26 2:26 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 11/20] PCI: dwc: Add EDMA_UNROLL capability flag Yoshihiro Shimoda
2023-07-24 11:35 ` Manivannan Sadhasivam
2023-07-26 2:58 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 12/20] PCI: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
2023-07-24 11:36 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit() Yoshihiro Shimoda
2023-07-21 9:23 ` Sergei Shtylyov
2023-07-24 11:40 ` Manivannan Sadhasivam
2023-07-26 3:02 ` Yoshihiro Shimoda
2023-08-01 0:15 ` Serge Semin
2023-08-02 10:40 ` Manivannan Sadhasivam
2023-08-01 0:22 ` Serge Semin
2023-08-01 6:27 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 14/20] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 15/20] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 16/20] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 17/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
2023-07-24 12:28 ` Manivannan Sadhasivam
2023-08-01 1:06 ` Serge Semin
2023-08-01 6:46 ` Yoshihiro Shimoda
2023-08-01 18:28 ` Serge Semin
2023-08-02 10:36 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 18/20] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
2023-08-01 1:36 ` Serge Semin
2023-08-01 6:59 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 19/20] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 20/20] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller Yoshihiro Shimoda
2023-07-24 10:53 ` [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Serge Semin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230724092454.GF6291@thinkpad \
--to=mani@kernel.org \
--cc=bhelgaas@google.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=fancer.lancer@gmail.com \
--cc=gustavo.pimentel@synopsys.com \
--cc=jingoohan1@gmail.com \
--cc=kishon@kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=linux-pci@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=marek.vasut+renesas@gmail.com \
--cc=robh+dt@kernel.org \
--cc=yoshihiro.shimoda.uh@renesas.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).