From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: "jingoohan1@gmail.com" <jingoohan1@gmail.com>,
"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"kw@linux.com" <kw@linux.com>,
"manivannan.sadhasivam@linaro.org"
<manivannan.sadhasivam@linaro.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"kishon@kernel.org" <kishon@kernel.org>,
"krzysztof.kozlowski+dt@linaro.org"
<krzysztof.kozlowski+dt@linaro.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"marek.vasut+renesas@gmail.com" <marek.vasut+renesas@gmail.com>,
"fancer.lancer@gmail.com" <fancer.lancer@gmail.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-renesas-soc@vger.kernel.org"
<linux-renesas-soc@vger.kernel.org>
Subject: RE: [PATCH v18 06/20] PCI: designware-ep: Add INTx IRQs support
Date: Wed, 26 Jul 2023 03:03:45 +0000 [thread overview]
Message-ID: <TYBPR01MB534172AB2D8AA33A889FC036D800A@TYBPR01MB5341.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <20230724083421.GE6291@thinkpad>
Hi Manivannan,
> From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 5:34 PM
>
> On Fri, Jul 21, 2023 at 04:44:38PM +0900, Yoshihiro Shimoda wrote:
> > Add support for triggering INTx IRQs by using outbound iATU.
> > Outbound iATU is utilized to send assert and de-assert INTx TLPs.
> > The message is generated based on the payloadless Msg TLP with type
> > 0x14, where 0x4 is the routing code implying the Terminate at
> > Receiver message. The message code is specified as b1000xx for
> > the INTx assertion and b1001xx for the INTx de-assertion.
> >
>
> Commit message is missing a few important points:
>
> 1. EDGE IRQ is simulated for INTx
> 2. Only INTA is asserted
> 3. INTx support is optional (if there is no memory for INTx, probe will not
> fail)
>
> Above points should be included in the commit message to properly describe the
> change.
I'll add such information.
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > ---
> > .../pci/controller/dwc/pcie-designware-ep.c | 69 +++++++++++++++++--
> > drivers/pci/controller/dwc/pcie-designware.h | 2 +
> > 2 files changed, 67 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > index fe2e0d765be9..1d24ebf9686f 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > @@ -6,9 +6,11 @@
> > * Author: Kishon Vijay Abraham I <kishon@ti.com>
> > */
> >
> > +#include <linux/delay.h>
> > #include <linux/of.h>
> > #include <linux/platform_device.h>
> >
> > +#include "../../pci.h"
> > #include "pcie-designware.h"
> > #include <linux/pci-epc.h>
> > #include <linux/pci-epf.h>
> > @@ -484,14 +486,60 @@ static const struct pci_epc_ops epc_ops = {
> > .get_features = dw_pcie_ep_get_features,
> > };
> >
> > +static int dw_pcie_ep_send_msg(struct dw_pcie_ep *ep, u8 func_no, u8 code,
> > + u8 routing)
> > +{
> > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > + struct pci_epc *epc = ep->epc;
> > + int ret;
> > +
> > + atu.func_no = func_no;
> > + atu.code = code;
> > + atu.routing = routing;
> > + atu.type = PCIE_ATU_TYPE_MSG;
> > + atu.cpu_addr = ep->intx_mem_phys;
> > + atu.size = epc->mem->window.page_size;
> > +
> > + ret = dw_pcie_ep_outbound_atu(ep, &atu);
> > + if (ret)
> > + return ret;
> > +
> > + writel(0, ep->intx_mem);
> > +
>
> This write is not described anywhere.
I'll add a comment before the writel.
Best regards,
Yoshihiro Shimoda
> - Mani
>
> > + dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->intx_mem_phys);
> > +
> > + return 0;
> > +}
> > +
> > int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > struct device *dev = pci->dev;
> > + int ret;
> >
> > - dev_err(dev, "EP cannot trigger INTx IRQs\n");
> > + if (!ep->intx_mem) {
> > + dev_err(dev, "INTx not supported\n");
> > + return -EOPNOTSUPP;
> > + }
> >
> > - return -EINVAL;
> > + /*
> > + * Even though the PCI bus specification implies the level-triggered
> > + * INTx interrupts the kernel PCIe endpoint framework has a single
> > + * PCI_EPC_IRQ_INTx flag defined for the legacy IRQs simulation. Thus
> > + * this function sends the Deassert_INTx PCIe TLP after the Assert_INTx
> > + * message with the 50 usec duration basically implementing the
> > + * rising-edge triggering IRQ. Hopefully the interrupt controller will
> > + * still be able to register the incoming IRQ event...
> > + */
> > + ret = dw_pcie_ep_send_msg(ep, func_no, PCI_MSG_CODE_ASSERT_INTA,
> > + PCI_MSG_TYPE_R_ROUTING_LOCAL);
> > + if (ret)
> > + return ret;
> > +
> > + usleep_range(50, 100);
> > +
> > + return dw_pcie_ep_send_msg(ep, func_no, PCI_MSG_CODE_DEASSERT_INTA,
> > + PCI_MSG_TYPE_R_ROUTING_LOCAL);
> > }
> > EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_intx_irq);
> >
> > @@ -622,6 +670,10 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> >
> > dw_pcie_edma_remove(pci);
> >
> > + if (ep->intx_mem)
> > + pci_epc_mem_free_addr(epc, ep->intx_mem_phys, ep->intx_mem,
> > + epc->mem->window.page_size);
> > +
> > pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
> > epc->mem->window.page_size);
> >
> > @@ -793,9 +845,14 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> > goto err_exit_epc_mem;
> > }
> >
> > + ep->intx_mem = pci_epc_mem_alloc_addr(epc, &ep->intx_mem_phys,
> > + epc->mem->window.page_size);
> > + if (!ep->intx_mem)
> > + dev_warn(dev, "Failed to reserve memory for INTx\n");
> > +
> > ret = dw_pcie_edma_detect(pci);
> > if (ret)
> > - goto err_free_epc_mem;
> > + goto err_free_epc_mem_intx;
> >
> > if (ep->ops->get_features) {
> > epc_features = ep->ops->get_features(ep);
> > @@ -812,7 +869,11 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> > err_remove_edma:
> > dw_pcie_edma_remove(pci);
> >
> > -err_free_epc_mem:
> > +err_free_epc_mem_intx:
> > + if (ep->intx_mem)
> > + pci_epc_mem_free_addr(epc, ep->intx_mem_phys, ep->intx_mem,
> > + epc->mem->window.page_size);
> > +
> > pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
> > epc->mem->window.page_size);
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index c626d21243b0..812c221b3f7c 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -365,6 +365,8 @@ struct dw_pcie_ep {
> > unsigned long *ob_window_map;
> > void __iomem *msi_mem;
> > phys_addr_t msi_mem_phys;
> > + void __iomem *intx_mem;
> > + phys_addr_t intx_mem_phys;
> > struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS];
> > };
> >
> > --
> > 2.25.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2023-07-26 3:03 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 01/20] PCI: Add INTx Mechanism Messages macros Yoshihiro Shimoda
2023-07-24 7:25 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 02/20] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX Yoshihiro Shimoda
2023-07-21 8:10 ` Damien Le Moal
2023-07-24 7:32 ` Manivannan Sadhasivam
2023-07-29 1:35 ` Serge Semin
2023-07-29 1:55 ` Damien Le Moal
2023-07-29 1:58 ` Damien Le Moal
2023-07-29 2:02 ` Serge Semin
2023-07-29 15:32 ` Bjorn Helgaas
2023-07-30 4:58 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 03/20] PCI: dwc: Rename "legacy_irq" to "INTx_irq" Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu() Yoshihiro Shimoda
2023-07-24 7:45 ` Manivannan Sadhasivam
2023-07-26 5:02 ` Serge Semin
2023-07-26 13:00 ` Manivannan Sadhasivam
2023-07-26 23:38 ` Serge Semin
2023-07-27 1:06 ` Yoshihiro Shimoda
2023-07-27 11:03 ` Manivannan Sadhasivam
2023-07-27 12:21 ` Serge Semin
2023-07-29 2:06 ` Serge Semin
2023-07-31 1:24 ` Yoshihiro Shimoda
2023-07-31 21:33 ` Serge Semin
2023-08-01 1:29 ` Yoshihiro Shimoda
2023-08-01 1:44 ` Serge Semin
2023-08-01 7:02 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 05/20] PCI: dwc: Add outbound MSG TLPs support Yoshihiro Shimoda
2023-07-24 8:12 ` Manivannan Sadhasivam
2023-07-29 1:40 ` Serge Semin
2023-07-31 1:18 ` Yoshihiro Shimoda
2023-07-31 22:11 ` Serge Semin
2023-08-01 1:31 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 06/20] PCI: designware-ep: Add INTx IRQs support Yoshihiro Shimoda
2023-07-24 8:34 ` Manivannan Sadhasivam
2023-07-26 3:03 ` Yoshihiro Shimoda [this message]
2023-07-21 7:44 ` [PATCH v18 07/20] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Yoshihiro Shimoda
2023-07-24 9:24 ` Manivannan Sadhasivam
2023-07-25 11:57 ` Yoshihiro Shimoda
2023-07-28 2:34 ` Manivannan Sadhasivam
2023-07-28 4:18 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width() Yoshihiro Shimoda
2023-07-31 23:53 ` Serge Semin
2023-08-01 1:50 ` Yoshihiro Shimoda
2023-08-07 22:53 ` Serge Semin
2023-08-07 23:40 ` Bjorn Helgaas
2023-08-08 0:15 ` Serge Semin
2023-08-08 15:08 ` Bjorn Helgaas
2023-08-08 21:16 ` Serge Semin
2023-07-21 7:44 ` [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling Yoshihiro Shimoda
2023-07-24 11:03 ` Manivannan Sadhasivam
2023-07-26 2:12 ` Yoshihiro Shimoda
2023-07-28 2:51 ` Manivannan Sadhasivam
2023-07-28 4:19 ` Yoshihiro Shimoda
2023-07-28 16:07 ` Serge Semin
2023-07-31 1:15 ` Yoshihiro Shimoda
2023-08-01 0:00 ` Serge Semin
2023-08-01 6:26 ` Yoshihiro Shimoda
2023-08-02 10:46 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 10/20] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting Yoshihiro Shimoda
2023-07-24 11:29 ` Manivannan Sadhasivam
2023-07-26 2:26 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 11/20] PCI: dwc: Add EDMA_UNROLL capability flag Yoshihiro Shimoda
2023-07-24 11:35 ` Manivannan Sadhasivam
2023-07-26 2:58 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 12/20] PCI: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
2023-07-24 11:36 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit() Yoshihiro Shimoda
2023-07-21 9:23 ` Sergei Shtylyov
2023-07-24 11:40 ` Manivannan Sadhasivam
2023-07-26 3:02 ` Yoshihiro Shimoda
2023-08-01 0:15 ` Serge Semin
2023-08-02 10:40 ` Manivannan Sadhasivam
2023-08-01 0:22 ` Serge Semin
2023-08-01 6:27 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 14/20] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 15/20] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 16/20] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 17/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
2023-07-24 12:28 ` Manivannan Sadhasivam
2023-08-01 1:06 ` Serge Semin
2023-08-01 6:46 ` Yoshihiro Shimoda
2023-08-01 18:28 ` Serge Semin
2023-08-02 10:36 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 18/20] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
2023-08-01 1:36 ` Serge Semin
2023-08-01 6:59 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 19/20] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 20/20] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller Yoshihiro Shimoda
2023-07-24 10:53 ` [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Serge Semin
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