From: Serge Semin <fancer.lancer@gmail.com>
To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
bhelgaas@google.com, Bjorn Helgaas <helgaas@kernel.org>
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
Manivannan Sadhasivam <mani@kernel.org>
Subject: Re: [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
Date: Tue, 1 Aug 2023 02:53:32 +0300 [thread overview]
Message-ID: <4ojfda5tlfu5wnljydzg7jncaa2zmhzgaqn723sst5rp44tfbl@j6ndm27ejinb> (raw)
In-Reply-To: <20230721074452.65545-9-yoshihiro.shimoda.uh@renesas.com>
On Fri, Jul 21, 2023 at 04:44:40PM +0900, Yoshihiro Shimoda wrote:
> To improve code readability, add dw_pcie_link_set_max_link_width().
You completely ignored all my comments regarding this patch again.
It's getting to be annoying really.
Once again: "This patch is a preparation before adding the
Max-Link-width capability setup which would in its turn complete the
max-link-width setup procedure defined by Synopsys in the HW-manual.
Seeing there is a max-link-speed setup method defined in the DW PCIe
core driver it would be good to have a similar function for the link
width setup. That's why we need to define a dedicated function first
from already implemented but incomplete link-width setting up
code." This is what should have been described in the commit log.
If you were a side-reader of the patch could you guess that from your
commit log and the patch content? I bet you couldn't. That's why a
very thorough description is important.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 86 ++++++++++----------
> 1 file changed, 41 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 2d0f816fa0ab..5cca34140d2a 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -728,6 +728,46 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
>
> }
>
> +static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> +{
> + u32 lwsc, plc;
> +
> + if (!num_lanes)
> + return;
> +
> + /* Set the number of lanes */
> + plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
> + plc &= ~PORT_LINK_FAST_LINK_MODE;
Once again: this masking is unrelated to the link width setup.
Moreover it's completely redundant in here and in the original code.
See further for details.
> + plc &= ~PORT_LINK_MODE_MASK;
> +
> + /* Set link width speed control register */
> + lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> + lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK;
> + switch (num_lanes) {
> + case 1:
> + plc |= PORT_LINK_MODE_1_LANES;
> + lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES;
> + break;
> + case 2:
> + plc |= PORT_LINK_MODE_2_LANES;
> + lwsc |= PORT_LOGIC_LINK_WIDTH_2_LANES;
> + break;
> + case 4:
> + plc |= PORT_LINK_MODE_4_LANES;
> + lwsc |= PORT_LOGIC_LINK_WIDTH_4_LANES;
> + break;
> + case 8:
> + plc |= PORT_LINK_MODE_8_LANES;
> + lwsc |= PORT_LOGIC_LINK_WIDTH_8_LANES;
> + break;
> + default:
> + dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
> + return;
> + }
> + dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> +}
> +
> void dw_pcie_iatu_detect(struct dw_pcie *pci)
> {
> int max_region, ob, ib;
> @@ -1009,49 +1049,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
> val |= PORT_LINK_DLL_LINK_EN;
> dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
>
> - if (!pci->num_lanes) {
> - dev_dbg(pci->dev, "Using h/w default number of lanes\n");
> - return;
> - }
> -
> - /* Set the number of lanes */
> - val &= ~PORT_LINK_FAST_LINK_MODE;
My series contains the patch which drops this line:
https://patchwork.kernel.org/project/linux-pci/patch/20230611192005.25636-6-Sergey.Semin@baikalelectronics.ru/
So either pick my patch up and add it to your series or still pick it up
but with changing the authorship and adding me under the Suggested-by
tag with the email-address I am using to review your series. Bjorn,
what approach would you prefer? Perhaps alternative?
Note the patch I am talking about doesn't contain anything what
couldn't be merged in. The problem with my series is in completely
another dimension.
Bjorn
> - val &= ~PORT_LINK_MODE_MASK;
> - switch (pci->num_lanes) {
> - case 1:
> - val |= PORT_LINK_MODE_1_LANES;
> - break;
> - case 2:
> - val |= PORT_LINK_MODE_2_LANES;
> - break;
> - case 4:
> - val |= PORT_LINK_MODE_4_LANES;
> - break;
> - case 8:
> - val |= PORT_LINK_MODE_8_LANES;
> - break;
> - default:
> - dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes);
> - return;
> - }
> - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
> -
> - /* Set link width speed control register */
> - val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> - val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
> - switch (pci->num_lanes) {
> - case 1:
> - val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
> - break;
> - case 2:
> - val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
> - break;
> - case 4:
> - val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
> - break;
> - case 8:
> - val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
> - break;
> - }
> - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> + dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
> }
> --
> 2.25.1
>
next prev parent reply other threads:[~2023-07-31 23:53 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 01/20] PCI: Add INTx Mechanism Messages macros Yoshihiro Shimoda
2023-07-24 7:25 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 02/20] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX Yoshihiro Shimoda
2023-07-21 8:10 ` Damien Le Moal
2023-07-24 7:32 ` Manivannan Sadhasivam
2023-07-29 1:35 ` Serge Semin
2023-07-29 1:55 ` Damien Le Moal
2023-07-29 1:58 ` Damien Le Moal
2023-07-29 2:02 ` Serge Semin
2023-07-29 15:32 ` Bjorn Helgaas
2023-07-30 4:58 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 03/20] PCI: dwc: Rename "legacy_irq" to "INTx_irq" Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu() Yoshihiro Shimoda
2023-07-24 7:45 ` Manivannan Sadhasivam
2023-07-26 5:02 ` Serge Semin
2023-07-26 13:00 ` Manivannan Sadhasivam
2023-07-26 23:38 ` Serge Semin
2023-07-27 1:06 ` Yoshihiro Shimoda
2023-07-27 11:03 ` Manivannan Sadhasivam
2023-07-27 12:21 ` Serge Semin
2023-07-29 2:06 ` Serge Semin
2023-07-31 1:24 ` Yoshihiro Shimoda
2023-07-31 21:33 ` Serge Semin
2023-08-01 1:29 ` Yoshihiro Shimoda
2023-08-01 1:44 ` Serge Semin
2023-08-01 7:02 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 05/20] PCI: dwc: Add outbound MSG TLPs support Yoshihiro Shimoda
2023-07-24 8:12 ` Manivannan Sadhasivam
2023-07-29 1:40 ` Serge Semin
2023-07-31 1:18 ` Yoshihiro Shimoda
2023-07-31 22:11 ` Serge Semin
2023-08-01 1:31 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 06/20] PCI: designware-ep: Add INTx IRQs support Yoshihiro Shimoda
2023-07-24 8:34 ` Manivannan Sadhasivam
2023-07-26 3:03 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 07/20] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Yoshihiro Shimoda
2023-07-24 9:24 ` Manivannan Sadhasivam
2023-07-25 11:57 ` Yoshihiro Shimoda
2023-07-28 2:34 ` Manivannan Sadhasivam
2023-07-28 4:18 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width() Yoshihiro Shimoda
2023-07-31 23:53 ` Serge Semin [this message]
2023-08-01 1:50 ` Yoshihiro Shimoda
2023-08-07 22:53 ` Serge Semin
2023-08-07 23:40 ` Bjorn Helgaas
2023-08-08 0:15 ` Serge Semin
2023-08-08 15:08 ` Bjorn Helgaas
2023-08-08 21:16 ` Serge Semin
2023-07-21 7:44 ` [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling Yoshihiro Shimoda
2023-07-24 11:03 ` Manivannan Sadhasivam
2023-07-26 2:12 ` Yoshihiro Shimoda
2023-07-28 2:51 ` Manivannan Sadhasivam
2023-07-28 4:19 ` Yoshihiro Shimoda
2023-07-28 16:07 ` Serge Semin
2023-07-31 1:15 ` Yoshihiro Shimoda
2023-08-01 0:00 ` Serge Semin
2023-08-01 6:26 ` Yoshihiro Shimoda
2023-08-02 10:46 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 10/20] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting Yoshihiro Shimoda
2023-07-24 11:29 ` Manivannan Sadhasivam
2023-07-26 2:26 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 11/20] PCI: dwc: Add EDMA_UNROLL capability flag Yoshihiro Shimoda
2023-07-24 11:35 ` Manivannan Sadhasivam
2023-07-26 2:58 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 12/20] PCI: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
2023-07-24 11:36 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit() Yoshihiro Shimoda
2023-07-21 9:23 ` Sergei Shtylyov
2023-07-24 11:40 ` Manivannan Sadhasivam
2023-07-26 3:02 ` Yoshihiro Shimoda
2023-08-01 0:15 ` Serge Semin
2023-08-02 10:40 ` Manivannan Sadhasivam
2023-08-01 0:22 ` Serge Semin
2023-08-01 6:27 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 14/20] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 15/20] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 16/20] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 17/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
2023-07-24 12:28 ` Manivannan Sadhasivam
2023-08-01 1:06 ` Serge Semin
2023-08-01 6:46 ` Yoshihiro Shimoda
2023-08-01 18:28 ` Serge Semin
2023-08-02 10:36 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 18/20] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
2023-08-01 1:36 ` Serge Semin
2023-08-01 6:59 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 19/20] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 20/20] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller Yoshihiro Shimoda
2023-07-24 10:53 ` [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Serge Semin
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