From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
To: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org
Cc: marek.vasut+renesas@gmail.com, fancer.lancer@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Subject: [PATCH v19 03/19] PCI: dwc: Add outbound MSG TLPs support
Date: Wed, 23 Aug 2023 18:11:37 +0900 [thread overview]
Message-ID: <20230823091153.2578417-4-yoshihiro.shimoda.uh@renesas.com> (raw)
In-Reply-To: <20230823091153.2578417-1-yoshihiro.shimoda.uh@renesas.com>
Add "code" and "routing" into struct dw_pcie_ob_atu_cfg for triggering
INTx IRQs by iATU in the PCIe endpoint mode in near the future.
PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of
MsgD. So, this implementation supports the data-less messages only
for now.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 780b1e38e763..d1dfe6f2eb4c 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -498,7 +498,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
upper_32_bits(atu->pci_addr));
- val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
+ val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
dw_pcie_ver_is_ge(pci, 460A))
val |= PCIE_ATU_INCREASE_REGION_SIZE;
@@ -506,7 +506,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
val = dw_pcie_enable_ecrc(val);
dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
- dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
+ val = PCIE_ATU_ENABLE;
+ if (atu->type == PCIE_ATU_TYPE_MSG) {
+ /* The data-less messages only for now */
+ val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
+ }
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
/*
* Make sure ATU enable takes effect before any subsequent config
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 05fbd361ecc3..d31c018a3803 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -147,11 +147,13 @@
#define PCIE_ATU_TYPE_IO 0x2
#define PCIE_ATU_TYPE_CFG0 0x4
#define PCIE_ATU_TYPE_CFG1 0x5
+#define PCIE_ATU_TYPE_MSG 0x10
#define PCIE_ATU_TD BIT(8)
#define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
#define PCIE_ATU_REGION_CTRL2 0x004
#define PCIE_ATU_ENABLE BIT(31)
#define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
+#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22)
#define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
#define PCIE_ATU_LOWER_BASE 0x008
#define PCIE_ATU_UPPER_BASE 0x00C
@@ -292,6 +294,8 @@ struct dw_pcie_ob_atu_cfg {
int index;
int type;
u8 func_no;
+ u8 code;
+ u8 routing;
u64 cpu_addr;
u64 pci_addr;
u64 size;
--
2.25.1
next prev parent reply other threads:[~2023-08-23 9:31 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-23 9:11 [PATCH v19 00/19] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 01/19] PCI: Add INTx Mechanism Messages macros Yoshihiro Shimoda
2023-08-23 10:18 ` Serge Semin
2023-08-24 2:57 ` Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 02/19] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu() Yoshihiro Shimoda
2023-08-23 9:11 ` Yoshihiro Shimoda [this message]
2023-08-23 9:11 ` [PATCH v19 04/19] PCI: designware-ep: Add INTx IRQs support Yoshihiro Shimoda
2023-08-23 10:32 ` Serge Semin
2023-08-24 1:58 ` Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 05/19] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Yoshihiro Shimoda
2023-08-23 10:46 ` Serge Semin
2023-08-24 3:13 ` Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 06/19] PCI: dwc: Add dw_pcie_link_set_max_link_width() Yoshihiro Shimoda
2023-08-23 10:51 ` Serge Semin
2023-08-23 9:11 ` [PATCH v19 07/19] PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 08/19] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 09/19] PCI: dwc: Add EDMA_UNROLL capability flag Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 10/19] PCI: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 11/19] PCI: dwc: Expose dw_pcie_write_dbi2() " Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 12/19] PCI: dwc: endpoint: Introduce .pre_init() and .deinit() Yoshihiro Shimoda
2023-08-23 11:14 ` Serge Semin
2023-08-23 9:11 ` [PATCH v19 13/19] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 14/19] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 15/19] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 16/19] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
2023-08-23 11:55 ` Serge Semin
2023-08-24 9:58 ` Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 17/19] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
2023-08-23 12:02 ` Serge Semin
2023-08-24 9:59 ` Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 18/19] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
2023-08-23 12:04 ` Serge Semin
2023-08-23 9:11 ` [PATCH v19 19/19] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller Yoshihiro Shimoda
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