From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
To: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org
Cc: marek.vasut+renesas@gmail.com, fancer.lancer@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Subject: [PATCH v19 05/19] PCI: dwc: endpoint: Add multiple PFs support for dbi2
Date: Wed, 23 Aug 2023 18:11:39 +0900 [thread overview]
Message-ID: <20230823091153.2578417-6-yoshihiro.shimoda.uh@renesas.com> (raw)
In-Reply-To: <20230823091153.2578417-1-yoshihiro.shimoda.uh@renesas.com>
The commit 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support
for DWC") added .func_conf_select() to get the configuration space of
different PFs and assumed that the offsets between dbi and dbi2 would
be the same. However, Renesas R-Car Gen4 PCIe controllers have different
offsets of function 1: dbi (+0x1000) and dbi2 (+0x800). To get
the offset for dbi2, add .get_dbi2_offset() and
dw_pcie_ep_get_dbi2_offset().
Note:
- .func_conf_select() should be renamed later.
- dw_pcie_ep_get_dbi2_offset() will call .func_conf_select()
if .get_dbi2_offset() doesn't exist for backward compatibility.
- dw_pcie_writeX_{dbi/dbi2} APIs accepted the func_no argument,
so that these offset calculations are contained in the API
definitions itself as it should.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
.../pci/controller/dwc/pcie-designware-ep.c | 32 ++++++++++++++-----
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 4a8c116cdd4b..500b092984b0 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -54,21 +54,35 @@ static unsigned int dw_pcie_ep_func_select(struct dw_pcie_ep *ep, u8 func_no)
return func_offset;
}
+static unsigned int dw_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep, u8 func_no)
+{
+ unsigned int dbi2_offset = 0;
+
+ if (ep->ops->get_dbi2_offset)
+ dbi2_offset = ep->ops->get_dbi2_offset(ep, func_no);
+ else if (ep->ops->func_conf_select) /* for backward compatibility */
+ dbi2_offset = ep->ops->func_conf_select(ep, func_no);
+
+ return dbi2_offset;
+}
+
static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no,
enum pci_barno bar, int flags)
{
- u32 reg;
- unsigned int func_offset = 0;
+ unsigned int func_offset, dbi2_offset;
struct dw_pcie_ep *ep = &pci->ep;
+ u32 reg, reg_dbi2;
func_offset = dw_pcie_ep_func_select(ep, func_no);
+ dbi2_offset = dw_pcie_ep_get_dbi2_offset(ep, func_no);
reg = func_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
+ reg_dbi2 = dbi2_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
dw_pcie_dbi_ro_wr_en(pci);
- dw_pcie_writel_dbi2(pci, reg, 0x0);
+ dw_pcie_writel_dbi2(pci, reg_dbi2, 0x0);
dw_pcie_writel_dbi(pci, reg, 0x0);
if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
- dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
+ dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, 0x0);
dw_pcie_writel_dbi(pci, reg + 4, 0x0);
}
dw_pcie_dbi_ro_wr_dis(pci);
@@ -229,16 +243,18 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
{
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ unsigned int func_offset, dbi2_offset;
enum pci_barno bar = epf_bar->barno;
size_t size = epf_bar->size;
int flags = epf_bar->flags;
- unsigned int func_offset = 0;
+ u32 reg, reg_dbi2;
int ret, type;
- u32 reg;
func_offset = dw_pcie_ep_func_select(ep, func_no);
+ dbi2_offset = dw_pcie_ep_get_dbi2_offset(ep, func_no);
reg = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset;
+ reg_dbi2 = PCI_BASE_ADDRESS_0 + (4 * bar) + dbi2_offset;
if (!(flags & PCI_BASE_ADDRESS_SPACE))
type = PCIE_ATU_TYPE_MEM;
@@ -254,11 +270,11 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
dw_pcie_dbi_ro_wr_en(pci);
- dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
+ dw_pcie_writel_dbi2(pci, reg_dbi2, lower_32_bits(size - 1));
dw_pcie_writel_dbi(pci, reg, flags);
if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
- dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
+ dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, upper_32_bits(size - 1));
dw_pcie_writel_dbi(pci, reg + 4, 0);
}
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index c17e5255fab6..7d02401fc783 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -343,6 +343,7 @@ struct dw_pcie_ep_ops {
* driver.
*/
unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
+ unsigned int (*get_dbi2_offset)(struct dw_pcie_ep *ep, u8 func_no);
};
struct dw_pcie_ep_func {
--
2.25.1
next prev parent reply other threads:[~2023-08-23 9:43 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-23 9:11 [PATCH v19 00/19] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 01/19] PCI: Add INTx Mechanism Messages macros Yoshihiro Shimoda
2023-08-23 10:18 ` Serge Semin
2023-08-24 2:57 ` Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 02/19] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu() Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 03/19] PCI: dwc: Add outbound MSG TLPs support Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 04/19] PCI: designware-ep: Add INTx IRQs support Yoshihiro Shimoda
2023-08-23 10:32 ` Serge Semin
2023-08-24 1:58 ` Yoshihiro Shimoda
2023-08-23 9:11 ` Yoshihiro Shimoda [this message]
2023-08-23 10:46 ` [PATCH v19 05/19] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Serge Semin
2023-08-24 3:13 ` Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 06/19] PCI: dwc: Add dw_pcie_link_set_max_link_width() Yoshihiro Shimoda
2023-08-23 10:51 ` Serge Semin
2023-08-23 9:11 ` [PATCH v19 07/19] PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 08/19] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 09/19] PCI: dwc: Add EDMA_UNROLL capability flag Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 10/19] PCI: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 11/19] PCI: dwc: Expose dw_pcie_write_dbi2() " Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 12/19] PCI: dwc: endpoint: Introduce .pre_init() and .deinit() Yoshihiro Shimoda
2023-08-23 11:14 ` Serge Semin
2023-08-23 9:11 ` [PATCH v19 13/19] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 14/19] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 15/19] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 16/19] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
2023-08-23 11:55 ` Serge Semin
2023-08-24 9:58 ` Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 17/19] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
2023-08-23 12:02 ` Serge Semin
2023-08-24 9:59 ` Yoshihiro Shimoda
2023-08-23 9:11 ` [PATCH v19 18/19] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
2023-08-23 12:04 ` Serge Semin
2023-08-23 9:11 ` [PATCH v19 19/19] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller Yoshihiro Shimoda
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