From: Frank Li <Frank.Li@nxp.com>
To: krzysztof.kozlowski@linaro.org
Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org,
devicetree@vger.kernel.org, festevam@gmail.com,
helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev,
kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org,
kw@linux.com, l.stach@pengutronix.de,
linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org,
robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org
Subject: [PATCH v7 12/16] PCI: imx6: Add iMX95 PCIe support
Date: Wed, 27 Dec 2023 13:27:23 -0500 [thread overview]
Message-ID: <20231227182727.1747435-13-Frank.Li@nxp.com> (raw)
In-Reply-To: <20231227182727.1747435-1-Frank.Li@nxp.com>
Add iMX95 PCIe basic root complex function support.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Notes:
Change from v1 to v3
- none
drivers/pci/controller/dwc/pci-imx6.c | 90 +++++++++++++++++++++++++--
1 file changed, 85 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index d66a2db53bdb7..9e60ab6f1885a 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -42,6 +42,25 @@
#define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12)
#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
+#define IMX95_PCIE_PHY_GEN_CTRL 0x0
+#define IMX95_PCIE_REF_USE_PAD BIT(17)
+
+#define IMX95_PCIE_PHY_MPLLA_CTRL 0x10
+#define IMX95_PCIE_PHY_MPLL_STATE BIT(30)
+
+#define IMX95_PCIE_SS_RW_REG_0 0xf0
+#define IMX95_PCIE_REF_CLKEN BIT(23)
+#define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9)
+
+#define IMX95_PE0_GEN_CTRL_1 0x1050
+#define IMX95_PCIE_DEVICE_TYPE GENMASK(3, 0)
+
+#define IMX95_PE0_GEN_CTRL_3 0x1058
+#define IMX95_PCIE_LTSSM_EN BIT(0)
+
+#define IMX95_PE0_PM_STS 0x1064
+#define IMX95_PCIE_PM_LINKST_IN_L2 BIT(14)
+
#define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
enum imx6_pcie_variants {
@@ -52,6 +71,7 @@ enum imx6_pcie_variants {
IMX8MQ,
IMX8MM,
IMX8MP,
+ IMX95,
IMX8MQ_EP,
IMX8MM_EP,
IMX8MP_EP,
@@ -63,6 +83,7 @@ enum imx6_pcie_variants {
#define IMX6_PCIE_FLAG_HAS_PHY BIT(3)
#define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4)
#define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5)
+#define IMX6_PCIE_FLAG_HAS_SERDES BIT(6)
#define imx6_check_flag(pci, val) (pci->drvdata->flags & val)
@@ -179,6 +200,24 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
}
+static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie)
+{
+ regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ IMX95_PCIE_SS_RW_REG_0,
+ IMX95_PCIE_PHY_CR_PARA_SEL,
+ IMX95_PCIE_PHY_CR_PARA_SEL);
+
+ regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ IMX95_PCIE_PHY_GEN_CTRL,
+ IMX95_PCIE_REF_USE_PAD, 0);
+ regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ IMX95_PCIE_SS_RW_REG_0,
+ IMX95_PCIE_REF_CLKEN,
+ IMX95_PCIE_REF_CLKEN);
+
+ return 0;
+}
+
static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
{
const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
@@ -579,6 +618,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
break;
case IMX7D:
+ case IMX95:
break;
case IMX8MM:
case IMX8MM_EP:
@@ -696,10 +736,19 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
{
struct dw_pcie *pci = imx6_pcie->pci;
struct device *dev = pci->dev;
+ u32 val;
reset_control_deassert(imx6_pcie->pciephy_reset);
switch (imx6_pcie->drvdata->variant) {
+ case IMX95:
+ /* Polling the MPLL_STATE */
+ if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
+ IMX95_PCIE_PHY_MPLLA_CTRL, val,
+ val & IMX95_PCIE_PHY_MPLL_STATE,
+ 10, 10000))
+ dev_err(dev, "PCIe PLL lock timeout\n");
+ break;
case IMX7D:
/* Workaround for ERR010728, failure of PCI-e PLL VCO to
* oscillate, especially when cold. This turns off "Duty-cycle
@@ -1281,12 +1330,32 @@ static int imx6_pcie_probe(struct platform_device *pdev)
return PTR_ERR(imx6_pcie->turnoff_reset);
}
+ if (imx6_pcie->drvdata->gpr) {
/* Grab GPR config register range */
- imx6_pcie->iomuxc_gpr =
- syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
- if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
- dev_err(dev, "unable to find iomuxc registers\n");
- return PTR_ERR(imx6_pcie->iomuxc_gpr);
+ imx6_pcie->iomuxc_gpr =
+ syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
+ if (IS_ERR(imx6_pcie->iomuxc_gpr))
+ return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
+ "unable to find iomuxc registers\n");
+ }
+
+ if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) {
+ void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app");
+
+ if (IS_ERR(off))
+ return dev_err_probe(dev, PTR_ERR(off),
+ "unable to find serdes registers\n");
+
+ static struct regmap_config regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ };
+
+ imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(imx6_pcie->iomuxc_gpr))
+ return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
+ "unable to find iomuxc registers\n");
}
/* Grab PCIe PHY Tx Settings */
@@ -1447,6 +1516,16 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
},
+ [IMX95] = {
+ .variant = IMX95,
+ .flags = IMX6_PCIE_FLAG_HAS_SERDES,
+ .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"},
+ .ltssm_off = IMX95_PE0_GEN_CTRL_3,
+ .ltssm_mask = IMX95_PCIE_LTSSM_EN,
+ .mode_off[0] = IMX95_PE0_GEN_CTRL_1,
+ .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
+ .init_phy = imx95_pcie_init_phy,
+ },
[IMX8MQ_EP] = {
.variant = IMX8MQ_EP,
.flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
@@ -1488,6 +1567,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
+ { .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], },
{ .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
{ .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
{ .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
--
2.34.1
next prev parent reply other threads:[~2023-12-27 18:28 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-27 18:27 [PATCH v7 00/16] PCI: imx6: Clean up and add imx95 pci support Frank Li
2023-12-27 18:27 ` [PATCH v7 01/16] PCI: imx6: Simplify clock handling by using bulk_clk_*() function Frank Li
2024-01-02 8:47 ` Marco Felsch
2024-01-03 17:02 ` Frank Li
2024-01-04 10:07 ` Marco Felsch
2024-01-06 15:27 ` Manivannan Sadhasivam
2024-01-06 16:48 ` Frank Li
2024-01-07 3:02 ` Manivannan Sadhasivam
2023-12-27 18:27 ` [PATCH v7 02/16] PCI: imx6: Simplify phy handling by using by using IMX6_PCIE_FLAG_HAS_PHY Frank Li
2024-01-06 15:33 ` Manivannan Sadhasivam
2024-01-06 16:50 ` Frank Li
2024-01-07 3:04 ` Manivannan Sadhasivam
2023-12-27 18:27 ` [PATCH v7 03/16] PCI: imx6: Simplify reset handling by using by using *_FLAG_HAS_*_RESET Frank Li
2023-12-27 18:27 ` [PATCH v7 04/16] dt-bindings: imx6q-pcie: Add linux,pci-domain as required for iMX8MQ Frank Li
2024-01-07 3:15 ` Manivannan Sadhasivam
2024-01-07 4:47 ` Frank Li
2024-01-07 5:19 ` Manivannan Sadhasivam
2024-01-07 5:38 ` Frank Li
2024-01-07 6:29 ` Manivannan Sadhasivam
2024-01-09 3:49 ` Rob Herring
2024-01-09 3:49 ` Rob Herring
2023-12-27 18:27 ` [PATCH v7 05/16] PCI: imx6: Using "linux,pci-domain" as slot ID Frank Li
2024-01-07 3:22 ` Manivannan Sadhasivam
2023-12-27 18:27 ` [PATCH v7 06/16] PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask Frank Li
2024-01-07 3:24 ` Manivannan Sadhasivam
2023-12-27 18:27 ` [PATCH v7 07/16] PCI: imx6: Simplify configure_type() by using mode_off and mode_mask Frank Li
2024-01-07 5:16 ` Manivannan Sadhasivam
2024-01-07 5:32 ` Frank Li
2024-01-07 5:35 ` Manivannan Sadhasivam
2023-12-27 18:27 ` [PATCH v7 08/16] PCI: imx6: Simplify switch-case logic by involve init_phy callback Frank Li
2024-01-07 5:33 ` Manivannan Sadhasivam
2023-12-27 18:27 ` [PATCH v7 09/16] dt-bindings: imx6q-pcie: Clean up irrationality clocks check Frank Li
2024-01-07 5:34 ` Manivannan Sadhasivam
2023-12-27 18:27 ` [PATCH v7 10/16] dt-bindings: imx6q-pcie: restruct reg and reg-name Frank Li
2024-01-07 5:35 ` Manivannan Sadhasivam
2023-12-27 18:27 ` [PATCH v7 11/16] dt-bindings: imx6q-pcie: Add imx95 pcie compatible string Frank Li
2024-01-02 16:03 ` Rob Herring
2023-12-27 18:27 ` Frank Li [this message]
2024-01-07 5:51 ` [PATCH v7 12/16] PCI: imx6: Add iMX95 PCIe support Manivannan Sadhasivam
2023-12-27 18:27 ` [PATCH v7 13/16] PCI: imx6: Clean up get addr_space code Frank Li
2024-01-07 5:55 ` Manivannan Sadhasivam
2023-12-27 18:27 ` [PATCH v7 14/16] PCI: imx6: Add epc_features in imx6_pcie_drvdata Frank Li
2024-01-07 6:16 ` Manivannan Sadhasivam
2023-12-27 18:27 ` [PATCH v7 15/16] dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string Frank Li
2024-01-09 3:53 ` Rob Herring
2023-12-27 18:27 ` [PATCH v7 16/16] PCI: imx6: Add iMX95 Endpoint (EP) function support Frank Li
2024-01-07 6:26 ` Manivannan Sadhasivam
2024-01-08 17:39 ` Frank Li
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