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From: Marc Zyngier <maz@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: daire.mcnamara@microchip.com, lorenzo.pieralisi@arm.com,
	bhelgaas@google.com, robh@kernel.org, linux-pci@vger.kernel.org,
	robh+dt@kernel.org, devicetree@vger.kernel.org,
	david.abdurachmanov@gmail.com, cyril.jean@microchip.com
Subject: Re: [PATCH v21 3/4] PCI: microchip: Add host driver for Microchip PCIe controller
Date: Fri, 28 Jan 2022 09:55:04 +0000	[thread overview]
Message-ID: <87pmoc5gnb.wl-maz@kernel.org> (raw)
In-Reply-To: <20220127202000.GA126335@bhelgaas>

On Thu, 27 Jan 2022 20:20:00 +0000,
Bjorn Helgaas <helgaas@kernel.org> wrote:
> 
> [+cc Marc]
> 
> On Mon, Jan 25, 2021 at 04:29:33PM +0000, daire.mcnamara@microchip.com wrote:
> > From: Daire McNamara <daire.mcnamara@microchip.com>
> > 
> > Add support for the Microchip PolarFire PCIe controller when
> > configured in host (Root Complex) mode.
> 
> > +static void mc_handle_msi(struct irq_desc *desc)
> > +{
> > +	struct mc_port *port = irq_desc_get_handler_data(desc);
> > +	struct device *dev = port->dev;
> > +	struct mc_msi *msi = &port->msi;
> > +	void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
> > +	unsigned long status;
> > +	u32 bit;
> > +	u32 virq;
> > +
> > +	status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
> > +	if (status & PM_MSI_INT_MSI_MASK) {
> > +		status = readl_relaxed(bridge_base_addr + ISTATUS_MSI);
> > +		for_each_set_bit(bit, &status, msi->num_vectors) {
> > +			virq = irq_find_mapping(msi->dev_domain, bit);
> > +			if (virq)
> > +				generic_handle_irq(virq);

Wrong construct. Please use generic_handle_domain_irq().

> > +			else
> > +				dev_err_ratelimited(dev, "bad MSI IRQ %d\n", bit);
> > +		}
> > +	}
> > +}
> > +
> > +static void mc_msi_bottom_irq_ack(struct irq_data *data)
> > +{
> > +	struct mc_port *port = irq_data_get_irq_chip_data(data);
> > +	void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
> > +	u32 bitpos = data->hwirq;
> > +	unsigned long status;
> > +
> > +	writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI);
> > +	status = readl_relaxed(bridge_base_addr + ISTATUS_MSI);
> > +	if (!status)
> > +		writel_relaxed(BIT(PM_MSI_INT_MSI_SHIFT), bridge_base_addr + ISTATUS_LOCAL);
> 
> This looks like it might be racy.  What happens if we read 0 from
> ISTATUS_MSI, but a new MSI is latched before we write ISTATUS_LOCAL?

I agree, this looks really odd. The irq_ack callback is per interrupt,
while this seems to deal with some global state. This cannot be right.

	M.

-- 
Without deviation from the norm, progress is not possible.

  reply	other threads:[~2022-01-28  9:55 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-25 16:29 [PATCH v21 0/4] " daire.mcnamara
2021-01-25 16:29 ` [PATCH v21 1/4] PCI: Call platform_set_drvdata earlier in devm_pci_alloc_host_bridge daire.mcnamara
2021-01-25 16:29 ` [PATCH v21 2/4] dt-bindings: PCI: microchip: Add Microchip PolarFire host binding daire.mcnamara
2021-01-25 16:29 ` [PATCH v21 3/4] PCI: microchip: Add host driver for Microchip PCIe controller daire.mcnamara
2021-02-01 19:05   ` Lorenzo Pieralisi
     [not found]     ` <MN2PR11MB42691AE1B54DEAB5C1BAA11D96B59@MN2PR11MB4269.namprd11.prod.outlook.com>
2021-02-04 10:20       ` Lorenzo Pieralisi
2021-02-10 13:07   ` Geert Uytterhoeven
2021-02-11 13:03     ` Ben Dooks
2021-02-11 13:07       ` Geert Uytterhoeven
2021-02-16  9:54         ` Daire.McNamara
2022-01-27 20:20   ` Bjorn Helgaas
2022-01-28  9:55     ` Marc Zyngier [this message]
2022-01-28 13:16       ` Bjorn Helgaas
2021-01-25 16:29 ` [PATCH v21 4/4] MAINTAINERS: Add Daire McNamara as maintainer for the Microchip PCIe driver daire.mcnamara
2021-02-04 11:42 ` [PATCH v21 0/4] PCI: microchip: Add host driver for Microchip PCIe controller Lorenzo Pieralisi

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