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From: "Wan Mohamad, Wan Ahmad Zainie"  <wan.ahmad.zainie.wan.mohamad@intel.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "bhelgaas@google.com" <bhelgaas@google.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"andriy.shevchenko@linux.intel.com" 
	<andriy.shevchenko@linux.intel.com>,
	"mgross@linux.intel.com" <mgross@linux.intel.com>,
	"Raja Subramanian,
	Lakshmi Bai"  <lakshmi.bai.raja.subramanian@intel.com>
Subject: RE: [PATCH 2/2] PCI: keembay: Add support for Intel Keem Bay
Date: Wed, 4 Nov 2020 12:03:39 +0000
Message-ID: <DM6PR11MB3721DE5452FA6C4CA3E23FC8DDEF0@DM6PR11MB3721.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20201103222223.GA269610@bjorn-Precision-5520>

> -----Original Message-----
> From: Bjorn Helgaas <helgaas@kernel.org>
> Sent: Wednesday, November 4, 2020 6:22 AM
> To: Wan Mohamad, Wan Ahmad Zainie
> <wan.ahmad.zainie.wan.mohamad@intel.com>
> Cc: bhelgaas@google.com; robh+dt@kernel.org; lorenzo.pieralisi@arm.com;
> linux-pci@vger.kernel.org; devicetree@vger.kernel.org;
> andriy.shevchenko@linux.intel.com; mgross@linux.intel.com; Raja
> Subramanian, Lakshmi Bai <lakshmi.bai.raja.subramanian@intel.com>
> Subject: Re: [PATCH 2/2] PCI: keembay: Add support for Intel Keem Bay
> 
> On Tue, Oct 27, 2020 at 02:00:11PM +0800, Wan Ahmad Zainie wrote:
> 
> > +static int keembay_pcie_link_up(struct dw_pcie *pci) {
> > +	struct keembay_pcie *pcie = dev_get_drvdata(pci->dev);
> > +	u32 val, mask;
> > +
> > +	val = keembay_pcie_readl(pcie, PCIE_REGS_PCIE_SII_PM_STATE);
> > +	mask = SMLH_LINK_UP | RDLH_LINK_UP;
> > +
> > +	return !!((val & mask) == mask);
> 
> I think the "!!" is redundant since you're applying it to a value that's a boolean
> already.  So you should be able to do:
> 
>   return (val & mask) == mask;
> 
> But it seems like "mask" just obfuscates a little bit, too.
> Personally I think it'd be easier to add something like:
> 
>   #define PCIE_REGS_PCIE_SII_LINK_UP  (SMLH_LINK_UP | RDLH_LINK_UP)
> 
> and then:
> 
>   if ((val & PCIE_REGS_PCIE_SII_LINK_UP) == PCIE_REGS_PCIE_SII_LINK_UP)
>     return 1;
>   return 0;

I will fix in v2, using the above as agreed by Andy.

> 
> or even:
> 
>   return (val & PCIE_REGS_PCIE_SII_LINK_UP) ==
> PCIE_REGS_PCIE_SII_LINK_UP;
> 
> > +static int keembay_pcie_establish_link(struct dw_pcie *pci) {
> > +	return 0;
> > +}
> 
> Are you sure you need this?  I see other cases where the .start_link pointer is
> left NULL, e.g., pci-exynos.c, pci-imx6.c, dw_ls1021_pcie_ops, etc.

Yes, as in endpoint mode, link initialization is done in boot firmware.
Leaving it NULL will cause pcie-designware-ep.c::dw_pcie_ep_start()
to return -EINVAL.

Rob is refactoring DWC code and looks like .start_link is used in root complex
mode too. I will make changes to above function in v2, by renaming to
keembay_pci2_start_link and add link initialization code for root complex
mode.

> 
> > +static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8
> func_no,
> > +				     enum pci_epc_irq_type type,
> > +				     u16 interrupt_num)
> > +{
> > +	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > +
> > +	switch (type) {
> > +	case PCI_EPC_IRQ_LEGACY:
> > +		/* Legacy interrupts are not supported in Keem Bay */
> > +		dev_err(pci->dev, "Unsupported IRQ type\n");
> 
> Might be nice to mention "legacy" here.

I will fix in v2, using string "Legacy IRQ is not supported".

> 
> > +		return -EINVAL;
> > +	case PCI_EPC_IRQ_MSI:
> > +		return dw_pcie_ep_raise_msi_irq(ep, func_no,
> interrupt_num);
> > +	case PCI_EPC_IRQ_MSIX:
> > +		return dw_pcie_ep_raise_msix_irq(ep, func_no,
> interrupt_num);
> > +	default:
> > +		dev_err(pci->dev, "Unknown IRQ type\n");
> 
> And maybe include the %d of "type"?

I will fix in v2, to show the value of "type".

Best regards,
Zainie

      parent reply index

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-27  6:00 [PATCH 0/2] " Wan Ahmad Zainie
2020-10-27  6:00 ` [PATCH 1/2] dt-bindings: PCI: Add Intel Keem Bay PCIe controller Wan Ahmad Zainie
2020-10-28 13:57   ` Rob Herring
2020-10-28 14:42   ` Rob Herring
2020-10-30 13:04     ` Wan Mohamad, Wan Ahmad Zainie
2020-10-30 14:55       ` Rob Herring
2020-11-03  6:01         ` Wan Mohamad, Wan Ahmad Zainie
2020-10-27  6:00 ` [PATCH 2/2] PCI: keembay: Add support for Intel Keem Bay Wan Ahmad Zainie
2020-10-28 14:22   ` Rob Herring
2020-10-28 15:34     ` Andy Shevchenko
2020-11-03  4:58     ` Wan Mohamad, Wan Ahmad Zainie
2020-11-03 22:22   ` Bjorn Helgaas
2020-11-04  9:36     ` Andy Shevchenko
2020-11-04 12:03     ` Wan Mohamad, Wan Ahmad Zainie [this message]

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