Linux-PCI Archive on lore.kernel.org
 help / color / Atom feed
From: "Wan Mohamad, Wan Ahmad Zainie"  <wan.ahmad.zainie.wan.mohamad@intel.com>
To: Rob Herring <robh@kernel.org>
Cc: "bhelgaas@google.com" <bhelgaas@google.com>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"andriy.shevchenko@linux.intel.com" 
	<andriy.shevchenko@linux.intel.com>,
	"mgross@linux.intel.com" <mgross@linux.intel.com>,
	"Raja Subramanian,
	Lakshmi Bai"  <lakshmi.bai.raja.subramanian@intel.com>
Subject: RE: [PATCH 1/2] dt-bindings: PCI: Add Intel Keem Bay PCIe controller
Date: Tue, 3 Nov 2020 06:01:57 +0000
Message-ID: <DM6PR11MB3721E3877611EEE08E90C2A9DD110@DM6PR11MB3721.namprd11.prod.outlook.com> (raw)
In-Reply-To: <CAL_Jsq+1HiYK09+piSqJz0Jo+F3XXfg0+qpKQSDL7G32c2P4Eg@mail.gmail.com>

Hi Rob.

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Friday, October 30, 2020 10:56 PM
> To: Wan Mohamad, Wan Ahmad Zainie
> <wan.ahmad.zainie.wan.mohamad@intel.com>
> Cc: bhelgaas@google.com; lorenzo.pieralisi@arm.com; linux-
> pci@vger.kernel.org; devicetree@vger.kernel.org;
> andriy.shevchenko@linux.intel.com; mgross@linux.intel.com; Raja
> Subramanian, Lakshmi Bai <lakshmi.bai.raja.subramanian@intel.com>
> Subject: Re: [PATCH 1/2] dt-bindings: PCI: Add Intel Keem Bay PCIe controller
> 
> On Fri, Oct 30, 2020 at 8:05 AM Wan Mohamad, Wan Ahmad Zainie
> <wan.ahmad.zainie.wan.mohamad@intel.com> wrote:
> >
> > Hi Rob.
> >
> > Thanks for the review.
> >
> > > -----Original Message-----
> > > From: Rob Herring <robh@kernel.org>
> > > Sent: Wednesday, October 28, 2020 10:42 PM
> > > To: Wan Mohamad, Wan Ahmad Zainie
> > > <wan.ahmad.zainie.wan.mohamad@intel.com>
> > > Cc: bhelgaas@google.com; lorenzo.pieralisi@arm.com; linux-
> > > pci@vger.kernel.org; devicetree@vger.kernel.org;
> > > andriy.shevchenko@linux.intel.com; mgross@linux.intel.com; Raja
> > > Subramanian, Lakshmi Bai <lakshmi.bai.raja.subramanian@intel.com>
> > > Subject: Re: [PATCH 1/2] dt-bindings: PCI: Add Intel Keem Bay PCIe
> > > controller
> > >
> > > On Tue, Oct 27, 2020 at 02:00:10PM +0800, Wan Ahmad Zainie wrote:

...

> > > > +  num-viewport:
> > > > +    description: Number of view ports configured in hardware.
> > > > +    $ref: /schemas/types.yaml#/definitions/uint32
> > > > +    default: 2
> > >
> > > Pretty sure it's not 2 if num-ib-windows and num-ob-windows are 4.
> >
> > As per pcie-designware-host.c, default value is 2, if it is not set.
> 
> Yes, that's true.
> 
> > My example and the DT in my system is 4.
> > I will fix in v2, by using const: 4.
> > Should I drop default?
> 
> Yes.
> 
> BTW, I'm going to make all 3 properties obsolete. I'm working on a patch to
> detect all this. It's pretty straight-forward, just see how many registers are
> writable. The WIP patch is on my for-kernelci branch.

I will take note on this.

I also take a look into for-kernelci branch. I will spend some time to try it
out with my patch.

> 
> The problem with these properties is they are defined as RC and EP specific,
> but they are really fixed h/w config independent of the mode. And num-
> viewport is incomplete because the inbound and outbound sizes are
> independent. The driver just currently doesn't use inbound windows for RC
> mode. Also, the driver claims there can be up to 256 windows, but I'm not
> really sure that's right. There's 2 platforms upstream (ls1088a and ls208xa)
> claiming 256 windows in DT, but testing with the detection code indicates
> they only have 16 IB and 16 OB windows. Perhaps if you have the DWC
> manual you could confirm what's possible.

Unfortunately, I don't have details on DWC manual. As for Keem Bay,
from the information in its databook, it is synthesized with 8 IB and 8 OB
windows. The values that I used for DT is based on recommendation from
our boot firmware team.

> 
> Rob

Best regards,
Zainie

  reply index

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-27  6:00 [PATCH 0/2] PCI: keembay: Add support for Intel Keem Bay Wan Ahmad Zainie
2020-10-27  6:00 ` [PATCH 1/2] dt-bindings: PCI: Add Intel Keem Bay PCIe controller Wan Ahmad Zainie
2020-10-28 13:57   ` Rob Herring
2020-10-28 14:42   ` Rob Herring
2020-10-30 13:04     ` Wan Mohamad, Wan Ahmad Zainie
2020-10-30 14:55       ` Rob Herring
2020-11-03  6:01         ` Wan Mohamad, Wan Ahmad Zainie [this message]
2020-10-27  6:00 ` [PATCH 2/2] PCI: keembay: Add support for Intel Keem Bay Wan Ahmad Zainie
2020-10-28 14:22   ` Rob Herring
2020-10-28 15:34     ` Andy Shevchenko
2020-11-03  4:58     ` Wan Mohamad, Wan Ahmad Zainie
2020-11-03 22:22   ` Bjorn Helgaas
2020-11-04  9:36     ` Andy Shevchenko
2020-11-04 12:03     ` Wan Mohamad, Wan Ahmad Zainie

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=DM6PR11MB3721E3877611EEE08E90C2A9DD110@DM6PR11MB3721.namprd11.prod.outlook.com \
    --to=wan.ahmad.zainie.wan.mohamad@intel.com \
    --cc=andriy.shevchenko@linux.intel.com \
    --cc=bhelgaas@google.com \
    --cc=devicetree@vger.kernel.org \
    --cc=lakshmi.bai.raja.subramanian@intel.com \
    --cc=linux-pci@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=mgross@linux.intel.com \
    --cc=robh@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Linux-PCI Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-pci/0 linux-pci/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-pci linux-pci/ https://lore.kernel.org/linux-pci \
		linux-pci@vger.kernel.org
	public-inbox-index linux-pci

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-pci


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git