* [PATCH 01/41] dt-bindings: phy: migrate QMP USB PHY bindings to qcom,sc8280xp-qmp-usb3-uni-phy.yaml
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 7:48 ` Johan Hovold
2023-03-24 9:43 ` Krzysztof Kozlowski
2023-03-24 2:24 ` [PATCH 02/41] dt-bindings: phy: migrate combo QMP PHY bindings to qcom,sc8280xp-qmp-usb43dp-phy.yaml Dmitry Baryshkov
` (39 subsequent siblings)
40 siblings, 2 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Migrate legacy bindings (described in qcom,msm8996-qmp-usb3-phy.yaml)
to qcom,sc8280xp-qmp-usb3-uni-phy.yaml. This removes a need to declare
the child PHY node or split resource regions.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qcom,msm8996-qmp-usb3-phy.yaml | 394 ------------------
.../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 236 ++++++++++-
2 files changed, 226 insertions(+), 404 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
deleted file mode 100644
index e81a38281f8c..000000000000
--- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
+++ /dev/null
@@ -1,394 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-usb3-phy.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm QMP PHY controller (USB, MSM8996)
-
-maintainers:
- - Vinod Koul <vkoul@kernel.org>
-
-description:
- QMP PHY controller supports physical layer functionality for a number of
- controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
-
- Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see
- qcom,sc8280xp-qmp-usb3-uni-phy.yaml.
-
-properties:
- compatible:
- enum:
- - qcom,ipq6018-qmp-usb3-phy
- - qcom,ipq8074-qmp-usb3-phy
- - qcom,msm8996-qmp-usb3-phy
- - qcom,msm8998-qmp-usb3-phy
- - qcom,qcm2290-qmp-usb3-phy
- - qcom,sc7180-qmp-usb3-phy
- - qcom,sc8180x-qmp-usb3-phy
- - qcom,sdm845-qmp-usb3-phy
- - qcom,sdm845-qmp-usb3-uni-phy
- - qcom,sdx55-qmp-usb3-uni-phy
- - qcom,sdx65-qmp-usb3-uni-phy
- - qcom,sm6115-qmp-usb3-phy
- - qcom,sm8150-qmp-usb3-phy
- - qcom,sm8150-qmp-usb3-uni-phy
- - qcom,sm8250-qmp-usb3-phy
- - qcom,sm8250-qmp-usb3-uni-phy
- - qcom,sm8350-qmp-usb3-phy
- - qcom,sm8350-qmp-usb3-uni-phy
- - qcom,sm8450-qmp-usb3-phy
-
- reg:
- minItems: 1
- items:
- - description: serdes
- - description: DP_COM
-
- "#address-cells":
- enum: [ 1, 2 ]
-
- "#size-cells":
- enum: [ 1, 2 ]
-
- ranges: true
-
- clocks:
- minItems: 3
- maxItems: 4
-
- clock-names:
- minItems: 3
- maxItems: 4
-
- power-domains:
- maxItems: 1
-
- resets:
- maxItems: 2
-
- reset-names:
- maxItems: 2
-
- vdda-phy-supply: true
-
- vdda-pll-supply: true
-
- vddp-ref-clk-supply: true
-
-patternProperties:
- "^phy@[0-9a-f]+$":
- type: object
- description: single PHY-provider child node
- properties:
- reg:
- minItems: 3
- maxItems: 6
-
- clocks:
- items:
- - description: PIPE clock
-
- clock-names:
- deprecated: true
- items:
- - const: pipe0
-
- "#clock-cells":
- const: 0
-
- clock-output-names:
- maxItems: 1
-
- "#phy-cells":
- const: 0
-
- required:
- - reg
- - clocks
- - "#clock-cells"
- - clock-output-names
- - "#phy-cells"
-
- additionalProperties: false
-
-required:
- - compatible
- - reg
- - "#address-cells"
- - "#size-cells"
- - ranges
- - clocks
- - clock-names
- - resets
- - reset-names
- - vdda-phy-supply
- - vdda-pll-supply
-
-additionalProperties: false
-
-allOf:
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sc7180-qmp-usb3-phy
- then:
- properties:
- clocks:
- maxItems: 4
- clock-names:
- items:
- - const: aux
- - const: cfg_ahb
- - const: ref
- - const: com_aux
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: phy
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sdm845-qmp-usb3-uni-phy
- then:
- properties:
- clocks:
- maxItems: 4
- clock-names:
- items:
- - const: aux
- - const: cfg_ahb
- - const: ref
- - const: com_aux
- resets:
- maxItems: 2
- reset-names:
- items:
- - const: phy
- - const: common
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,ipq8074-qmp-usb3-phy
- - qcom,msm8996-qmp-usb3-phy
- - qcom,msm8998-qmp-usb3-phy
- - qcom,sdx55-qmp-usb3-uni-phy
- - qcom,sdx65-qmp-usb3-uni-phy
- then:
- properties:
- clocks:
- maxItems: 3
- clock-names:
- items:
- - const: aux
- - const: cfg_ahb
- - const: ref
- resets:
- maxItems: 2
- reset-names:
- items:
- - const: phy
- - const: common
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sm8150-qmp-usb3-phy
- - qcom,sm8150-qmp-usb3-uni-phy
- - qcom,sm8250-qmp-usb3-uni-phy
- - qcom,sm8350-qmp-usb3-uni-phy
- then:
- properties:
- clocks:
- maxItems: 4
- clock-names:
- items:
- - const: aux
- - const: ref_clk_src
- - const: ref
- - const: com_aux
- resets:
- maxItems: 2
- reset-names:
- items:
- - const: phy
- - const: common
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sm8250-qmp-usb3-phy
- - qcom,sm8350-qmp-usb3-phy
- then:
- properties:
- clocks:
- maxItems: 3
- clock-names:
- items:
- - const: aux
- - const: ref_clk_src
- - const: com_aux
- resets:
- maxItems: 2
- reset-names:
- items:
- - const: phy
- - const: common
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,qcm2290-qmp-usb3-phy
- - qcom,sm6115-qmp-usb3-phy
- then:
- properties:
- clocks:
- maxItems: 3
- clock-names:
- items:
- - const: cfg_ahb
- - const: ref
- - const: com_aux
- resets:
- maxItems: 2
- reset-names:
- items:
- - const: phy_phy
- - const: phy
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sdm845-qmp-usb3-phy
- - qcom,sm8150-qmp-usb3-phy
- - qcom,sm8350-qmp-usb3-phy
- - qcom,sm8450-qmp-usb3-phy
- then:
- patternProperties:
- "^phy@[0-9a-f]+$":
- properties:
- reg:
- items:
- - description: TX lane 1
- - description: RX lane 1
- - description: PCS
- - description: TX lane 2
- - description: RX lane 2
- - description: PCS_MISC
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,msm8998-qmp-usb3-phy
- then:
- patternProperties:
- "^phy@[0-9a-f]+$":
- properties:
- reg:
- items:
- - description: TX lane 1
- - description: RX lane 1
- - description: PCS
- - description: TX lane 2
- - description: RX lane 2
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,ipq6018-qmp-usb3-phy
- - qcom,ipq8074-qmp-usb3-phy
- - qcom,qcm2290-qmp-usb3-phy
- - qcom,sc7180-qmp-usb3-phy
- - qcom,sc8180x-qmp-usb3-phy
- - qcom,sdx55-qmp-usb3-uni-phy
- - qcom,sdx65-qmp-usb3-uni-phy
- - qcom,sm6115-qmp-usb3-phy
- - qcom,sm8150-qmp-usb3-uni-phy
- - qcom,sm8250-qmp-usb3-phy
- then:
- patternProperties:
- "^phy@[0-9a-f]+$":
- properties:
- reg:
- items:
- - description: TX
- - description: RX
- - description: PCS
- - description: PCS_MISC
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,msm8996-qmp-usb3-phy
- - qcom,sm8250-qmp-usb3-uni-phy
- - qcom,sm8350-qmp-usb3-uni-phy
- then:
- patternProperties:
- "^phy@[0-9a-f]+$":
- properties:
- reg:
- items:
- - description: TX
- - description: RX
- - description: PCS
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,gcc-sdm845.h>
- usb_2_qmpphy: phy-wrapper@88eb000 {
- compatible = "qcom,sdm845-qmp-usb3-uni-phy";
- reg = <0x088eb000 0x18c>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x088eb000 0x2000>;
-
- clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_SEC_CLKREF_CLK>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "com_aux";
-
- resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
- <&gcc GCC_USB3_PHY_SEC_BCR>;
- reset-names = "phy", "common";
-
- vdda-phy-supply = <&vdda_usb2_ss_1p2>;
- vdda-pll-supply = <&vdda_usb2_ss_core>;
-
- usb_2_ssphy: phy@200 {
- reg = <0x200 0x128>,
- <0x400 0x1fc>,
- <0x800 0x218>,
- <0x600 0x70>;
-
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
-
- #clock-cells = <0>;
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
-
- #phy-cells = <0>;
- };
- };
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
index 16fce1038285..29a417fb7af1 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
@@ -16,20 +16,37 @@ description:
properties:
compatible:
enum:
+ - qcom,ipq6018-qmp-usb3-phy
+ - qcom,ipq8074-qmp-usb3-phy
+ - qcom,msm8996-qmp-usb3-phy
+ - qcom,msm8998-qmp-usb3-phy
+ - qcom,qcm2290-qmp-usb3-phy
+ - qcom,sc7180-qmp-usb3-phy
+ - qcom,sc8180x-qmp-usb3-phy
- qcom,sc8280xp-qmp-usb3-uni-phy
+ - qcom,sdm845-qmp-usb3-phy
+ - qcom,sdm845-qmp-usb3-uni-phy
+ - qcom,sdx55-qmp-usb3-uni-phy
+ - qcom,sdx65-qmp-usb3-uni-phy
+ - qcom,sm6115-qmp-usb3-phy
+ - qcom,sm8150-qmp-usb3-phy
+ - qcom,sm8150-qmp-usb3-uni-phy
+ - qcom,sm8250-qmp-usb3-phy
+ - qcom,sm8250-qmp-usb3-uni-phy
+ - qcom,sm8350-qmp-usb3-phy
+ - qcom,sm8350-qmp-usb3-uni-phy
+ - qcom,sm8450-qmp-usb3-phy
reg:
maxItems: 1
clocks:
- maxItems: 4
+ minItems: 4
+ maxItems: 5
clock-names:
- items:
- - const: aux
- - const: ref
- - const: com_aux
- - const: pipe
+ minItems: 4
+ maxItems: 5
power-domains:
maxItems: 1
@@ -38,9 +55,7 @@ properties:
maxItems: 2
reset-names:
- items:
- - const: phy
- - const: phy_phy
+ maxItems: 2
vdda-phy-supply: true
@@ -60,7 +75,6 @@ required:
- reg
- clocks
- clock-names
- - power-domains
- resets
- reset-names
- vdda-phy-supply
@@ -71,6 +85,179 @@ required:
additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7180-qmp-usb3-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 5
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: com_aux
+ - const: pipe
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: phy
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc8280xp-qmp-usb3-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 4
+ clock-names:
+ items:
+ - const: aux
+ - const: ref
+ - const: com_aux
+ - const: pipe
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: phy
+ - const: phy_phy
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm845-qmp-usb3-uni-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 5
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: com_aux
+ - const: pipe
+ resets:
+ maxItems: 2
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq8074-qmp-usb3-phy
+ - qcom,msm8996-qmp-usb3-phy
+ - qcom,msm8998-qmp-usb3-phy
+ - qcom,sdx55-qmp-usb3-uni-phy
+ - qcom,sdx65-qmp-usb3-uni-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 4
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: pipe
+ resets:
+ maxItems: 2
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8150-qmp-usb3-phy
+ - qcom,sm8150-qmp-usb3-uni-phy
+ - qcom,sm8250-qmp-usb3-uni-phy
+ - qcom,sm8350-qmp-usb3-uni-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 5
+ clock-names:
+ items:
+ - const: aux
+ - const: ref_clk_src
+ - const: ref
+ - const: com_aux
+ - const: pipe
+ resets:
+ maxItems: 2
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8250-qmp-usb3-phy
+ - qcom,sm8350-qmp-usb3-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 4
+ clock-names:
+ items:
+ - const: aux
+ - const: ref_clk_src
+ - const: com_aux
+ - const: pipe
+ resets:
+ maxItems: 2
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcm2290-qmp-usb3-phy
+ - qcom,sm6115-qmp-usb3-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 4
+ clock-names:
+ items:
+ - const: cfg_ahb
+ - const: ref
+ - const: com_aux
+ - const: pipe
+ resets:
+ maxItems: 2
+ reset-names:
+ items:
+ - const: phy_phy
+ - const: phy
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
@@ -100,3 +287,32 @@ examples:
#phy-cells = <0>;
};
+ - |
+ #define GCC_USB3_SEC_CLKREF_CLK 156
+ #define GCC_USB_PHY_CFG_AHB2PHY_CLK 161
+
+ phy@88eb000 {
+ compatible = "qcom,sdm845-qmp-usb3-uni-phy";
+ reg = <0x088eb000 0x18c>;
+
+ clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_SEC_CLKREF_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "com_aux", "pipe";
+
+ resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
+ <&gcc GCC_USB3_PHY_SEC_BCR>;
+ reset-names = "phy", "common";
+
+ vdda-phy-supply = <&vdda_usb2_ss_1p2>;
+ vdda-pll-supply = <&vdda_usb2_ss_core>;
+
+
+ #clock-cells = <0>;
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+
+ #phy-cells = <0>;
+ };
+...
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 01/41] dt-bindings: phy: migrate QMP USB PHY bindings to qcom,sc8280xp-qmp-usb3-uni-phy.yaml
2023-03-24 2:24 ` [PATCH 01/41] dt-bindings: phy: migrate QMP USB PHY bindings to qcom,sc8280xp-qmp-usb3-uni-phy.yaml Dmitry Baryshkov
@ 2023-03-24 7:48 ` Johan Hovold
2023-03-24 12:12 ` Dmitry Baryshkov
2023-03-24 9:43 ` Krzysztof Kozlowski
1 sibling, 1 reply; 50+ messages in thread
From: Johan Hovold @ 2023-03-24 7:48 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, linux-arm-msm, linux-phy, Johan Hovold
On Fri, Mar 24, 2023 at 05:24:34AM +0300, Dmitry Baryshkov wrote:
> Migrate legacy bindings (described in qcom,msm8996-qmp-usb3-phy.yaml)
> to qcom,sc8280xp-qmp-usb3-uni-phy.yaml. This removes a need to declare
> the child PHY node or split resource regions.
This needs to be done more care, rather than just dumping the old mess
we have in the new schema file.
Same comment for the other conversions.
NAK for the whole series for now.
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../phy/qcom,msm8996-qmp-usb3-phy.yaml | 394 ------------------
> .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 236 ++++++++++-
> 2 files changed, 226 insertions(+), 404 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> deleted file mode 100644
> index e81a38281f8c..000000000000
> --- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> +++ /dev/null
> @@ -1,394 +0,0 @@
> -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> -%YAML 1.2
> ----
> -$id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-usb3-phy.yaml#
> -$schema: http://devicetree.org/meta-schemas/core.yaml#
> -
> -title: Qualcomm QMP PHY controller (USB, MSM8996)
> -
> -maintainers:
> - - Vinod Koul <vkoul@kernel.org>
> -
> -description:
> - QMP PHY controller supports physical layer functionality for a number of
> - controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
> -
> - Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see
> - qcom,sc8280xp-qmp-usb3-uni-phy.yaml.
> -
> -properties:
> - compatible:
> - enum:
> - - qcom,ipq6018-qmp-usb3-phy
> - - qcom,ipq8074-qmp-usb3-phy
> - - qcom,msm8996-qmp-usb3-phy
> - - qcom,msm8998-qmp-usb3-phy
> - - qcom,qcm2290-qmp-usb3-phy
> - - qcom,sc7180-qmp-usb3-phy
> - - qcom,sc8180x-qmp-usb3-phy
> - - qcom,sdm845-qmp-usb3-phy
> - - qcom,sdm845-qmp-usb3-uni-phy
> - - qcom,sdx55-qmp-usb3-uni-phy
> - - qcom,sdx65-qmp-usb3-uni-phy
> - - qcom,sm6115-qmp-usb3-phy
> - - qcom,sm8150-qmp-usb3-phy
> - - qcom,sm8150-qmp-usb3-uni-phy
> - - qcom,sm8250-qmp-usb3-phy
> - - qcom,sm8250-qmp-usb3-uni-phy
> - - qcom,sm8350-qmp-usb3-phy
> - - qcom,sm8350-qmp-usb3-uni-phy
> - - qcom,sm8450-qmp-usb3-phy
> -
> - reg:
> - minItems: 1
> - items:
> - - description: serdes
> - - description: DP_COM
> -
> - "#address-cells":
> - enum: [ 1, 2 ]
> -
> - "#size-cells":
> - enum: [ 1, 2 ]
> -
> - ranges: true
> -
> - clocks:
> - minItems: 3
> - maxItems: 4
> -
> - clock-names:
> - minItems: 3
> - maxItems: 4
> -
> - power-domains:
> - maxItems: 1
> -
> - resets:
> - maxItems: 2
> -
> - reset-names:
> - maxItems: 2
> -
> - vdda-phy-supply: true
> -
> - vdda-pll-supply: true
> -
> - vddp-ref-clk-supply: true
> -
> -patternProperties:
> - "^phy@[0-9a-f]+$":
> - type: object
> - description: single PHY-provider child node
> - properties:
> - reg:
> - minItems: 3
> - maxItems: 6
> -
> - clocks:
> - items:
> - - description: PIPE clock
> -
> - clock-names:
> - deprecated: true
> - items:
> - - const: pipe0
> -
> - "#clock-cells":
> - const: 0
> -
> - clock-output-names:
> - maxItems: 1
> -
> - "#phy-cells":
> - const: 0
> -
> - required:
> - - reg
> - - clocks
> - - "#clock-cells"
> - - clock-output-names
> - - "#phy-cells"
> -
> - additionalProperties: false
> -
> -required:
> - - compatible
> - - reg
> - - "#address-cells"
> - - "#size-cells"
> - - ranges
> - - clocks
> - - clock-names
> - - resets
> - - reset-names
> - - vdda-phy-supply
> - - vdda-pll-supply
> -
> -additionalProperties: false
> -
> -allOf:
> - - if:
> - properties:
> - compatible:
> - contains:
> - enum:
> - - qcom,sc7180-qmp-usb3-phy
> - then:
> - properties:
> - clocks:
> - maxItems: 4
> - clock-names:
> - items:
> - - const: aux
> - - const: cfg_ahb
> - - const: ref
> - - const: com_aux
> - resets:
> - maxItems: 1
> - reset-names:
> - items:
> - - const: phy
> -
> - - if:
> - properties:
> - compatible:
> - contains:
> - enum:
> - - qcom,sdm845-qmp-usb3-uni-phy
> - then:
> - properties:
> - clocks:
> - maxItems: 4
> - clock-names:
> - items:
> - - const: aux
> - - const: cfg_ahb
> - - const: ref
> - - const: com_aux
> - resets:
> - maxItems: 2
> - reset-names:
> - items:
> - - const: phy
> - - const: common
> -
> - - if:
> - properties:
> - compatible:
> - contains:
> - enum:
> - - qcom,ipq8074-qmp-usb3-phy
> - - qcom,msm8996-qmp-usb3-phy
> - - qcom,msm8998-qmp-usb3-phy
> - - qcom,sdx55-qmp-usb3-uni-phy
> - - qcom,sdx65-qmp-usb3-uni-phy
> - then:
> - properties:
> - clocks:
> - maxItems: 3
> - clock-names:
> - items:
> - - const: aux
> - - const: cfg_ahb
> - - const: ref
> - resets:
> - maxItems: 2
> - reset-names:
> - items:
> - - const: phy
> - - const: common
> -
> - - if:
> - properties:
> - compatible:
> - contains:
> - enum:
> - - qcom,sm8150-qmp-usb3-phy
> - - qcom,sm8150-qmp-usb3-uni-phy
> - - qcom,sm8250-qmp-usb3-uni-phy
> - - qcom,sm8350-qmp-usb3-uni-phy
> - then:
> - properties:
> - clocks:
> - maxItems: 4
> - clock-names:
> - items:
> - - const: aux
> - - const: ref_clk_src
> - - const: ref
> - - const: com_aux
> - resets:
> - maxItems: 2
> - reset-names:
> - items:
> - - const: phy
> - - const: common
> -
> - - if:
> - properties:
> - compatible:
> - contains:
> - enum:
> - - qcom,sm8250-qmp-usb3-phy
> - - qcom,sm8350-qmp-usb3-phy
> - then:
> - properties:
> - clocks:
> - maxItems: 3
> - clock-names:
> - items:
> - - const: aux
> - - const: ref_clk_src
> - - const: com_aux
> - resets:
> - maxItems: 2
> - reset-names:
> - items:
> - - const: phy
> - - const: common
> -
> - - if:
> - properties:
> - compatible:
> - contains:
> - enum:
> - - qcom,qcm2290-qmp-usb3-phy
> - - qcom,sm6115-qmp-usb3-phy
> - then:
> - properties:
> - clocks:
> - maxItems: 3
> - clock-names:
> - items:
> - - const: cfg_ahb
> - - const: ref
> - - const: com_aux
> - resets:
> - maxItems: 2
> - reset-names:
> - items:
> - - const: phy_phy
> - - const: phy
> -
> - - if:
> - properties:
> - compatible:
> - contains:
> - enum:
> - - qcom,sdm845-qmp-usb3-phy
> - - qcom,sm8150-qmp-usb3-phy
> - - qcom,sm8350-qmp-usb3-phy
> - - qcom,sm8450-qmp-usb3-phy
> - then:
> - patternProperties:
> - "^phy@[0-9a-f]+$":
> - properties:
> - reg:
> - items:
> - - description: TX lane 1
> - - description: RX lane 1
> - - description: PCS
> - - description: TX lane 2
> - - description: RX lane 2
> - - description: PCS_MISC
> -
> - - if:
> - properties:
> - compatible:
> - contains:
> - enum:
> - - qcom,msm8998-qmp-usb3-phy
> - then:
> - patternProperties:
> - "^phy@[0-9a-f]+$":
> - properties:
> - reg:
> - items:
> - - description: TX lane 1
> - - description: RX lane 1
> - - description: PCS
> - - description: TX lane 2
> - - description: RX lane 2
> -
> - - if:
> - properties:
> - compatible:
> - contains:
> - enum:
> - - qcom,ipq6018-qmp-usb3-phy
> - - qcom,ipq8074-qmp-usb3-phy
> - - qcom,qcm2290-qmp-usb3-phy
> - - qcom,sc7180-qmp-usb3-phy
> - - qcom,sc8180x-qmp-usb3-phy
> - - qcom,sdx55-qmp-usb3-uni-phy
> - - qcom,sdx65-qmp-usb3-uni-phy
> - - qcom,sm6115-qmp-usb3-phy
> - - qcom,sm8150-qmp-usb3-uni-phy
> - - qcom,sm8250-qmp-usb3-phy
> - then:
> - patternProperties:
> - "^phy@[0-9a-f]+$":
> - properties:
> - reg:
> - items:
> - - description: TX
> - - description: RX
> - - description: PCS
> - - description: PCS_MISC
> -
> - - if:
> - properties:
> - compatible:
> - contains:
> - enum:
> - - qcom,msm8996-qmp-usb3-phy
> - - qcom,sm8250-qmp-usb3-uni-phy
> - - qcom,sm8350-qmp-usb3-uni-phy
> - then:
> - patternProperties:
> - "^phy@[0-9a-f]+$":
> - properties:
> - reg:
> - items:
> - - description: TX
> - - description: RX
> - - description: PCS
> -
> -examples:
> - - |
> - #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> - usb_2_qmpphy: phy-wrapper@88eb000 {
> - compatible = "qcom,sdm845-qmp-usb3-uni-phy";
> - reg = <0x088eb000 0x18c>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0x0 0x088eb000 0x2000>;
> -
> - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
> - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> - <&gcc GCC_USB3_SEC_CLKREF_CLK>,
> - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
> - clock-names = "aux", "cfg_ahb", "ref", "com_aux";
> -
> - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
> - <&gcc GCC_USB3_PHY_SEC_BCR>;
> - reset-names = "phy", "common";
> -
> - vdda-phy-supply = <&vdda_usb2_ss_1p2>;
> - vdda-pll-supply = <&vdda_usb2_ss_core>;
> -
> - usb_2_ssphy: phy@200 {
> - reg = <0x200 0x128>,
> - <0x400 0x1fc>,
> - <0x800 0x218>,
> - <0x600 0x70>;
> -
> - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
> -
> - #clock-cells = <0>;
> - clock-output-names = "usb3_uni_phy_pipe_clk_src";
> -
> - #phy-cells = <0>;
> - };
> - };
> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> index 16fce1038285..29a417fb7af1 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> @@ -16,20 +16,37 @@ description:
> properties:
> compatible:
> enum:
> + - qcom,ipq6018-qmp-usb3-phy
> + - qcom,ipq8074-qmp-usb3-phy
> + - qcom,msm8996-qmp-usb3-phy
> + - qcom,msm8998-qmp-usb3-phy
> + - qcom,qcm2290-qmp-usb3-phy
> + - qcom,sc7180-qmp-usb3-phy
> + - qcom,sc8180x-qmp-usb3-phy
> - qcom,sc8280xp-qmp-usb3-uni-phy
> + - qcom,sdm845-qmp-usb3-phy
> + - qcom,sdm845-qmp-usb3-uni-phy
> + - qcom,sdx55-qmp-usb3-uni-phy
> + - qcom,sdx65-qmp-usb3-uni-phy
> + - qcom,sm6115-qmp-usb3-phy
> + - qcom,sm8150-qmp-usb3-phy
> + - qcom,sm8150-qmp-usb3-uni-phy
> + - qcom,sm8250-qmp-usb3-phy
> + - qcom,sm8250-qmp-usb3-uni-phy
> + - qcom,sm8350-qmp-usb3-phy
> + - qcom,sm8350-qmp-usb3-uni-phy
> + - qcom,sm8450-qmp-usb3-phy
>
> reg:
> maxItems: 1
>
> clocks:
> - maxItems: 4
> + minItems: 4
> + maxItems: 5
>
> clock-names:
> - items:
> - - const: aux
> - - const: ref
> - - const: com_aux
> - - const: pipe
> + minItems: 4
> + maxItems: 5
>
> power-domains:
> maxItems: 1
> @@ -38,9 +55,7 @@ properties:
> maxItems: 2
>
> reset-names:
> - items:
> - - const: phy
> - - const: phy_phy
> + maxItems: 2
>
> vdda-phy-supply: true
>
> @@ -60,7 +75,6 @@ required:
> - reg
> - clocks
> - clock-names
> - - power-domains
> - resets
> - reset-names
> - vdda-phy-supply
> @@ -71,6 +85,179 @@ required:
>
> additionalProperties: false
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc7180-qmp-usb3-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 5
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: com_aux
> + - const: pipe
> + resets:
> + maxItems: 1
> + reset-names:
> + items:
> + - const: phy
This is just a subset of the next entrie's resets and could possibly be
merged.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc8280xp-qmp-usb3-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 4
> + clock-names:
> + items:
> + - const: aux
> + - const: ref
> + - const: com_aux
> + - const: pipe
> + resets:
> + maxItems: 1
> + reset-names:
> + items:
> + - const: phy
> + - const: phy_phy
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sdm845-qmp-usb3-uni-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 5
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: com_aux
> + - const: pipe
> + resets:
> + maxItems: 2
> + reset-names:
> + items:
> + - const: phy
> + - const: common
Is this really a DP-USB phy? Then it does not belong in this schema,
otherwise the phy name looks wrong.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq8074-qmp-usb3-phy
> + - qcom,msm8996-qmp-usb3-phy
> + - qcom,msm8998-qmp-usb3-phy
> + - qcom,sdx55-qmp-usb3-uni-phy
> + - qcom,sdx65-qmp-usb3-uni-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 4
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: pipe
> + resets:
> + maxItems: 2
> + reset-names:
> + items:
> + - const: phy
> + - const: common
Same here.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sm8150-qmp-usb3-phy
> + - qcom,sm8150-qmp-usb3-uni-phy
> + - qcom,sm8250-qmp-usb3-uni-phy
> + - qcom,sm8350-qmp-usb3-uni-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 5
> + clock-names:
> + items:
> + - const: aux
> + - const: ref_clk_src
As we've discussed before, this clock does not belong in the binding and
this should definitely not be reproduced in the new one.
> + - const: ref
> + - const: com_aux
> + - const: pipe
> + resets:
> + maxItems: 2
> + reset-names:
> + items:
> + - const: phy
> + - const: common
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sm8250-qmp-usb3-phy
> + - qcom,sm8350-qmp-usb3-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 4
> + clock-names:
> + items:
> + - const: aux
> + - const: ref_clk_src
Same here, was this supposed to be ref?
> + - const: com_aux
> + - const: pipe
> + resets:
> + maxItems: 2
> + reset-names:
> + items:
> + - const: phy
> + - const: common
Another combo PHY?
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,qcm2290-qmp-usb3-phy
> + - qcom,sm6115-qmp-usb3-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 4
> + clock-names:
> + items:
> + - const: cfg_ahb
> + - const: ref
> + - const: com_aux
> + - const: pipe
> + resets:
> + maxItems: 2
> + reset-names:
> + items:
> + - const: phy_phy
> + - const: phy
You should be able to get rid of most of the above by looking at the
various platforms and recognising that there are just two sets of
clocks, and probably just two sets of resets where one is a subset of
the other.
As you're introducing a new binding this should all be fixed here and
now rather than do another quick hack.
And if you don't have the time and motivation to fix this up now, then
it's better to leave the old half-broken bindings where they are for
now.
> +
> examples:
> - |
> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
> @@ -100,3 +287,32 @@ examples:
>
> #phy-cells = <0>;
> };
> + - |
> + #define GCC_USB3_SEC_CLKREF_CLK 156
> + #define GCC_USB_PHY_CFG_AHB2PHY_CLK 161
> +
> + phy@88eb000 {
> + compatible = "qcom,sdm845-qmp-usb3-uni-phy";
> + reg = <0x088eb000 0x18c>;
> +
> + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
> + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> + <&gcc GCC_USB3_SEC_CLKREF_CLK>,
> + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
> + clock-names = "aux", "cfg_ahb", "ref", "com_aux", "pipe";
> +
> + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
> + <&gcc GCC_USB3_PHY_SEC_BCR>;
> + reset-names = "phy", "common";
It looks like these resets should have been named 'phy_phy' and 'phy'
(and order reversed).
> +
> + vdda-phy-supply = <&vdda_usb2_ss_1p2>;
> + vdda-pll-supply = <&vdda_usb2_ss_core>;
> +
> +
Stray newline.
> + #clock-cells = <0>;
> + clock-output-names = "usb3_uni_phy_pipe_clk_src";
> +
> + #phy-cells = <0>;
> + };
But what is the purpose of adding this example? It looks essentially the
same as the current one and is thus redundant.
> +...
Johan
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH 01/41] dt-bindings: phy: migrate QMP USB PHY bindings to qcom,sc8280xp-qmp-usb3-uni-phy.yaml
2023-03-24 7:48 ` Johan Hovold
@ 2023-03-24 12:12 ` Dmitry Baryshkov
0 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 12:12 UTC (permalink / raw)
To: Johan Hovold
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, linux-arm-msm, linux-phy, Johan Hovold
On Fri, 24 Mar 2023 at 09:48, Johan Hovold <johan@kernel.org> wrote:
>
> On Fri, Mar 24, 2023 at 05:24:34AM +0300, Dmitry Baryshkov wrote:
> > Migrate legacy bindings (described in qcom,msm8996-qmp-usb3-phy.yaml)
> > to qcom,sc8280xp-qmp-usb3-uni-phy.yaml. This removes a need to declare
> > the child PHY node or split resource regions.
>
> This needs to be done more care, rather than just dumping the old mess
> we have in the new schema file.
Yes, I thought it would be an easier thing. Thank you for your
comments. A (hopefully) good thing is that this also resulted in
several fixes which might be immediately beneficial.
>
> Same comment for the other conversions.
>
> NAK for the whole series for now.
>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > .../phy/qcom,msm8996-qmp-usb3-phy.yaml | 394 ------------------
> > .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 236 ++++++++++-
> > 2 files changed, 226 insertions(+), 404 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> > deleted file mode 100644
> > index e81a38281f8c..000000000000
> > --- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> > +++ /dev/null
> > @@ -1,394 +0,0 @@
> > -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > -%YAML 1.2
> > ----
> > -$id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-usb3-phy.yaml#
> > -$schema: http://devicetree.org/meta-schemas/core.yaml#
> > -
> > -title: Qualcomm QMP PHY controller (USB, MSM8996)
> > -
> > -maintainers:
> > - - Vinod Koul <vkoul@kernel.org>
> > -
> > -description:
> > - QMP PHY controller supports physical layer functionality for a number of
> > - controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
> > -
> > - Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see
> > - qcom,sc8280xp-qmp-usb3-uni-phy.yaml.
> > -
> > -properties:
> > - compatible:
> > - enum:
> > - - qcom,ipq6018-qmp-usb3-phy
> > - - qcom,ipq8074-qmp-usb3-phy
> > - - qcom,msm8996-qmp-usb3-phy
> > - - qcom,msm8998-qmp-usb3-phy
> > - - qcom,qcm2290-qmp-usb3-phy
> > - - qcom,sc7180-qmp-usb3-phy
> > - - qcom,sc8180x-qmp-usb3-phy
> > - - qcom,sdm845-qmp-usb3-phy
> > - - qcom,sdm845-qmp-usb3-uni-phy
> > - - qcom,sdx55-qmp-usb3-uni-phy
> > - - qcom,sdx65-qmp-usb3-uni-phy
> > - - qcom,sm6115-qmp-usb3-phy
> > - - qcom,sm8150-qmp-usb3-phy
> > - - qcom,sm8150-qmp-usb3-uni-phy
> > - - qcom,sm8250-qmp-usb3-phy
> > - - qcom,sm8250-qmp-usb3-uni-phy
> > - - qcom,sm8350-qmp-usb3-phy
> > - - qcom,sm8350-qmp-usb3-uni-phy
> > - - qcom,sm8450-qmp-usb3-phy
> > -
> > - reg:
> > - minItems: 1
> > - items:
> > - - description: serdes
> > - - description: DP_COM
> > -
> > - "#address-cells":
> > - enum: [ 1, 2 ]
> > -
> > - "#size-cells":
> > - enum: [ 1, 2 ]
> > -
> > - ranges: true
> > -
> > - clocks:
> > - minItems: 3
> > - maxItems: 4
> > -
> > - clock-names:
> > - minItems: 3
> > - maxItems: 4
> > -
> > - power-domains:
> > - maxItems: 1
> > -
> > - resets:
> > - maxItems: 2
> > -
> > - reset-names:
> > - maxItems: 2
> > -
> > - vdda-phy-supply: true
> > -
> > - vdda-pll-supply: true
> > -
> > - vddp-ref-clk-supply: true
> > -
> > -patternProperties:
> > - "^phy@[0-9a-f]+$":
> > - type: object
> > - description: single PHY-provider child node
> > - properties:
> > - reg:
> > - minItems: 3
> > - maxItems: 6
> > -
> > - clocks:
> > - items:
> > - - description: PIPE clock
> > -
> > - clock-names:
> > - deprecated: true
> > - items:
> > - - const: pipe0
> > -
> > - "#clock-cells":
> > - const: 0
> > -
> > - clock-output-names:
> > - maxItems: 1
> > -
> > - "#phy-cells":
> > - const: 0
> > -
> > - required:
> > - - reg
> > - - clocks
> > - - "#clock-cells"
> > - - clock-output-names
> > - - "#phy-cells"
> > -
> > - additionalProperties: false
> > -
> > -required:
> > - - compatible
> > - - reg
> > - - "#address-cells"
> > - - "#size-cells"
> > - - ranges
> > - - clocks
> > - - clock-names
> > - - resets
> > - - reset-names
> > - - vdda-phy-supply
> > - - vdda-pll-supply
> > -
> > -additionalProperties: false
> > -
> > -allOf:
> > - - if:
> > - properties:
> > - compatible:
> > - contains:
> > - enum:
> > - - qcom,sc7180-qmp-usb3-phy
> > - then:
> > - properties:
> > - clocks:
> > - maxItems: 4
> > - clock-names:
> > - items:
> > - - const: aux
> > - - const: cfg_ahb
> > - - const: ref
> > - - const: com_aux
> > - resets:
> > - maxItems: 1
> > - reset-names:
> > - items:
> > - - const: phy
> > -
> > - - if:
> > - properties:
> > - compatible:
> > - contains:
> > - enum:
> > - - qcom,sdm845-qmp-usb3-uni-phy
> > - then:
> > - properties:
> > - clocks:
> > - maxItems: 4
> > - clock-names:
> > - items:
> > - - const: aux
> > - - const: cfg_ahb
> > - - const: ref
> > - - const: com_aux
> > - resets:
> > - maxItems: 2
> > - reset-names:
> > - items:
> > - - const: phy
> > - - const: common
> > -
> > - - if:
> > - properties:
> > - compatible:
> > - contains:
> > - enum:
> > - - qcom,ipq8074-qmp-usb3-phy
> > - - qcom,msm8996-qmp-usb3-phy
> > - - qcom,msm8998-qmp-usb3-phy
> > - - qcom,sdx55-qmp-usb3-uni-phy
> > - - qcom,sdx65-qmp-usb3-uni-phy
> > - then:
> > - properties:
> > - clocks:
> > - maxItems: 3
> > - clock-names:
> > - items:
> > - - const: aux
> > - - const: cfg_ahb
> > - - const: ref
> > - resets:
> > - maxItems: 2
> > - reset-names:
> > - items:
> > - - const: phy
> > - - const: common
> > -
> > - - if:
> > - properties:
> > - compatible:
> > - contains:
> > - enum:
> > - - qcom,sm8150-qmp-usb3-phy
> > - - qcom,sm8150-qmp-usb3-uni-phy
> > - - qcom,sm8250-qmp-usb3-uni-phy
> > - - qcom,sm8350-qmp-usb3-uni-phy
> > - then:
> > - properties:
> > - clocks:
> > - maxItems: 4
> > - clock-names:
> > - items:
> > - - const: aux
> > - - const: ref_clk_src
> > - - const: ref
> > - - const: com_aux
> > - resets:
> > - maxItems: 2
> > - reset-names:
> > - items:
> > - - const: phy
> > - - const: common
> > -
> > - - if:
> > - properties:
> > - compatible:
> > - contains:
> > - enum:
> > - - qcom,sm8250-qmp-usb3-phy
> > - - qcom,sm8350-qmp-usb3-phy
> > - then:
> > - properties:
> > - clocks:
> > - maxItems: 3
> > - clock-names:
> > - items:
> > - - const: aux
> > - - const: ref_clk_src
> > - - const: com_aux
> > - resets:
> > - maxItems: 2
> > - reset-names:
> > - items:
> > - - const: phy
> > - - const: common
> > -
> > - - if:
> > - properties:
> > - compatible:
> > - contains:
> > - enum:
> > - - qcom,qcm2290-qmp-usb3-phy
> > - - qcom,sm6115-qmp-usb3-phy
> > - then:
> > - properties:
> > - clocks:
> > - maxItems: 3
> > - clock-names:
> > - items:
> > - - const: cfg_ahb
> > - - const: ref
> > - - const: com_aux
> > - resets:
> > - maxItems: 2
> > - reset-names:
> > - items:
> > - - const: phy_phy
> > - - const: phy
> > -
> > - - if:
> > - properties:
> > - compatible:
> > - contains:
> > - enum:
> > - - qcom,sdm845-qmp-usb3-phy
> > - - qcom,sm8150-qmp-usb3-phy
> > - - qcom,sm8350-qmp-usb3-phy
> > - - qcom,sm8450-qmp-usb3-phy
> > - then:
> > - patternProperties:
> > - "^phy@[0-9a-f]+$":
> > - properties:
> > - reg:
> > - items:
> > - - description: TX lane 1
> > - - description: RX lane 1
> > - - description: PCS
> > - - description: TX lane 2
> > - - description: RX lane 2
> > - - description: PCS_MISC
> > -
> > - - if:
> > - properties:
> > - compatible:
> > - contains:
> > - enum:
> > - - qcom,msm8998-qmp-usb3-phy
> > - then:
> > - patternProperties:
> > - "^phy@[0-9a-f]+$":
> > - properties:
> > - reg:
> > - items:
> > - - description: TX lane 1
> > - - description: RX lane 1
> > - - description: PCS
> > - - description: TX lane 2
> > - - description: RX lane 2
> > -
> > - - if:
> > - properties:
> > - compatible:
> > - contains:
> > - enum:
> > - - qcom,ipq6018-qmp-usb3-phy
> > - - qcom,ipq8074-qmp-usb3-phy
> > - - qcom,qcm2290-qmp-usb3-phy
> > - - qcom,sc7180-qmp-usb3-phy
> > - - qcom,sc8180x-qmp-usb3-phy
> > - - qcom,sdx55-qmp-usb3-uni-phy
> > - - qcom,sdx65-qmp-usb3-uni-phy
> > - - qcom,sm6115-qmp-usb3-phy
> > - - qcom,sm8150-qmp-usb3-uni-phy
> > - - qcom,sm8250-qmp-usb3-phy
> > - then:
> > - patternProperties:
> > - "^phy@[0-9a-f]+$":
> > - properties:
> > - reg:
> > - items:
> > - - description: TX
> > - - description: RX
> > - - description: PCS
> > - - description: PCS_MISC
> > -
> > - - if:
> > - properties:
> > - compatible:
> > - contains:
> > - enum:
> > - - qcom,msm8996-qmp-usb3-phy
> > - - qcom,sm8250-qmp-usb3-uni-phy
> > - - qcom,sm8350-qmp-usb3-uni-phy
> > - then:
> > - patternProperties:
> > - "^phy@[0-9a-f]+$":
> > - properties:
> > - reg:
> > - items:
> > - - description: TX
> > - - description: RX
> > - - description: PCS
> > -
> > -examples:
> > - - |
> > - #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> > - usb_2_qmpphy: phy-wrapper@88eb000 {
> > - compatible = "qcom,sdm845-qmp-usb3-uni-phy";
> > - reg = <0x088eb000 0x18c>;
> > - #address-cells = <1>;
> > - #size-cells = <1>;
> > - ranges = <0x0 0x088eb000 0x2000>;
> > -
> > - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
> > - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> > - <&gcc GCC_USB3_SEC_CLKREF_CLK>,
> > - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
> > - clock-names = "aux", "cfg_ahb", "ref", "com_aux";
> > -
> > - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
> > - <&gcc GCC_USB3_PHY_SEC_BCR>;
> > - reset-names = "phy", "common";
> > -
> > - vdda-phy-supply = <&vdda_usb2_ss_1p2>;
> > - vdda-pll-supply = <&vdda_usb2_ss_core>;
> > -
> > - usb_2_ssphy: phy@200 {
> > - reg = <0x200 0x128>,
> > - <0x400 0x1fc>,
> > - <0x800 0x218>,
> > - <0x600 0x70>;
> > -
> > - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
> > -
> > - #clock-cells = <0>;
> > - clock-output-names = "usb3_uni_phy_pipe_clk_src";
> > -
> > - #phy-cells = <0>;
> > - };
> > - };
> > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> > index 16fce1038285..29a417fb7af1 100644
> > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> > @@ -16,20 +16,37 @@ description:
> > properties:
> > compatible:
> > enum:
> > + - qcom,ipq6018-qmp-usb3-phy
> > + - qcom,ipq8074-qmp-usb3-phy
> > + - qcom,msm8996-qmp-usb3-phy
> > + - qcom,msm8998-qmp-usb3-phy
> > + - qcom,qcm2290-qmp-usb3-phy
> > + - qcom,sc7180-qmp-usb3-phy
> > + - qcom,sc8180x-qmp-usb3-phy
> > - qcom,sc8280xp-qmp-usb3-uni-phy
> > + - qcom,sdm845-qmp-usb3-phy
> > + - qcom,sdm845-qmp-usb3-uni-phy
> > + - qcom,sdx55-qmp-usb3-uni-phy
> > + - qcom,sdx65-qmp-usb3-uni-phy
> > + - qcom,sm6115-qmp-usb3-phy
> > + - qcom,sm8150-qmp-usb3-phy
> > + - qcom,sm8150-qmp-usb3-uni-phy
> > + - qcom,sm8250-qmp-usb3-phy
> > + - qcom,sm8250-qmp-usb3-uni-phy
> > + - qcom,sm8350-qmp-usb3-phy
> > + - qcom,sm8350-qmp-usb3-uni-phy
> > + - qcom,sm8450-qmp-usb3-phy
> >
> > reg:
> > maxItems: 1
> >
> > clocks:
> > - maxItems: 4
> > + minItems: 4
> > + maxItems: 5
> >
> > clock-names:
> > - items:
> > - - const: aux
> > - - const: ref
> > - - const: com_aux
> > - - const: pipe
> > + minItems: 4
> > + maxItems: 5
> >
> > power-domains:
> > maxItems: 1
> > @@ -38,9 +55,7 @@ properties:
> > maxItems: 2
> >
> > reset-names:
> > - items:
> > - - const: phy
> > - - const: phy_phy
> > + maxItems: 2
> >
> > vdda-phy-supply: true
> >
> > @@ -60,7 +75,6 @@ required:
> > - reg
> > - clocks
> > - clock-names
> > - - power-domains
> > - resets
> > - reset-names
> > - vdda-phy-supply
> > @@ -71,6 +85,179 @@ required:
> >
> > additionalProperties: false
> >
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,sc7180-qmp-usb3-phy
> > + then:
> > + properties:
> > + clocks:
> > + maxItems: 5
> > + clock-names:
> > + items:
> > + - const: aux
> > + - const: cfg_ahb
> > + - const: ref
> > + - const: com_aux
> > + - const: pipe
> > + resets:
> > + maxItems: 1
> > + reset-names:
> > + items:
> > + - const: phy
>
> This is just a subset of the next entrie's resets and could possibly be
> merged.
I see.
>
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,sc8280xp-qmp-usb3-phy
> > + then:
> > + properties:
> > + clocks:
> > + maxItems: 4
> > + clock-names:
> > + items:
> > + - const: aux
> > + - const: ref
> > + - const: com_aux
> > + - const: pipe
> > + resets:
> > + maxItems: 1
> > + reset-names:
> > + items:
> > + - const: phy
> > + - const: phy_phy
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,sdm845-qmp-usb3-uni-phy
> > + then:
> > + properties:
> > + clocks:
> > + maxItems: 5
> > + clock-names:
> > + items:
> > + - const: aux
> > + - const: cfg_ahb
> > + - const: ref
> > + - const: com_aux
> > + - const: pipe
> > + resets:
> > + maxItems: 2
> > + reset-names:
> > + items:
> > + - const: phy
> > + - const: common
>
> Is this really a DP-USB phy? Then it does not belong in this schema,
> otherwise the phy name looks wrong.
No, this is really a uni (USB-only) PHY. It has two resets (at least
two resets are declared in the dts):
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
If it was a new code, it would have been possible to use "phy_phy',
"phy". However as we already have code in place, changing the resets
would be a bit of a pain.
>
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,ipq8074-qmp-usb3-phy
> > + - qcom,msm8996-qmp-usb3-phy
> > + - qcom,msm8998-qmp-usb3-phy
> > + - qcom,sdx55-qmp-usb3-uni-phy
> > + - qcom,sdx65-qmp-usb3-uni-phy
> > + then:
> > + properties:
> > + clocks:
> > + maxItems: 4
> > + clock-names:
> > + items:
> > + - const: aux
> > + - const: cfg_ahb
> > + - const: ref
> > + - const: pipe
> > + resets:
> > + maxItems: 2
> > + reset-names:
> > + items:
> > + - const: phy
> > + - const: common
>
> Same here.
Same as above
>
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,sm8150-qmp-usb3-phy
> > + - qcom,sm8150-qmp-usb3-uni-phy
> > + - qcom,sm8250-qmp-usb3-uni-phy
> > + - qcom,sm8350-qmp-usb3-uni-phy
> > + then:
> > + properties:
> > + clocks:
> > + maxItems: 5
> > + clock-names:
> > + items:
> > + - const: aux
> > + - const: ref_clk_src
>
> As we've discussed before, this clock does not belong in the binding and
> this should definitely not be reproduced in the new one.
Ack, thanks.
>
> > + - const: ref
> > + - const: com_aux
> > + - const: pipe
> > + resets:
> > + maxItems: 2
> > + reset-names:
> > + items:
> > + - const: phy
> > + - const: common
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,sm8250-qmp-usb3-phy
> > + - qcom,sm8350-qmp-usb3-phy
> > + then:
> > + properties:
> > + clocks:
> > + maxItems: 4
> > + clock-names:
> > + items:
> > + - const: aux
> > + - const: ref_clk_src
>
> Same here, was this supposed to be ref?
Hmm, no. It seems we just have to use SEC_CLKREF_EN here for refclk:
* GCC_USB3_SEC_CLKREF_EN provides ref_clk for both
* USB instances.
*/
<&clock_gcc GCC_USB3_SEC_CLKREF_EN>;
>
> > + - const: com_aux
> > + - const: pipe
> > + resets:
> > + maxItems: 2
> > + reset-names:
> > + items:
> > + - const: phy
> > + - const: common
>
> Another combo PHY?
Yes, even historical one. Let's drop them completely.
We also have one last combo PHY that was not converted from being
USB-only: qcom,sm8150-qmp-usb3-phy. I will check if we can do a quick
shift now.
>
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,qcm2290-qmp-usb3-phy
> > + - qcom,sm6115-qmp-usb3-phy
> > + then:
> > + properties:
> > + clocks:
> > + maxItems: 4
> > + clock-names:
> > + items:
> > + - const: cfg_ahb
> > + - const: ref
> > + - const: com_aux
> > + - const: pipe
> > + resets:
> > + maxItems: 2
> > + reset-names:
> > + items:
> > + - const: phy_phy
> > + - const: phy
>
> You should be able to get rid of most of the above by looking at the
> various platforms and recognising that there are just two sets of
> clocks, and probably just two sets of resets where one is a subset of
> the other.
I will take a look at optimizing these entries, thank you.
>
> As you're introducing a new binding this should all be fixed here and
> now rather than do another quick hack.
>
> And if you don't have the time and motivation to fix this up now, then
> it's better to leave the old half-broken bindings where they are for
> now.
I was hesitant to do this conversion for quite some time, but then I
somehow became tired of pointing to newer bindings. Keeping both old
and new ones is confusing.
>
> > +
> > examples:
> > - |
> > #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
> > @@ -100,3 +287,32 @@ examples:
> >
> > #phy-cells = <0>;
> > };
> > + - |
> > + #define GCC_USB3_SEC_CLKREF_CLK 156
> > + #define GCC_USB_PHY_CFG_AHB2PHY_CLK 161
> > +
> > + phy@88eb000 {
> > + compatible = "qcom,sdm845-qmp-usb3-uni-phy";
> > + reg = <0x088eb000 0x18c>;
> > +
> > + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
> > + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> > + <&gcc GCC_USB3_SEC_CLKREF_CLK>,
> > + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
> > + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
> > + clock-names = "aux", "cfg_ahb", "ref", "com_aux", "pipe";
> > +
> > + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
> > + <&gcc GCC_USB3_PHY_SEC_BCR>;
> > + reset-names = "phy", "common";
>
> It looks like these resets should have been named 'phy_phy' and 'phy'
> (and order reversed).
As I wrote above, renaming resets doesn't sound like an easy way to
go. But if you, Krzysztof or Rob insist, I will take a look.
> > +
> > + vdda-phy-supply = <&vdda_usb2_ss_1p2>;
> > + vdda-pll-supply = <&vdda_usb2_ss_core>;
> > +
> > +
>
> Stray newline.
>
> > + #clock-cells = <0>;
> > + clock-output-names = "usb3_uni_phy_pipe_clk_src";
> > +
> > + #phy-cells = <0>;
> > + };
>
> But what is the purpose of adding this example? It looks essentially the
> same as the current one and is thus redundant.
It was mostly to ensure at dt_bindings_check time that the bindings
are converted correctly. I can drop added examples.
--
With best wishes
Dmitry
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 01/41] dt-bindings: phy: migrate QMP USB PHY bindings to qcom,sc8280xp-qmp-usb3-uni-phy.yaml
2023-03-24 2:24 ` [PATCH 01/41] dt-bindings: phy: migrate QMP USB PHY bindings to qcom,sc8280xp-qmp-usb3-uni-phy.yaml Dmitry Baryshkov
2023-03-24 7:48 ` Johan Hovold
@ 2023-03-24 9:43 ` Krzysztof Kozlowski
2023-03-24 11:45 ` Dmitry Baryshkov
1 sibling, 1 reply; 50+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-24 9:43 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
On 24/03/2023 03:24, Dmitry Baryshkov wrote:
> Migrate legacy bindings (described in qcom,msm8996-qmp-usb3-phy.yaml)
> to qcom,sc8280xp-qmp-usb3-uni-phy.yaml. This removes a need to declare
> the child PHY node or split resource regions.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../phy/qcom,msm8996-qmp-usb3-phy.yaml | 394 ------------------
> .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 236 ++++++++++-
> 2 files changed, 226 insertions(+), 404 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
>
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.
Since you skipped DT list, there will be no tests run, thus this is
unfortunately a NAK.
Best regards,
Krzysztof
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 01/41] dt-bindings: phy: migrate QMP USB PHY bindings to qcom,sc8280xp-qmp-usb3-uni-phy.yaml
2023-03-24 9:43 ` Krzysztof Kozlowski
@ 2023-03-24 11:45 ` Dmitry Baryshkov
0 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 11:45 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, linux-arm-msm, linux-phy, Johan Hovold
On Fri, 24 Mar 2023 at 11:43, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 24/03/2023 03:24, Dmitry Baryshkov wrote:
> > Migrate legacy bindings (described in qcom,msm8996-qmp-usb3-phy.yaml)
> > to qcom,sc8280xp-qmp-usb3-uni-phy.yaml. This removes a need to declare
> > the child PHY node or split resource regions.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > .../phy/qcom,msm8996-qmp-usb3-phy.yaml | 394 ------------------
> > .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 236 ++++++++++-
> > 2 files changed, 226 insertions(+), 404 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
> >
>
> Please use scripts/get_maintainers.pl to get a list of necessary people
> and lists to CC. It might happen, that command when run on an older
> kernel, gives you outdated entries. Therefore please be sure you base
> your patches on recent Linux kernel.
>
> Since you skipped DT list, there will be no tests run, thus this is
> unfortunately a NAK.
Yeah, I should enforce a ban on me sending patches after midnight.
--
With best wishes
Dmitry
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 02/41] dt-bindings: phy: migrate combo QMP PHY bindings to qcom,sc8280xp-qmp-usb43dp-phy.yaml
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 01/41] dt-bindings: phy: migrate QMP USB PHY bindings to qcom,sc8280xp-qmp-usb3-uni-phy.yaml Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 7:54 ` Johan Hovold
2023-03-24 2:24 ` [PATCH 03/41] dt-bindings: phy: migrate QMP UFS PHY bindings to qcom,sc8280xp-qmp-ufs-phy.yaml Dmitry Baryshkov
` (38 subsequent siblings)
40 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Migrate legacy bindings (described in qcom,sc7180-qmp-usb3-dp-phy.yaml)
to qcom,sc8280xp-qmp-usb43dp-phy.yaml. This removes a need to declare
the child PHY node or split resource regions.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qcom,sc7180-qmp-usb3-dp-phy.yaml | 276 ------------------
.../phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 124 +++++++-
2 files changed, 111 insertions(+), 289 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml
deleted file mode 100644
index 0ef2c9b9d466..000000000000
--- a/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml
+++ /dev/null
@@ -1,276 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm QMP USB3 DP PHY controller (SC7180)
-
-description:
- The QMP PHY controller supports physical layer functionality for a number of
- controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
-
- Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see
- qcom,sc8280xp-qmp-usb43dp-phy.yaml.
-
-maintainers:
- - Wesley Cheng <quic_wcheng@quicinc.com>
-
-properties:
- compatible:
- oneOf:
- - enum:
- - qcom,sc7180-qmp-usb3-dp-phy
- - qcom,sc8180x-qmp-usb3-dp-phy
- - qcom,sdm845-qmp-usb3-dp-phy
- - qcom,sm8250-qmp-usb3-dp-phy
- - items:
- - enum:
- - qcom,sc7280-qmp-usb3-dp-phy
- - const: qcom,sm8250-qmp-usb3-dp-phy
-
- reg:
- items:
- - description: Address and length of PHY's USB serdes block.
- - description: Address and length of the DP_COM control block.
- - description: Address and length of PHY's DP serdes block.
-
- reg-names:
- items:
- - const: usb
- - const: dp_com
- - const: dp
-
- "#address-cells":
- enum: [ 1, 2 ]
-
- "#size-cells":
- enum: [ 1, 2 ]
-
- ranges: true
-
- clocks:
- minItems: 3
- maxItems: 4
-
- clock-names:
- minItems: 3
- maxItems: 4
-
- power-domains:
- maxItems: 1
-
- resets:
- items:
- - description: reset of phy block.
- - description: phy common block reset.
-
- reset-names:
- items:
- - const: phy
- - const: common
-
- vdda-phy-supply:
- description:
- Phandle to a regulator supply to PHY core block.
-
- vdda-pll-supply:
- description:
- Phandle to 1.8V regulator supply to PHY refclk pll block.
-
- vddp-ref-clk-supply:
- description:
- Phandle to a regulator supply to any specific refclk pll block.
-
-# Required nodes:
-patternProperties:
- "^usb3-phy@[0-9a-f]+$":
- type: object
- additionalProperties: false
- description:
- The USB3 PHY.
-
- properties:
- reg:
- items:
- - description: Address and length of TX.
- - description: Address and length of RX.
- - description: Address and length of PCS.
- - description: Address and length of TX2.
- - description: Address and length of RX2.
- - description: Address and length of pcs_misc.
-
- clocks:
- items:
- - description: pipe clock
-
- clock-names:
- deprecated: true
- items:
- - const: pipe0
-
- clock-output-names:
- items:
- - const: usb3_phy_pipe_clk_src
-
- '#clock-cells':
- const: 0
-
- '#phy-cells':
- const: 0
-
- required:
- - reg
- - clocks
- - '#clock-cells'
- - '#phy-cells'
-
- "^dp-phy@[0-9a-f]+$":
- type: object
- additionalProperties: false
- description:
- The DP PHY.
-
- properties:
- reg:
- items:
- - description: Address and length of TX.
- - description: Address and length of RX.
- - description: Address and length of PCS.
- - description: Address and length of TX2.
- - description: Address and length of RX2.
-
- '#clock-cells':
- const: 1
-
- '#phy-cells':
- const: 0
-
- required:
- - reg
- - '#clock-cells'
- - '#phy-cells'
-
-required:
- - compatible
- - reg
- - "#address-cells"
- - "#size-cells"
- - ranges
- - clocks
- - clock-names
- - resets
- - reset-names
- - vdda-phy-supply
- - vdda-pll-supply
-
-allOf:
- - if:
- properties:
- compatible:
- enum:
- - qcom,sc7180-qmp-usb3-dp-phy
- - qcom,sdm845-qmp-usb3-dp-phy
- then:
- properties:
- clocks:
- items:
- - description: Phy aux clock
- - description: Phy config clock
- - description: 19.2 MHz ref clk
- - description: Phy common block aux clock
- clock-names:
- items:
- - const: aux
- - const: cfg_ahb
- - const: ref
- - const: com_aux
-
- - if:
- properties:
- compatible:
- enum:
- - qcom,sc8180x-qmp-usb3-dp-phy
- then:
- properties:
- clocks:
- items:
- - description: Phy aux clock
- - description: 19.2 MHz ref clk
- - description: Phy common block aux clock
- clock-names:
- items:
- - const: aux
- - const: ref
- - const: com_aux
-
- - if:
- properties:
- compatible:
- enum:
- - qcom,sm8250-qmp-usb3-dp-phy
- then:
- properties:
- clocks:
- items:
- - description: Phy aux clock
- - description: Board XO source
- - description: Phy common block aux clock
- clock-names:
- items:
- - const: aux
- - const: ref_clk_src
- - const: com_aux
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,gcc-sdm845.h>
- usb_1_qmpphy: phy-wrapper@88e9000 {
- compatible = "qcom,sdm845-qmp-usb3-dp-phy";
- reg = <0x088e9000 0x18c>,
- <0x088e8000 0x10>,
- <0x088ea000 0x40>;
- reg-names = "usb", "dp_com", "dp";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x088e9000 0x2000>;
-
- clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "com_aux";
-
- resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
- <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
- reset-names = "phy", "common";
-
- vdda-phy-supply = <&vdda_usb2_ss_1p2>;
- vdda-pll-supply = <&vdda_usb2_ss_core>;
-
- usb3-phy@200 {
- reg = <0x200 0x128>,
- <0x400 0x200>,
- <0xc00 0x218>,
- <0x600 0x128>,
- <0x800 0x200>,
- <0xa00 0x100>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-output-names = "usb3_phy_pipe_clk_src";
- };
-
- dp-phy@88ea200 {
- reg = <0xa200 0x200>,
- <0xa400 0x200>,
- <0xaa00 0x200>,
- <0xa600 0x200>,
- <0xa800 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
- };
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
index 3cd5fc3e8fab..484f321aefce 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
@@ -15,25 +15,32 @@ description:
properties:
compatible:
- enum:
- - qcom,sc8280xp-qmp-usb43dp-phy
- - qcom,sm6350-qmp-usb3-dp-phy
- - qcom,sm8350-qmp-usb3-dp-phy
- - qcom,sm8450-qmp-usb3-dp-phy
- - qcom,sm8550-qmp-usb3-dp-phy
+ oneOf:
+ - enum:
+ - qcom,sc7180-qmp-usb3-dp-phy
+ - qcom,sc8180x-qmp-usb3-dp-phy
+ - qcom,sc8280xp-qmp-usb43dp-phy
+ - qcom,sdm845-qmp-usb3-dp-phy
+ - qcom,sm6350-qmp-usb3-dp-phy
+ - qcom,sm8250-qmp-usb3-dp-phy
+ - qcom,sm8350-qmp-usb3-dp-phy
+ - qcom,sm8450-qmp-usb3-dp-phy
+ - qcom,sm8550-qmp-usb3-dp-phy
+ - items:
+ - enum:
+ - qcom,sc7280-qmp-usb3-dp-phy
+ - const: qcom,sm8250-qmp-usb3-dp-phy
reg:
maxItems: 1
clocks:
- maxItems: 4
+ minItems: 3
+ maxItems: 5
clock-names:
- items:
- - const: aux
- - const: ref
- - const: com_aux
- - const: usb3_pipe
+ minItems: 3
+ maxItems: 5
power-domains:
maxItems: 1
@@ -50,6 +57,8 @@ properties:
vdda-pll-supply: true
+ vddp-ref-clk-supply: true
+
"#clock-cells":
const: 1
description:
@@ -65,7 +74,6 @@ required:
- reg
- clocks
- clock-names
- - power-domains
- resets
- reset-names
- vdda-phy-supply
@@ -73,6 +81,71 @@ required:
- "#clock-cells"
- "#phy-cells"
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sc7180-qmp-usb3-dp-phy
+ - qcom,sdm845-qmp-usb3-dp-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock
+ - description: Phy config clock
+ - description: 19.2 MHz ref clk
+ - description: Phy common block aux clock
+ - description: USB3 PIPE clock
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: com_aux
+ - const: usb3_pipe
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sc8180x-qmp-usb3-dp-phy
+ - qcom,sc8280xp-qmp-usb3-dp-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock
+ - description: 19.2 MHz ref clk
+ - description: Phy common block aux clock
+ - description: USB3 PIPE clock
+ clock-names:
+ items:
+ - const: aux
+ - const: ref
+ - const: com_aux
+ - const: usb3_pipe
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sm8250-qmp-usb3-dp-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock
+ - description: Board XO source
+ - description: Phy common block aux clock
+ - description: USB3 PIPE clock
+ clock-names:
+ items:
+ - const: aux
+ - const: ref_clk_src
+ - const: com_aux
+ - const: usb3_pipe
+
additionalProperties: false
examples:
@@ -101,3 +174,28 @@ examples:
#clock-cells = <1>;
#phy-cells = <1>;
};
+ - |
+ #define GCC_USB3_PRIM_CLKREF_CLK 151
+ #define GCC_USB_PHY_CFG_AHB2PHY_CLK 161
+
+ phy@88e8000 {
+ compatible = "qcom,sdm845-qmp-usb3-dp-phy";
+ reg = <0x088e8000 0x3000>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "com_aux", "usb3_pipe";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+ reset-names = "phy", "common";
+
+ vdda-phy-supply = <&vdda_usb2_ss_1p2>;
+ vdda-pll-supply = <&vdda_usb2_ss_core>;
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+ };
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 02/41] dt-bindings: phy: migrate combo QMP PHY bindings to qcom,sc8280xp-qmp-usb43dp-phy.yaml
2023-03-24 2:24 ` [PATCH 02/41] dt-bindings: phy: migrate combo QMP PHY bindings to qcom,sc8280xp-qmp-usb43dp-phy.yaml Dmitry Baryshkov
@ 2023-03-24 7:54 ` Johan Hovold
0 siblings, 0 replies; 50+ messages in thread
From: Johan Hovold @ 2023-03-24 7:54 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, linux-arm-msm, linux-phy, Johan Hovold
On Fri, Mar 24, 2023 at 05:24:35AM +0300, Dmitry Baryshkov wrote:
> Migrate legacy bindings (described in qcom,sc7180-qmp-usb3-dp-phy.yaml)
> to qcom,sc8280xp-qmp-usb43dp-phy.yaml. This removes a need to declare
> the child PHY node or split resource regions.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../phy/qcom,sc7180-qmp-usb3-dp-phy.yaml | 276 ------------------
> .../phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 124 +++++++-
> 2 files changed, 111 insertions(+), 289 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml
> deleted file mode 100644
> index 0ef2c9b9d466..000000000000
> --- a/Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml
> +++ /dev/null
> @@ -1,276 +0,0 @@
> -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> -
> -%YAML 1.2
> ----
> -$id: http://devicetree.org/schemas/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml#
> -$schema: http://devicetree.org/meta-schemas/core.yaml#
> -
> -title: Qualcomm QMP USB3 DP PHY controller (SC7180)
> -
> -description:
> - The QMP PHY controller supports physical layer functionality for a number of
> - controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
> -
> - Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see
> - qcom,sc8280xp-qmp-usb43dp-phy.yaml.
> -
> -maintainers:
> - - Wesley Cheng <quic_wcheng@quicinc.com>
> -
> -properties:
> - compatible:
> - oneOf:
> - - enum:
> - - qcom,sc7180-qmp-usb3-dp-phy
> - - qcom,sc8180x-qmp-usb3-dp-phy
> - - qcom,sdm845-qmp-usb3-dp-phy
> - - qcom,sm8250-qmp-usb3-dp-phy
> - - items:
> - - enum:
> - - qcom,sc7280-qmp-usb3-dp-phy
> - - const: qcom,sm8250-qmp-usb3-dp-phy
> -
> - reg:
> - items:
> - - description: Address and length of PHY's USB serdes block.
> - - description: Address and length of the DP_COM control block.
> - - description: Address and length of PHY's DP serdes block.
> -
> - reg-names:
> - items:
> - - const: usb
> - - const: dp_com
> - - const: dp
> -
> - "#address-cells":
> - enum: [ 1, 2 ]
> -
> - "#size-cells":
> - enum: [ 1, 2 ]
> -
> - ranges: true
> -
> - clocks:
> - minItems: 3
> - maxItems: 4
> -
> - clock-names:
> - minItems: 3
> - maxItems: 4
> -
> - power-domains:
> - maxItems: 1
> -
> - resets:
> - items:
> - - description: reset of phy block.
> - - description: phy common block reset.
> -
> - reset-names:
> - items:
> - - const: phy
> - - const: common
> -
> - vdda-phy-supply:
> - description:
> - Phandle to a regulator supply to PHY core block.
> -
> - vdda-pll-supply:
> - description:
> - Phandle to 1.8V regulator supply to PHY refclk pll block.
> -
> - vddp-ref-clk-supply:
> - description:
> - Phandle to a regulator supply to any specific refclk pll block.
> -
> -# Required nodes:
> -patternProperties:
> - "^usb3-phy@[0-9a-f]+$":
> - type: object
> - additionalProperties: false
> - description:
> - The USB3 PHY.
> -
> - properties:
> - reg:
> - items:
> - - description: Address and length of TX.
> - - description: Address and length of RX.
> - - description: Address and length of PCS.
> - - description: Address and length of TX2.
> - - description: Address and length of RX2.
> - - description: Address and length of pcs_misc.
> -
> - clocks:
> - items:
> - - description: pipe clock
> -
> - clock-names:
> - deprecated: true
> - items:
> - - const: pipe0
> -
> - clock-output-names:
> - items:
> - - const: usb3_phy_pipe_clk_src
> -
> - '#clock-cells':
> - const: 0
> -
> - '#phy-cells':
> - const: 0
> -
> - required:
> - - reg
> - - clocks
> - - '#clock-cells'
> - - '#phy-cells'
> -
> - "^dp-phy@[0-9a-f]+$":
> - type: object
> - additionalProperties: false
> - description:
> - The DP PHY.
> -
> - properties:
> - reg:
> - items:
> - - description: Address and length of TX.
> - - description: Address and length of RX.
> - - description: Address and length of PCS.
> - - description: Address and length of TX2.
> - - description: Address and length of RX2.
> -
> - '#clock-cells':
> - const: 1
> -
> - '#phy-cells':
> - const: 0
> -
> - required:
> - - reg
> - - '#clock-cells'
> - - '#phy-cells'
> -
> -required:
> - - compatible
> - - reg
> - - "#address-cells"
> - - "#size-cells"
> - - ranges
> - - clocks
> - - clock-names
> - - resets
> - - reset-names
> - - vdda-phy-supply
> - - vdda-pll-supply
> -
> -allOf:
> - - if:
> - properties:
> - compatible:
> - enum:
> - - qcom,sc7180-qmp-usb3-dp-phy
> - - qcom,sdm845-qmp-usb3-dp-phy
> - then:
> - properties:
> - clocks:
> - items:
> - - description: Phy aux clock
> - - description: Phy config clock
> - - description: 19.2 MHz ref clk
> - - description: Phy common block aux clock
> - clock-names:
> - items:
> - - const: aux
> - - const: cfg_ahb
> - - const: ref
> - - const: com_aux
> -
> - - if:
> - properties:
> - compatible:
> - enum:
> - - qcom,sc8180x-qmp-usb3-dp-phy
> - then:
> - properties:
> - clocks:
> - items:
> - - description: Phy aux clock
> - - description: 19.2 MHz ref clk
> - - description: Phy common block aux clock
> - clock-names:
> - items:
> - - const: aux
> - - const: ref
> - - const: com_aux
> -
> - - if:
> - properties:
> - compatible:
> - enum:
> - - qcom,sm8250-qmp-usb3-dp-phy
> - then:
> - properties:
> - clocks:
> - items:
> - - description: Phy aux clock
> - - description: Board XO source
> - - description: Phy common block aux clock
> - clock-names:
> - items:
> - - const: aux
> - - const: ref_clk_src
> - - const: com_aux
> -
> -additionalProperties: false
> -
> -examples:
> - - |
> - #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> - usb_1_qmpphy: phy-wrapper@88e9000 {
> - compatible = "qcom,sdm845-qmp-usb3-dp-phy";
> - reg = <0x088e9000 0x18c>,
> - <0x088e8000 0x10>,
> - <0x088ea000 0x40>;
> - reg-names = "usb", "dp_com", "dp";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0x0 0x088e9000 0x2000>;
> -
> - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> - <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> - clock-names = "aux", "cfg_ahb", "ref", "com_aux";
> -
> - resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
> - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
> - reset-names = "phy", "common";
> -
> - vdda-phy-supply = <&vdda_usb2_ss_1p2>;
> - vdda-pll-supply = <&vdda_usb2_ss_core>;
> -
> - usb3-phy@200 {
> - reg = <0x200 0x128>,
> - <0x400 0x200>,
> - <0xc00 0x218>,
> - <0x600 0x128>,
> - <0x800 0x200>,
> - <0xa00 0x100>;
> - #clock-cells = <0>;
> - #phy-cells = <0>;
> - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> - clock-output-names = "usb3_phy_pipe_clk_src";
> - };
> -
> - dp-phy@88ea200 {
> - reg = <0xa200 0x200>,
> - <0xa400 0x200>,
> - <0xaa00 0x200>,
> - <0xa600 0x200>,
> - <0xa800 0x200>;
> - #clock-cells = <1>;
> - #phy-cells = <0>;
> - };
> - };
> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
> index 3cd5fc3e8fab..484f321aefce 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
> @@ -15,25 +15,32 @@ description:
>
> properties:
> compatible:
> - enum:
> - - qcom,sc8280xp-qmp-usb43dp-phy
> - - qcom,sm6350-qmp-usb3-dp-phy
> - - qcom,sm8350-qmp-usb3-dp-phy
> - - qcom,sm8450-qmp-usb3-dp-phy
> - - qcom,sm8550-qmp-usb3-dp-phy
> + oneOf:
> + - enum:
> + - qcom,sc7180-qmp-usb3-dp-phy
> + - qcom,sc8180x-qmp-usb3-dp-phy
> + - qcom,sc8280xp-qmp-usb43dp-phy
> + - qcom,sdm845-qmp-usb3-dp-phy
> + - qcom,sm6350-qmp-usb3-dp-phy
> + - qcom,sm8250-qmp-usb3-dp-phy
> + - qcom,sm8350-qmp-usb3-dp-phy
> + - qcom,sm8450-qmp-usb3-dp-phy
> + - qcom,sm8550-qmp-usb3-dp-phy
> + - items:
> + - enum:
> + - qcom,sc7280-qmp-usb3-dp-phy
> + - const: qcom,sm8250-qmp-usb3-dp-phy
Why are you carrying over this mess to a new binding? Again, this is the
time to get rid of legacy cruft.
> reg:
> maxItems: 1
>
> clocks:
> - maxItems: 4
> + minItems: 3
> + maxItems: 5
>
> clock-names:
> - items:
> - - const: aux
> - - const: ref
> - - const: com_aux
> - - const: usb3_pipe
> + minItems: 3
> + maxItems: 5
>
> power-domains:
> maxItems: 1
> @@ -50,6 +57,8 @@ properties:
>
> vdda-pll-supply: true
>
> + vddp-ref-clk-supply: true
> +
> "#clock-cells":
> const: 1
> description:
> @@ -65,7 +74,6 @@ required:
> - reg
> - clocks
> - clock-names
> - - power-domains
> - resets
> - reset-names
> - vdda-phy-supply
> @@ -73,6 +81,71 @@ required:
> - "#clock-cells"
> - "#phy-cells"
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + enum:
> + - qcom,sc7180-qmp-usb3-dp-phy
> + - qcom,sdm845-qmp-usb3-dp-phy
> + then:
> + properties:
> + clocks:
> + items:
> + - description: Phy aux clock
> + - description: Phy config clock
> + - description: 19.2 MHz ref clk
> + - description: Phy common block aux clock
> + - description: USB3 PIPE clock
These descriptions don't add anything and should not be carried over.
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: com_aux
> + - const: usb3_pipe
Should the cfg_ahb clock be moved last so that you could unify with the
next set?
> +
> + - if:
> + properties:
> + compatible:
> + enum:
> + - qcom,sc8180x-qmp-usb3-dp-phy
> + - qcom,sc8280xp-qmp-usb3-dp-phy
> + then:
> + properties:
> + clocks:
> + items:
> + - description: Phy aux clock
> + - description: 19.2 MHz ref clk
> + - description: Phy common block aux clock
> + - description: USB3 PIPE clock
Please do not add these either.
> + clock-names:
> + items:
> + - const: aux
> + - const: ref
> + - const: com_aux
> + - const: usb3_pipe
> +
> + - if:
> + properties:
> + compatible:
> + enum:
> + - qcom,sm8250-qmp-usb3-dp-phy
> + then:
> + properties:
> + clocks:
> + items:
> + - description: Phy aux clock
> + - description: Board XO source
> + - description: Phy common block aux clock
> + - description: USB3 PIPE clock
> + clock-names:
> + items:
> + - const: aux
> + - const: ref_clk_src
Again, no 'src' clock belong in the binding.
> + - const: com_aux
> + - const: usb3_pipe
> +
> additionalProperties: false
>
> examples:
> @@ -101,3 +174,28 @@ examples:
> #clock-cells = <1>;
> #phy-cells = <1>;
> };
> + - |
> + #define GCC_USB3_PRIM_CLKREF_CLK 151
> + #define GCC_USB_PHY_CFG_AHB2PHY_CLK 161
> +
> + phy@88e8000 {
> + compatible = "qcom,sdm845-qmp-usb3-dp-phy";
> + reg = <0x088e8000 0x3000>;
> +
> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> + <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "aux", "cfg_ahb", "ref", "com_aux", "usb3_pipe";
> +
> + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
> + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
> + reset-names = "phy", "common";
> +
> + vdda-phy-supply = <&vdda_usb2_ss_1p2>;
> + vdda-pll-supply = <&vdda_usb2_ss_core>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <1>;
> + };
I see no point in adding this example either.
Johan
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 03/41] dt-bindings: phy: migrate QMP UFS PHY bindings to qcom,sc8280xp-qmp-ufs-phy.yaml
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 01/41] dt-bindings: phy: migrate QMP USB PHY bindings to qcom,sc8280xp-qmp-usb3-uni-phy.yaml Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 02/41] dt-bindings: phy: migrate combo QMP PHY bindings to qcom,sc8280xp-qmp-usb43dp-phy.yaml Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 7:56 ` Johan Hovold
2023-03-24 2:24 ` [PATCH 04/41] dt-bindings: phy: migrate QMP PCIe PHY bindings to qcom,sc8280xp-qmp-pcie-phy.yaml Dmitry Baryshkov
` (37 subsequent siblings)
40 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Migrate legacy bindings (described in qcom,msm8996-qmp-ufs-phy.yaml)
to qcom,sc8280xp-qmp-ufs-phy.yaml. This removes a need to declare
the child PHY node or split resource regions.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qcom,msm8996-qmp-ufs-phy.yaml | 244 ------------------
.../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 94 ++++++-
2 files changed, 89 insertions(+), 249 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml
deleted file mode 100644
index 80a5348dbfde..000000000000
--- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml
+++ /dev/null
@@ -1,244 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-ufs-phy.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm QMP PHY controller (UFS, MSM8996)
-
-maintainers:
- - Vinod Koul <vkoul@kernel.org>
-
-description:
- QMP PHY controller supports physical layer functionality for a number of
- controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
-
- Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see
- qcom,sc8280xp-qmp-ufs-phy.yaml.
-
-properties:
- compatible:
- enum:
- - qcom,msm8996-qmp-ufs-phy
- - qcom,msm8998-qmp-ufs-phy
- - qcom,sc8180x-qmp-ufs-phy
- - qcom,sdm845-qmp-ufs-phy
- - qcom,sm6115-qmp-ufs-phy
- - qcom,sm6350-qmp-ufs-phy
- - qcom,sm8150-qmp-ufs-phy
- - qcom,sm8250-qmp-ufs-phy
- - qcom,sm8350-qmp-ufs-phy
- - qcom,sm8450-qmp-ufs-phy
-
- reg:
- items:
- - description: serdes
-
- "#address-cells":
- enum: [ 1, 2 ]
-
- "#size-cells":
- enum: [ 1, 2 ]
-
- ranges: true
-
- clocks:
- minItems: 1
- maxItems: 3
-
- clock-names:
- minItems: 1
- maxItems: 3
-
- power-domains:
- maxItems: 1
-
- resets:
- maxItems: 1
-
- reset-names:
- items:
- - const: ufsphy
-
- vdda-phy-supply: true
-
- vdda-pll-supply: true
-
- vddp-ref-clk-supply: true
-
-patternProperties:
- "^phy@[0-9a-f]+$":
- type: object
- description: single PHY-provider child node
- properties:
- reg:
- minItems: 3
- maxItems: 6
-
- "#clock-cells":
- const: 1
-
- "#phy-cells":
- const: 0
-
- required:
- - reg
- - "#phy-cells"
-
- additionalProperties: false
-
-required:
- - compatible
- - reg
- - "#address-cells"
- - "#size-cells"
- - ranges
- - clocks
- - clock-names
- - resets
- - reset-names
- - vdda-phy-supply
- - vdda-pll-supply
-
-additionalProperties: false
-
-allOf:
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,msm8996-qmp-ufs-phy
- then:
- properties:
- clocks:
- maxItems: 1
- clock-names:
- items:
- - const: ref
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,msm8998-qmp-ufs-phy
- - qcom,sc8180x-qmp-ufs-phy
- - qcom,sdm845-qmp-ufs-phy
- - qcom,sm6115-qmp-ufs-phy
- - qcom,sm6350-qmp-ufs-phy
- - qcom,sm8150-qmp-ufs-phy
- - qcom,sm8250-qmp-ufs-phy
- then:
- properties:
- clocks:
- maxItems: 2
- clock-names:
- items:
- - const: ref
- - const: ref_aux
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sm8450-qmp-ufs-phy
- then:
- properties:
- clocks:
- maxItems: 3
- clock-names:
- items:
- - const: ref
- - const: ref_aux
- - const: qref
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,msm8998-qmp-ufs-phy
- - qcom,sdm845-qmp-ufs-phy
- - qcom,sm6350-qmp-ufs-phy
- - qcom,sm8150-qmp-ufs-phy
- - qcom,sm8250-qmp-ufs-phy
- - qcom,sm8350-qmp-ufs-phy
- - qcom,sm8450-qmp-ufs-phy
- then:
- patternProperties:
- "^phy@[0-9a-f]+$":
- properties:
- reg:
- items:
- - description: TX lane 1
- - description: RX lane 1
- - description: PCS
- - description: TX lane 2
- - description: RX lane 2
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sc8180x-qmp-ufs-phy
- then:
- patternProperties:
- "^phy@[0-9a-f]+$":
- properties:
- reg:
- items:
- - description: TX
- - description: RX
- - description: PCS
- - description: PCS_MISC
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,msm8996-qmp-ufs-phy
- - qcom,sm6115-qmp-ufs-phy
- then:
- patternProperties:
- "^phy@[0-9a-f]+$":
- properties:
- reg:
- items:
- - description: TX
- - description: RX
- - description: PCS
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,gcc-sm8250.h>
- #include <dt-bindings/clock/qcom,rpmh.h>
-
- phy-wrapper@1d87000 {
- compatible = "qcom,sm8250-qmp-ufs-phy";
- reg = <0x01d87000 0x1c0>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x01d87000 0x1000>;
-
- clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
- clock-names = "ref", "ref_aux";
-
- resets = <&ufs_mem_hc 0>;
- reset-names = "ufsphy";
-
- vdda-phy-supply = <&vreg_l6b>;
- vdda-pll-supply = <&vreg_l3b>;
-
- phy@400 {
- reg = <0x400 0x108>,
- <0x600 0x1e0>,
- <0xc00 0x1dc>,
- <0x800 0x108>,
- <0xa00 0x1e0>;
- #phy-cells = <0>;
- };
- };
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index 64ed331880f6..1718c68ef2cf 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -16,20 +16,30 @@ description:
properties:
compatible:
enum:
+ - qcom,msm8996-qmp-ufs-phy
+ - qcom,msm8998-qmp-ufs-phy
+ - qcom,sc8180x-qmp-ufs-phy
- qcom,sc8280xp-qmp-ufs-phy
+ - qcom,sdm845-qmp-ufs-phy
+ - qcom,sm6115-qmp-ufs-phy
- qcom,sm6125-qmp-ufs-phy
+ - qcom,sm6350-qmp-ufs-phy
+ - qcom,sm8150-qmp-ufs-phy
+ - qcom,sm8250-qmp-ufs-phy
+ - qcom,sm8350-qmp-ufs-phy
+ - qcom,sm8450-qmp-ufs-phy
- qcom,sm8550-qmp-ufs-phy
reg:
maxItems: 1
clocks:
- maxItems: 2
+ minItems: 1
+ maxItems: 3
clock-names:
- items:
- - const: ref
- - const: ref_aux
+ minItems: 1
+ maxItems: 3
power-domains:
maxItems: 1
@@ -45,6 +55,8 @@ properties:
vdda-pll-supply: true
+ vddp-ref-clk-supply: true
+
"#clock-cells":
const: 1
@@ -56,13 +68,67 @@ required:
- reg
- clocks
- clock-names
- - power-domains
- resets
- reset-names
- vdda-phy-supply
- vdda-pll-supply
- "#phy-cells"
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-qmp-ufs-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ items:
+ - const: ref
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-qmp-ufs-phy
+ - qcom,sc8180x-qmp-ufs-phy
+ - qcom,sc8280xp-qmp-ufs-phy
+ - qcom,sdm845-qmp-ufs-phy
+ - qcom,sm6115-qmp-ufs-phy
+ - qcom,sm6125-qmp-ufs-phy
+ - qcom,sm6350-qmp-ufs-phy
+ - qcom,sm8150-qmp-ufs-phy
+ - qcom,sm8250-qmp-ufs-phy
+ - qcom,sm8550-qmp-ufs-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 2
+ clock-names:
+ items:
+ - const: ref
+ - const: ref_aux
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8450-qmp-ufs-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ items:
+ - const: ref
+ - const: ref_aux
+ - const: qref
+
additionalProperties: false
examples:
@@ -84,5 +150,23 @@ examples:
vdda-phy-supply = <&vreg_l6b>;
vdda-pll-supply = <&vreg_l3b>;
+ #phy-cells = <0>;
+ };
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ phy@1d87000 {
+ compatible = "qcom,sm8250-qmp-ufs-phy";
+ reg = <0x01d87000 0x1c0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ clock-names = "ref", "ref_aux";
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+
+ vdda-phy-supply = <&vreg_l6b>;
+ vdda-pll-supply = <&vreg_l3b>;
+
#phy-cells = <0>;
};
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 03/41] dt-bindings: phy: migrate QMP UFS PHY bindings to qcom,sc8280xp-qmp-ufs-phy.yaml
2023-03-24 2:24 ` [PATCH 03/41] dt-bindings: phy: migrate QMP UFS PHY bindings to qcom,sc8280xp-qmp-ufs-phy.yaml Dmitry Baryshkov
@ 2023-03-24 7:56 ` Johan Hovold
0 siblings, 0 replies; 50+ messages in thread
From: Johan Hovold @ 2023-03-24 7:56 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, linux-arm-msm, linux-phy, Johan Hovold
On Fri, Mar 24, 2023 at 05:24:36AM +0300, Dmitry Baryshkov wrote:
> Migrate legacy bindings (described in qcom,msm8996-qmp-ufs-phy.yaml)
> to qcom,sc8280xp-qmp-ufs-phy.yaml. This removes a need to declare
> the child PHY node or split resource regions.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../phy/qcom,msm8996-qmp-ufs-phy.yaml | 244 ------------------
> .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 94 ++++++-
> 2 files changed, 89 insertions(+), 249 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml
> examples:
> @@ -84,5 +150,23 @@ examples:
> vdda-phy-supply = <&vreg_l6b>;
> vdda-pll-supply = <&vreg_l3b>;
>
> + #phy-cells = <0>;
> + };
> + - |
> + #include <dt-bindings/clock/qcom,rpmh.h>
> +
> + phy@1d87000 {
> + compatible = "qcom,sm8250-qmp-ufs-phy";
> + reg = <0x01d87000 0x1c0>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> + clock-names = "ref", "ref_aux";
> +
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> +
> + vdda-phy-supply = <&vreg_l6b>;
> + vdda-pll-supply = <&vreg_l3b>;
> +
> #phy-cells = <0>;
> };
This example also looks unnecessary.
Johan
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 04/41] dt-bindings: phy: migrate QMP PCIe PHY bindings to qcom,sc8280xp-qmp-pcie-phy.yaml
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (2 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 03/41] dt-bindings: phy: migrate QMP UFS PHY bindings to qcom,sc8280xp-qmp-ufs-phy.yaml Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 8:04 ` Johan Hovold
2023-03-24 2:24 ` [PATCH 05/41] phy: qcom-qmp-usb: make QPHY_PCS_MISC_CLAMP_ENABLE access conditional Dmitry Baryshkov
` (36 subsequent siblings)
40 siblings, 1 reply; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Migrate legacy bindings (described in qcom,ipq8074-qmp-pcie-phy.yaml)
to qcom,sc8280xp-qmp-pcie-phy.yaml. This removes a need to declare
the child PHY node or split resource regions.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 299 ------------------
.../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 213 +++++++++++--
2 files changed, 187 insertions(+), 325 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
deleted file mode 100644
index 62045dcfb20c..000000000000
--- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
+++ /dev/null
@@ -1,299 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm QMP PHY controller (PCIe, IPQ8074)
-
-maintainers:
- - Vinod Koul <vkoul@kernel.org>
-
-description:
- QMP PHY controller supports physical layer functionality for a number of
- controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
-
- Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see
- qcom,sc8280xp-qmp-pcie-phy.yaml.
-
-properties:
- compatible:
- enum:
- - qcom,ipq6018-qmp-pcie-phy
- - qcom,ipq8074-qmp-gen3-pcie-phy
- - qcom,ipq8074-qmp-pcie-phy
- - qcom,msm8998-qmp-pcie-phy
- - qcom,sc8180x-qmp-pcie-phy
- - qcom,sdm845-qhp-pcie-phy
- - qcom,sdm845-qmp-pcie-phy
- - qcom,sdx55-qmp-pcie-phy
- - qcom,sm8250-qmp-gen3x1-pcie-phy
- - qcom,sm8250-qmp-gen3x2-pcie-phy
- - qcom,sm8250-qmp-modem-pcie-phy
- - qcom,sm8450-qmp-gen3x1-pcie-phy
- - qcom,sm8450-qmp-gen4x2-pcie-phy
-
- reg:
- items:
- - description: serdes
-
- "#address-cells":
- enum: [ 1, 2 ]
-
- "#size-cells":
- enum: [ 1, 2 ]
-
- ranges: true
-
- clocks:
- minItems: 2
- maxItems: 4
-
- clock-names:
- minItems: 2
- maxItems: 4
-
- resets:
- minItems: 1
- maxItems: 2
-
- reset-names:
- minItems: 1
- maxItems: 2
-
- vdda-phy-supply: true
-
- vdda-pll-supply: true
-
- vddp-ref-clk-supply: true
-
-patternProperties:
- "^phy@[0-9a-f]+$":
- type: object
- description: single PHY-provider child node
- properties:
- reg:
- minItems: 3
- maxItems: 6
-
- clocks:
- items:
- - description: PIPE clock
-
- clock-names:
- deprecated: true
- items:
- - const: pipe0
-
- "#clock-cells":
- const: 0
-
- clock-output-names:
- maxItems: 1
-
- "#phy-cells":
- const: 0
-
- required:
- - reg
- - clocks
- - "#clock-cells"
- - clock-output-names
- - "#phy-cells"
-
- additionalProperties: false
-
-required:
- - compatible
- - reg
- - "#address-cells"
- - "#size-cells"
- - ranges
- - clocks
- - clock-names
- - resets
- - reset-names
-
-additionalProperties: false
-
-allOf:
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,msm8998-qmp-pcie-phy
- then:
- properties:
- clocks:
- maxItems: 3
- clock-names:
- items:
- - const: aux
- - const: cfg_ahb
- - const: ref
- resets:
- maxItems: 2
- reset-names:
- items:
- - const: phy
- - const: common
- required:
- - vdda-phy-supply
- - vdda-pll-supply
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,ipq6018-qmp-pcie-phy
- - qcom,ipq8074-qmp-gen3-pcie-phy
- - qcom,ipq8074-qmp-pcie-phy
- then:
- properties:
- clocks:
- maxItems: 2
- clock-names:
- items:
- - const: aux
- - const: cfg_ahb
- resets:
- maxItems: 2
- reset-names:
- items:
- - const: phy
- - const: common
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sc8180x-qmp-pcie-phy
- - qcom,sdm845-qhp-pcie-phy
- - qcom,sdm845-qmp-pcie-phy
- - qcom,sdx55-qmp-pcie-phy
- - qcom,sm8250-qmp-gen3x1-pcie-phy
- - qcom,sm8250-qmp-gen3x2-pcie-phy
- - qcom,sm8250-qmp-modem-pcie-phy
- - qcom,sm8450-qmp-gen3x1-pcie-phy
- - qcom,sm8450-qmp-gen4x2-pcie-phy
- then:
- properties:
- clocks:
- maxItems: 4
- clock-names:
- items:
- - const: aux
- - const: cfg_ahb
- - const: ref
- - const: refgen
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: phy
- required:
- - vdda-phy-supply
- - vdda-pll-supply
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sm8250-qmp-gen3x2-pcie-phy
- - qcom,sm8250-qmp-modem-pcie-phy
- - qcom,sm8450-qmp-gen4x2-pcie-phy
- then:
- patternProperties:
- "^phy@[0-9a-f]+$":
- properties:
- reg:
- items:
- - description: TX lane 1
- - description: RX lane 1
- - description: PCS
- - description: TX lane 2
- - description: RX lane 2
- - description: PCS_MISC
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sc8180x-qmp-pcie-phy
- - qcom,sdm845-qmp-pcie-phy
- - qcom,sdx55-qmp-pcie-phy
- - qcom,sm8250-qmp-gen3x1-pcie-phy
- - qcom,sm8450-qmp-gen3x1-pcie-phy
- then:
- patternProperties:
- "^phy@[0-9a-f]+$":
- properties:
- reg:
- items:
- - description: TX
- - description: RX
- - description: PCS
- - description: PCS_MISC
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,ipq6018-qmp-pcie-phy
- - qcom,ipq8074-qmp-pcie-phy
- - qcom,msm8998-qmp-pcie-phy
- - qcom,sdm845-qhp-pcie-phy
- then:
- patternProperties:
- "^phy@[0-9a-f]+$":
- properties:
- reg:
- items:
- - description: TX
- - description: RX
- - description: PCS
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,gcc-sm8250.h>
- phy-wrapper@1c0e000 {
- compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
- reg = <0x01c0e000 0x1c0>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x01c0e000 0x1000>;
-
- clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
- <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
- <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "refgen";
-
- resets = <&gcc GCC_PCIE_1_PHY_BCR>;
- reset-names = "phy";
-
- vdda-phy-supply = <&vreg_l10c_0p88>;
- vdda-pll-supply = <&vreg_l6b_1p2>;
-
- phy@200 {
- reg = <0x200 0x170>,
- <0x400 0x200>,
- <0xa00 0x1f0>,
- <0x600 0x170>,
- <0x800 0x200>,
- <0xe00 0xf4>;
-
- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
-
- #clock-cells = <0>;
- clock-output-names = "pcie_1_pipe_clk";
-
- #phy-cells = <0>;
- };
- };
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index ef49efbd0a20..328588448c6b 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -16,10 +16,23 @@ description:
properties:
compatible:
enum:
+ - qcom,ipq6018-qmp-pcie-phy
+ - qcom,ipq8074-qmp-gen3-pcie-phy
+ - qcom,ipq8074-qmp-pcie-phy
+ - qcom,msm8998-qmp-pcie-phy
+ - qcom,sc8180x-qmp-pcie-phy
- qcom,sc8280xp-qmp-gen3x1-pcie-phy
- qcom,sc8280xp-qmp-gen3x2-pcie-phy
- qcom,sc8280xp-qmp-gen3x4-pcie-phy
+ - qcom,sdm845-qhp-pcie-phy
+ - qcom,sdm845-qmp-pcie-phy
+ - qcom,sdx55-qmp-pcie-phy
+ - qcom,sm8250-qmp-gen3x1-pcie-phy
+ - qcom,sm8250-qmp-gen3x2-pcie-phy
+ - qcom,sm8250-qmp-modem-pcie-phy
- qcom,sm8350-qmp-gen3x1-pcie-phy
+ - qcom,sm8450-qmp-gen3x1-pcie-phy
+ - qcom,sm8450-qmp-gen4x2-pcie-phy
- qcom,sm8550-qmp-gen3x2-pcie-phy
- qcom,sm8550-qmp-gen4x2-pcie-phy
@@ -28,18 +41,12 @@ properties:
maxItems: 2
clocks:
- minItems: 5
+ minItems: 3
maxItems: 6
clock-names:
- minItems: 5
- items:
- - const: aux
- - const: cfg_ahb
- - const: ref
- - const: rchng
- - const: pipe
- - const: pipediv2
+ minItems: 3
+ maxItems: 6
power-domains:
maxItems: 1
@@ -50,9 +57,7 @@ properties:
reset-names:
minItems: 1
- items:
- - const: phy
- - const: phy_nocsr
+ maxItems: 2
vdda-phy-supply: true
@@ -83,11 +88,8 @@ required:
- reg
- clocks
- clock-names
- - power-domains
- resets
- reset-names
- - vdda-phy-supply
- - vdda-pll-supply
- "#clock-cells"
- clock-output-names
- "#phy-cells"
@@ -119,21 +121,116 @@ allOf:
compatible:
contains:
enum:
- - qcom,sm8350-qmp-gen3x1-pcie-phy
- - qcom,sm8550-qmp-gen3x2-pcie-phy
- - qcom,sm8550-qmp-gen4x2-pcie-phy
+ - qcom,msm8998-qmp-pcie-phy
then:
properties:
clocks:
- maxItems: 5
+ maxItems: 4
clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: pipe
+ resets:
+ maxItems: 2
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ required:
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq6018-qmp-pcie-phy
+ - qcom,ipq8074-qmp-gen3-pcie-phy
+ - qcom,ipq8074-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: pipe
+ resets:
+ maxItems: 2
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc8180x-qmp-pcie-phy
+ - qcom,sdm845-qhp-pcie-phy
+ - qcom,sdm845-qmp-pcie-phy
+ - qcom,sdx55-qmp-pcie-phy
+ - qcom,sm8250-qmp-gen3x1-pcie-phy
+ - qcom,sm8250-qmp-gen3x2-pcie-phy
+ - qcom,sm8250-qmp-modem-pcie-phy
+ - qcom,sm8450-qmp-gen3x1-pcie-phy
+ - qcom,sm8450-qmp-gen4x2-pcie-phy
+ then:
+ properties:
+ clocks:
maxItems: 5
- else:
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: refgen
+ - const: pipe
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: phy
+ required:
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8350-qmp-gen3x1-pcie-phy
+ - qcom,sm8550-qmp-gen3x2-pcie-phy
+ resets:
+ minItems: 1
+ reset-names:
+ items:
+ - const: phy
+ then:
properties:
clocks:
- minItems: 6
+ maxItems: 5
clock-names:
- minItems: 6
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: rchng
+ - const: pipe
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: phy
+ required:
+ - vdda-phy-supply
+ - vdda-pll-supply
- if:
properties:
@@ -143,16 +240,53 @@ allOf:
- qcom,sm8550-qmp-gen4x2-pcie-phy
then:
properties:
+ clocks:
+ maxItems: 5
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: rchng
+ - const: pipe
resets:
minItems: 2
reset-names:
- minItems: 2
- else:
+ items:
+ - const: phy
+ - const: phy_nocsr
+ required:
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc8280xp-qmp-gen3x1-pcie-phy
+ - qcom,sc8280xp-qmp-gen3x2-pcie-phy
+ - qcom,sc8280xp-qmp-gen3x4-pcie-phy
+ then:
properties:
+ clocks:
+ minItems: 6
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: rchng
+ - const: pipe
+ - const: pipediv2
resets:
- maxItems: 1
+ minItems: 1
reset-names:
- maxItems: 1
+ items:
+ - const: phy
+ required:
+ - vdda-phy-supply
+ - vdda-pll-supply
examples:
- |
@@ -213,3 +347,30 @@ examples:
#phy-cells = <0>;
};
+ - |
+ #define GCC_PCIE1_PHY_REFGEN_CLK 47
+ #define GCC_PCIE_PHY_AUX_CLK 71
+ #define GCC_PCIE_WIGIG_CLKREF_EN 74
+
+ phy@1c0e000 {
+ compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
+ reg = <0x01c0e000 0x1c0>;
+
+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
+ <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "refgen", "pipe";
+
+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+ reset-names = "phy";
+
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_1_pipe_clk";
+
+ #phy-cells = <0>;
+ };
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH 04/41] dt-bindings: phy: migrate QMP PCIe PHY bindings to qcom,sc8280xp-qmp-pcie-phy.yaml
2023-03-24 2:24 ` [PATCH 04/41] dt-bindings: phy: migrate QMP PCIe PHY bindings to qcom,sc8280xp-qmp-pcie-phy.yaml Dmitry Baryshkov
@ 2023-03-24 8:04 ` Johan Hovold
2023-03-24 12:16 ` Dmitry Baryshkov
0 siblings, 1 reply; 50+ messages in thread
From: Johan Hovold @ 2023-03-24 8:04 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, linux-arm-msm, linux-phy, Johan Hovold
On Fri, Mar 24, 2023 at 05:24:37AM +0300, Dmitry Baryshkov wrote:
> Migrate legacy bindings (described in qcom,ipq8074-qmp-pcie-phy.yaml)
> to qcom,sc8280xp-qmp-pcie-phy.yaml. This removes a need to declare
> the child PHY node or split resource regions.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 299 ------------------
> .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 213 +++++++++++--
> 2 files changed, 187 insertions(+), 325 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> index ef49efbd0a20..328588448c6b 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> @@ -16,10 +16,23 @@ description:
> properties:
> compatible:
> enum:
> + - qcom,ipq6018-qmp-pcie-phy
> + - qcom,ipq8074-qmp-gen3-pcie-phy
> + - qcom,ipq8074-qmp-pcie-phy
> + - qcom,msm8998-qmp-pcie-phy
> + - qcom,sc8180x-qmp-pcie-phy
> - qcom,sc8280xp-qmp-gen3x1-pcie-phy
> - qcom,sc8280xp-qmp-gen3x2-pcie-phy
> - qcom,sc8280xp-qmp-gen3x4-pcie-phy
> + - qcom,sdm845-qhp-pcie-phy
> + - qcom,sdm845-qmp-pcie-phy
> + - qcom,sdx55-qmp-pcie-phy
> + - qcom,sm8250-qmp-gen3x1-pcie-phy
> + - qcom,sm8250-qmp-gen3x2-pcie-phy
> + - qcom,sm8250-qmp-modem-pcie-phy
> - qcom,sm8350-qmp-gen3x1-pcie-phy
> + - qcom,sm8450-qmp-gen3x1-pcie-phy
> + - qcom,sm8450-qmp-gen4x2-pcie-phy
> - qcom,sm8550-qmp-gen3x2-pcie-phy
> - qcom,sm8550-qmp-gen4x2-pcie-phy
>
> @@ -28,18 +41,12 @@ properties:
> maxItems: 2
>
> clocks:
> - minItems: 5
> + minItems: 3
> maxItems: 6
>
> clock-names:
> - minItems: 5
> - items:
> - - const: aux
> - - const: cfg_ahb
> - - const: ref
> - - const: rchng
> - - const: pipe
> - - const: pipediv2
> + minItems: 3
> + maxItems: 6
>
> power-domains:
> maxItems: 1
> @@ -50,9 +57,7 @@ properties:
>
> reset-names:
> minItems: 1
> - items:
> - - const: phy
> - - const: phy_nocsr
> + maxItems: 2
>
> vdda-phy-supply: true
>
> @@ -83,11 +88,8 @@ required:
> - reg
> - clocks
> - clock-names
> - - power-domains
> - resets
> - reset-names
> - - vdda-phy-supply
> - - vdda-pll-supply
> - "#clock-cells"
> - clock-output-names
> - "#phy-cells"
> @@ -119,21 +121,116 @@ allOf:
> compatible:
> contains:
> enum:
> - - qcom,sm8350-qmp-gen3x1-pcie-phy
> - - qcom,sm8550-qmp-gen3x2-pcie-phy
> - - qcom,sm8550-qmp-gen4x2-pcie-phy
> + - qcom,msm8998-qmp-pcie-phy
> then:
> properties:
> clocks:
> - maxItems: 5
> + maxItems: 4
> clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: pipe
> + resets:
> + maxItems: 2
> + reset-names:
> + items:
> + - const: phy
> + - const: common
Reset name looks wrong here too.
> + required:
> + - vdda-phy-supply
> + - vdda-pll-supply
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq6018-qmp-pcie-phy
> + - qcom,ipq8074-qmp-gen3-pcie-phy
> + - qcom,ipq8074-qmp-pcie-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 3
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: pipe
> + resets:
> + maxItems: 2
> + reset-names:
> + items:
> + - const: phy
> + - const: common
Same here.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc8180x-qmp-pcie-phy
> + - qcom,sdm845-qhp-pcie-phy
> + - qcom,sdm845-qmp-pcie-phy
> + - qcom,sdx55-qmp-pcie-phy
> + - qcom,sm8250-qmp-gen3x1-pcie-phy
> + - qcom,sm8250-qmp-gen3x2-pcie-phy
> + - qcom,sm8250-qmp-modem-pcie-phy
> + - qcom,sm8450-qmp-gen3x1-pcie-phy
> + - qcom,sm8450-qmp-gen4x2-pcie-phy
> + then:
> + properties:
> + clocks:
> maxItems: 5
> - else:
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: refgen
This one should be named 'rchng' and this set a strict subset of the
sc8280xp clocks.
> + - const: pipe
> + resets:
> + maxItems: 1
> + reset-names:
> + items:
> + - const: phy
> + required:
> + - vdda-phy-supply
> + - vdda-pll-supply
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sm8350-qmp-gen3x1-pcie-phy
> + - qcom,sm8550-qmp-gen3x2-pcie-phy
> + resets:
> + minItems: 1
> + reset-names:
> + items:
> + - const: phy
> + then:
> properties:
> clocks:
> - minItems: 6
> + maxItems: 5
> clock-names:
> - minItems: 6
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: rchng
> + - const: pipe
> + resets:
> + maxItems: 1
> + reset-names:
> + items:
> + - const: phy
> + required:
> + - vdda-phy-supply
> + - vdda-pll-supply
>
> - if:
> properties:
> @@ -143,16 +240,53 @@ allOf:
> - qcom,sm8550-qmp-gen4x2-pcie-phy
> then:
> properties:
> + clocks:
> + maxItems: 5
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: rchng
> + - const: pipe
> resets:
> minItems: 2
> reset-names:
> - minItems: 2
> - else:
> + items:
> + - const: phy
> + - const: phy_nocsr
> + required:
> + - vdda-phy-supply
> + - vdda-pll-supply
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc8280xp-qmp-gen3x1-pcie-phy
> + - qcom,sc8280xp-qmp-gen3x2-pcie-phy
> + - qcom,sc8280xp-qmp-gen3x4-pcie-phy
> + then:
> properties:
> + clocks:
> + minItems: 6
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: rchng
> + - const: pipe
> + - const: pipediv2
> resets:
> - maxItems: 1
> + minItems: 1
> reset-names:
> - maxItems: 1
> + items:
> + - const: phy
> + required:
> + - vdda-phy-supply
> + - vdda-pll-supply
>
> examples:
> - |
> @@ -213,3 +347,30 @@ examples:
>
> #phy-cells = <0>;
> };
> + - |
> + #define GCC_PCIE1_PHY_REFGEN_CLK 47
> + #define GCC_PCIE_PHY_AUX_CLK 71
> + #define GCC_PCIE_WIGIG_CLKREF_EN 74
> +
> + phy@1c0e000 {
> + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
> + reg = <0x01c0e000 0x1c0>;
> +
> + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
> + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
> + <&gcc GCC_PCIE_1_PIPE_CLK>;
> + clock-names = "aux", "cfg_ahb", "ref", "refgen", "pipe";
> +
> + resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> + reset-names = "phy";
> +
> + vdda-phy-supply = <&vreg_l10c_0p88>;
> + vdda-pll-supply = <&vreg_l6b_1p2>;
> +
> + #clock-cells = <0>;
> + clock-output-names = "pcie_1_pipe_clk";
> +
> + #phy-cells = <0>;
> + };
This example also looks redundant.
Johan
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH 04/41] dt-bindings: phy: migrate QMP PCIe PHY bindings to qcom,sc8280xp-qmp-pcie-phy.yaml
2023-03-24 8:04 ` Johan Hovold
@ 2023-03-24 12:16 ` Dmitry Baryshkov
0 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 12:16 UTC (permalink / raw)
To: Johan Hovold
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, linux-arm-msm, linux-phy, Johan Hovold
On Fri, 24 Mar 2023 at 10:04, Johan Hovold <johan@kernel.org> wrote:
>
> On Fri, Mar 24, 2023 at 05:24:37AM +0300, Dmitry Baryshkov wrote:
> > Migrate legacy bindings (described in qcom,ipq8074-qmp-pcie-phy.yaml)
> > to qcom,sc8280xp-qmp-pcie-phy.yaml. This removes a need to declare
> > the child PHY node or split resource regions.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > .../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 299 ------------------
> > .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 213 +++++++++++--
> > 2 files changed, 187 insertions(+), 325 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
>
> > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> > index ef49efbd0a20..328588448c6b 100644
> > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> > @@ -16,10 +16,23 @@ description:
> > properties:
> > compatible:
> > enum:
> > + - qcom,ipq6018-qmp-pcie-phy
> > + - qcom,ipq8074-qmp-gen3-pcie-phy
> > + - qcom,ipq8074-qmp-pcie-phy
> > + - qcom,msm8998-qmp-pcie-phy
> > + - qcom,sc8180x-qmp-pcie-phy
> > - qcom,sc8280xp-qmp-gen3x1-pcie-phy
> > - qcom,sc8280xp-qmp-gen3x2-pcie-phy
> > - qcom,sc8280xp-qmp-gen3x4-pcie-phy
> > + - qcom,sdm845-qhp-pcie-phy
> > + - qcom,sdm845-qmp-pcie-phy
> > + - qcom,sdx55-qmp-pcie-phy
> > + - qcom,sm8250-qmp-gen3x1-pcie-phy
> > + - qcom,sm8250-qmp-gen3x2-pcie-phy
> > + - qcom,sm8250-qmp-modem-pcie-phy
> > - qcom,sm8350-qmp-gen3x1-pcie-phy
> > + - qcom,sm8450-qmp-gen3x1-pcie-phy
> > + - qcom,sm8450-qmp-gen4x2-pcie-phy
> > - qcom,sm8550-qmp-gen3x2-pcie-phy
> > - qcom,sm8550-qmp-gen4x2-pcie-phy
> >
> > @@ -28,18 +41,12 @@ properties:
> > maxItems: 2
> >
> > clocks:
> > - minItems: 5
> > + minItems: 3
> > maxItems: 6
> >
> > clock-names:
> > - minItems: 5
> > - items:
> > - - const: aux
> > - - const: cfg_ahb
> > - - const: ref
> > - - const: rchng
> > - - const: pipe
> > - - const: pipediv2
> > + minItems: 3
> > + maxItems: 6
> >
> > power-domains:
> > maxItems: 1
> > @@ -50,9 +57,7 @@ properties:
> >
> > reset-names:
> > minItems: 1
> > - items:
> > - - const: phy
> > - - const: phy_nocsr
> > + maxItems: 2
> >
> > vdda-phy-supply: true
> >
> > @@ -83,11 +88,8 @@ required:
> > - reg
> > - clocks
> > - clock-names
> > - - power-domains
> > - resets
> > - reset-names
> > - - vdda-phy-supply
> > - - vdda-pll-supply
> > - "#clock-cells"
> > - clock-output-names
> > - "#phy-cells"
> > @@ -119,21 +121,116 @@ allOf:
> > compatible:
> > contains:
> > enum:
> > - - qcom,sm8350-qmp-gen3x1-pcie-phy
> > - - qcom,sm8550-qmp-gen3x2-pcie-phy
> > - - qcom,sm8550-qmp-gen4x2-pcie-phy
> > + - qcom,msm8998-qmp-pcie-phy
> > then:
> > properties:
> > clocks:
> > - maxItems: 5
> > + maxItems: 4
> > clock-names:
> > + items:
> > + - const: aux
> > + - const: cfg_ahb
> > + - const: ref
> > + - const: pipe
> > + resets:
> > + maxItems: 2
> > + reset-names:
> > + items:
> > + - const: phy
> > + - const: common
>
> Reset name looks wrong here too.
>
> > + required:
> > + - vdda-phy-supply
> > + - vdda-pll-supply
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,ipq6018-qmp-pcie-phy
> > + - qcom,ipq8074-qmp-gen3-pcie-phy
> > + - qcom,ipq8074-qmp-pcie-phy
> > + then:
> > + properties:
> > + clocks:
> > + maxItems: 3
> > + clock-names:
> > + items:
> > + - const: aux
> > + - const: cfg_ahb
> > + - const: pipe
> > + resets:
> > + maxItems: 2
> > + reset-names:
> > + items:
> > + - const: phy
> > + - const: common
>
> Same here.
>
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,sc8180x-qmp-pcie-phy
> > + - qcom,sdm845-qhp-pcie-phy
> > + - qcom,sdm845-qmp-pcie-phy
> > + - qcom,sdx55-qmp-pcie-phy
> > + - qcom,sm8250-qmp-gen3x1-pcie-phy
> > + - qcom,sm8250-qmp-gen3x2-pcie-phy
> > + - qcom,sm8250-qmp-modem-pcie-phy
> > + - qcom,sm8450-qmp-gen3x1-pcie-phy
> > + - qcom,sm8450-qmp-gen4x2-pcie-phy
> > + then:
> > + properties:
> > + clocks:
> > maxItems: 5
> > - else:
> > + clock-names:
> > + items:
> > + - const: aux
> > + - const: cfg_ahb
> > + - const: ref
> > + - const: refgen
>
> This one should be named 'rchng' and this set a strict subset of the
> sc8280xp clocks.
Ack. Same story as the resets. Let's stop my grumbling and move
clock/reset parsing to legacy vs non-legacy code.
>
> > + - const: pipe
> > + resets:
> > + maxItems: 1
> > + reset-names:
> > + items:
> > + - const: phy
> > + required:
> > + - vdda-phy-supply
> > + - vdda-pll-supply
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,sm8350-qmp-gen3x1-pcie-phy
> > + - qcom,sm8550-qmp-gen3x2-pcie-phy
> > + resets:
> > + minItems: 1
> > + reset-names:
> > + items:
> > + - const: phy
> > + then:
> > properties:
> > clocks:
> > - minItems: 6
> > + maxItems: 5
> > clock-names:
> > - minItems: 6
> > + items:
> > + - const: aux
> > + - const: cfg_ahb
> > + - const: ref
> > + - const: rchng
> > + - const: pipe
> > + resets:
> > + maxItems: 1
> > + reset-names:
> > + items:
> > + - const: phy
> > + required:
> > + - vdda-phy-supply
> > + - vdda-pll-supply
> >
> > - if:
> > properties:
> > @@ -143,16 +240,53 @@ allOf:
> > - qcom,sm8550-qmp-gen4x2-pcie-phy
> > then:
> > properties:
> > + clocks:
> > + maxItems: 5
> > + clock-names:
> > + items:
> > + - const: aux
> > + - const: cfg_ahb
> > + - const: ref
> > + - const: rchng
> > + - const: pipe
> > resets:
> > minItems: 2
> > reset-names:
> > - minItems: 2
> > - else:
> > + items:
> > + - const: phy
> > + - const: phy_nocsr
> > + required:
> > + - vdda-phy-supply
> > + - vdda-pll-supply
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,sc8280xp-qmp-gen3x1-pcie-phy
> > + - qcom,sc8280xp-qmp-gen3x2-pcie-phy
> > + - qcom,sc8280xp-qmp-gen3x4-pcie-phy
> > + then:
> > properties:
> > + clocks:
> > + minItems: 6
> > + clock-names:
> > + items:
> > + - const: aux
> > + - const: cfg_ahb
> > + - const: ref
> > + - const: rchng
> > + - const: pipe
> > + - const: pipediv2
> > resets:
> > - maxItems: 1
> > + minItems: 1
> > reset-names:
> > - maxItems: 1
> > + items:
> > + - const: phy
> > + required:
> > + - vdda-phy-supply
> > + - vdda-pll-supply
> >
> > examples:
> > - |
> > @@ -213,3 +347,30 @@ examples:
> >
> > #phy-cells = <0>;
> > };
> > + - |
> > + #define GCC_PCIE1_PHY_REFGEN_CLK 47
> > + #define GCC_PCIE_PHY_AUX_CLK 71
> > + #define GCC_PCIE_WIGIG_CLKREF_EN 74
> > +
> > + phy@1c0e000 {
> > + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
> > + reg = <0x01c0e000 0x1c0>;
> > +
> > + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> > + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> > + <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
> > + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
> > + <&gcc GCC_PCIE_1_PIPE_CLK>;
> > + clock-names = "aux", "cfg_ahb", "ref", "refgen", "pipe";
> > +
> > + resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> > + reset-names = "phy";
> > +
> > + vdda-phy-supply = <&vreg_l10c_0p88>;
> > + vdda-pll-supply = <&vreg_l6b_1p2>;
> > +
> > + #clock-cells = <0>;
> > + clock-output-names = "pcie_1_pipe_clk";
> > +
> > + #phy-cells = <0>;
> > + };
>
> This example also looks redundant.
>
> Johan
--
With best wishes
Dmitry
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 05/41] phy: qcom-qmp-usb: make QPHY_PCS_MISC_CLAMP_ENABLE access conditional
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (3 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 04/41] dt-bindings: phy: migrate QMP PCIe PHY bindings to qcom,sc8280xp-qmp-pcie-phy.yaml Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 06/41] phy: qcom-qmp: move PCS MISC V4 registers to separate header Dmitry Baryshkov
` (35 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
The register QPHY_V[34]_PCS_MISC_CLAMP_ENABLE is present only on some
SoC families. Other platforms (qcm2290) can have PCS_MISC region, but do
not have this register. Add it to the register layout table and check
that it is defined before toggling CLAMP settings.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index a49711c5a63d..269350687259 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -95,6 +95,7 @@ enum qphy_reg_layout {
QPHY_PCS_AUTONOMOUS_MODE_CTRL,
QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
QPHY_PCS_POWER_DOWN_CONTROL,
+ QPHY_PCS_MISC_CLAMP_ENABLE,
/* Keep last to ensure regs_layout arrays are properly initialized */
QPHY_LAYOUT_SIZE
};
@@ -115,6 +116,16 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
+ [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V3_PCS_MISC_CLAMP_ENABLE,
+};
+
+static const unsigned int qmp_v3_usb3phy_regs_layout_qcm2290[QPHY_LAYOUT_SIZE] = {
+ [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
+ [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
+ [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
};
static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
@@ -126,6 +137,7 @@ static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
/* In PCS_USB */
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
+ [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V4_PCS_MISC_CLAMP_ENABLE,
};
static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
@@ -1936,7 +1948,7 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
.num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = qmp_v3_usb3phy_regs_layout,
+ .regs = qmp_v3_usb3phy_regs_layout_qcm2290,
};
static void qmp_usb_configure_lane(void __iomem *base,
@@ -2198,8 +2210,8 @@ static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp)
qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
/* Enable i/o clamp_n for autonomous mode */
- if (pcs_misc)
- qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
+ if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])
+ qphy_clrbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);
}
static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp)
@@ -2209,8 +2221,8 @@ static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp)
void __iomem *pcs_misc = qmp->pcs_misc;
/* Disable i/o clamp_n on resume for normal mode */
- if (pcs_misc)
- qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
+ if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])
+ qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);
qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 06/41] phy: qcom-qmp: move PCS MISC V4 registers to separate header
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (4 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 05/41] phy: qcom-qmp-usb: make QPHY_PCS_MISC_CLAMP_ENABLE access conditional Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 07/41] phy: qcom-qmp-usb: populate offsets configuration Dmitry Baryshkov
` (34 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Move PCS MISC V4 registers to the separate header.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v4.h | 17 +++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 1 +
drivers/phy/qualcomm/phy-qcom-qmp.h | 8 --------
3 files changed, 18 insertions(+), 8 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v4.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v4.h
new file mode 100644
index 000000000000..e256a089f228
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v4.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_MISC_V4_H_
+#define QCOM_PHY_QMP_PCS_MISC_V4_H_
+
+/* Only for QMP V4 PHY - PCS_MISC registers */
+#define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00
+#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04
+#define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08
+#define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c
+#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10
+#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index 269350687259..8a1dd5d80145 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -22,6 +22,7 @@
#include "phy-qcom-qmp.h"
#include "phy-qcom-qmp-pcs-misc-v3.h"
+#include "phy-qcom-qmp-pcs-misc-v4.h"
#include "phy-qcom-qmp-pcs-usb-v4.h"
#include "phy-qcom-qmp-pcs-usb-v5.h"
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 7ee4b0e07d11..1581d9b3d25c 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -126,14 +126,6 @@
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
#define QSERDES_V4_DP_PHY_STATUS 0x0dc
-/* Only for QMP V4 PHY - PCS_MISC registers */
-#define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00
-#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04
-#define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08
-#define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c
-#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10
-#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14
-
/* Only for QMP V6 PHY - DP PHY registers */
#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
#define QSERDES_V6_DP_PHY_STATUS 0x0e4
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 07/41] phy: qcom-qmp-usb: populate offsets configuration
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (5 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 06/41] phy: qcom-qmp: move PCS MISC V4 registers to separate header Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 08/41] phy: qcom-qmp-ufs: " Dmitry Baryshkov
` (33 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Populate offsets configuration for the rest of USB PHYs to make it
possible to switch them to the new (single-node) bindings style.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 99 ++++++++++++++++++++++++-
1 file changed, 98 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index 8a1dd5d80145..3fe7efafa8b8 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -1425,8 +1425,12 @@ struct qmp_usb_offsets {
u16 serdes;
u16 pcs;
u16 pcs_usb;
+ u16 pcs_misc;
u16 tx;
u16 rx;
+ u16 tx2;
+ u16 rx2;
+ u16 dp_com;
};
/* struct qmp_phy_cfg - per-PHY initialization config */
@@ -1571,6 +1575,59 @@ static const char * const qmp_phy_vreg_l[] = {
"vdda-phy", "vdda-pll",
};
+static const struct qmp_usb_offsets qmp_usb_offsets_v2 = {
+ .serdes = 0,
+ .pcs = 0x0600,
+ .tx = 0x0200,
+ .rx = 0x0400,
+};
+
+static const struct qmp_usb_offsets qmp_usb_offsets_v3 = {
+ .serdes = 0,
+ .pcs = 0x0800,
+ .pcs_misc = 0x0600,
+ .tx = 0x0200,
+ .rx = 0x0400,
+};
+
+static const struct qmp_usb_offsets qmp_usb_offsets_v3_combo = {
+ .serdes = 0x1000,
+ .pcs = 0x1c00,
+ .pcs_usb = 0x1f00,
+ .tx = 0x1200,
+ .rx = 0x1400,
+ .tx2 = 0x1600,
+ .rx2 = 0x1800,
+ .dp_com = 0,
+};
+
+static const struct qmp_usb_offsets qmp_usb_offsets_v3_msm8998 = {
+ .serdes = 0,
+ .pcs = 0x0c00,
+ .tx = 0x0200,
+ .rx = 0x0400,
+ .tx2 = 0x0600,
+ .rx2 = 0x0800,
+};
+
+static const struct qmp_usb_offsets qmp_usb_offsets_v3_qcm2290 = {
+ .serdes = 0x0000,
+ .pcs = 0x0c00,
+ .pcs_misc = 0x0a00,
+ .tx = 0x0200,
+ .rx = 0x0400,
+ .tx2 = 0x0600,
+ .rx2 = 0x0800,
+};
+
+static const struct qmp_usb_offsets qmp_usb_offsets_v4 = {
+ .serdes = 0,
+ .pcs = 0x0800,
+ .pcs_usb = 0x0e00,
+ .tx = 0x0200,
+ .rx = 0x0400,
+};
+
static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
.serdes = 0,
.pcs = 0x0200,
@@ -1582,6 +1639,8 @@ static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
.lanes = 1,
+ .offsets = &qmp_usb_offsets_v3,
+
.serdes_tbl = ipq8074_usb3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
.tx_tbl = msm8996_usb3_tx_tbl,
@@ -1602,6 +1661,8 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
.lanes = 1,
+ .offsets = &qmp_usb_offsets_v3,
+
.serdes_tbl = msm8996_usb3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
.tx_tbl = msm8996_usb3_tx_tbl,
@@ -1622,6 +1683,8 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
.lanes = 2,
+ .offsets = &qmp_usb_offsets_v3_combo,
+
.serdes_tbl = qmp_v3_usb3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
.tx_tbl = qmp_v3_usb3_tx_tbl,
@@ -1645,6 +1708,8 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
.lanes = 2,
+ .offsets = &qmp_usb_offsets_v3_combo,
+
.serdes_tbl = qmp_v3_usb3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
.tx_tbl = qmp_v3_usb3_tx_tbl,
@@ -1690,6 +1755,8 @@ static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {
static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
.lanes = 1,
+ .offsets = &qmp_usb_offsets_v3,
+
.serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
.tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
@@ -1712,6 +1779,8 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
.lanes = 2,
+ .offsets = &qmp_usb_offsets_v3_msm8998,
+
.serdes_tbl = msm8998_usb3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
.tx_tbl = msm8998_usb3_tx_tbl,
@@ -1732,6 +1801,8 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
.lanes = 2,
+ .offsets = &qmp_usb_offsets_v3_combo,
+
.serdes_tbl = sm8150_usb3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
.tx_tbl = sm8150_usb3_tx_tbl,
@@ -1758,6 +1829,8 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
.lanes = 1,
+ .offsets = &qmp_usb_offsets_v4,
+
.serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
.tx_tbl = sm8150_usb3_uniphy_tx_tbl,
@@ -1783,6 +1856,8 @@ static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
.lanes = 2,
+ .offsets = &qmp_usb_offsets_v3_combo,
+
.serdes_tbl = sm8150_usb3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
.tx_tbl = sm8250_usb3_tx_tbl,
@@ -1809,6 +1884,8 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
.lanes = 1,
+ .offsets = &qmp_usb_offsets_v4,
+
.serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
.tx_tbl = sm8250_usb3_uniphy_tx_tbl,
@@ -1834,6 +1911,8 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
.lanes = 1,
+ .offsets = &qmp_usb_offsets_v4,
+
.serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
.tx_tbl = sdx55_usb3_uniphy_tx_tbl,
@@ -1859,6 +1938,8 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
.lanes = 1,
+ .offsets = &qmp_usb_offsets_v5,
+
.serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
.tx_tbl = sdx65_usb3_uniphy_tx_tbl,
@@ -1884,6 +1965,8 @@ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
.lanes = 2,
+ .offsets = &qmp_usb_offsets_v3_combo,
+
.serdes_tbl = sm8150_usb3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
.tx_tbl = sm8350_usb3_tx_tbl,
@@ -1910,6 +1993,8 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
.lanes = 1,
+ .offsets = &qmp_usb_offsets_v5,
+
.serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
.tx_tbl = sm8350_usb3_uniphy_tx_tbl,
@@ -1935,6 +2020,8 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
.lanes = 2,
+ .offsets = &qmp_usb_offsets_v3_qcm2290,
+
.serdes_tbl = qcm2290_usb3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
.tx_tbl = qcm2290_usb3_tx_tbl,
@@ -2506,9 +2593,19 @@ static int qmp_usb_parse_dt(struct qmp_usb *qmp)
qmp->serdes = base + offs->serdes;
qmp->pcs = base + offs->pcs;
- qmp->pcs_usb = base + offs->pcs_usb;
+ if (offs->pcs_usb)
+ qmp->pcs_usb = base + offs->pcs_usb;
+ if (offs->pcs_misc)
+ qmp->pcs_misc = base + offs->pcs_misc;
qmp->tx = base + offs->tx;
qmp->rx = base + offs->rx;
+ if (cfg->has_phy_dp_com_ctrl)
+ qmp->dp_com = base + offs->dp_com;
+
+ if (cfg->lanes >= 2) {
+ qmp->tx2 = base + offs->tx2;
+ qmp->rx2 = base + offs->rx2;
+ }
qmp->pipe_clk = devm_clk_get(dev, "pipe");
if (IS_ERR(qmp->pipe_clk)) {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 08/41] phy: qcom-qmp-ufs: populate offsets configuration
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (6 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 07/41] phy: qcom-qmp-usb: populate offsets configuration Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 09/41] phy: qcom-qmp-pcie: " Dmitry Baryshkov
` (32 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Populate offsets configuration for the rest of UFS PHYs to make it
possible to switch them to the new (single-node) bindings style.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 994ddd5d4a81..55f7b3b74501 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -803,6 +803,8 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
.lanes = 1,
+ .offsets = &qmp_ufs_offsets,
+
.tbls = {
.serdes = msm8996_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
@@ -860,6 +862,8 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.lanes = 2,
+ .offsets = &qmp_ufs_offsets,
+
.tbls = {
.serdes = sdm845_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
@@ -946,6 +950,8 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
.lanes = 2,
+ .offsets = &qmp_ufs_offsets,
+
.tbls = {
.serdes = sm8150_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
@@ -978,6 +984,8 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.lanes = 2,
+ .offsets = &qmp_ufs_offsets,
+
.tbls = {
.serdes = sm8350_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
@@ -1010,6 +1018,8 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.lanes = 2,
+ .offsets = &qmp_ufs_offsets,
+
.tbls = {
.serdes = sm8350_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 09/41] phy: qcom-qmp-pcie: populate offsets configuration
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (7 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 08/41] phy: qcom-qmp-ufs: " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 10/41] arm64: dts: qcom: ipq6018: switch USB QMP PHY to new style of bindings Dmitry Baryshkov
` (31 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Populate offsets configuration for the rest of UFS PHYs to make it
possible to switch them to the new (single-node) bindings style.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 84 ++++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index c95bf7ec2abe..ac60da8e0b88 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1939,6 +1939,56 @@ static const char * const sdm845_pciephy_reset_l[] = {
"phy",
};
+static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = {
+ .serdes = 0,
+ .pcs = 0x1800,
+ .tx = 0x0800,
+ /* no .rx for QHP */
+};
+
+static const struct qmp_pcie_offsets qmp_pcie_offsets_v2 = {
+ .serdes = 0,
+ .pcs = 0x0800,
+ .tx = 0x0200,
+ .rx = 0x0400,
+};
+
+static const struct qmp_pcie_offsets qmp_pcie_offsets_v3 = {
+ .serdes = 0,
+ .pcs = 0x0800,
+ .pcs_misc = 0x0600,
+ .tx = 0x0200,
+ .rx = 0x0400,
+};
+
+static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = {
+ .serdes = 0,
+ .pcs = 0x0800,
+ .pcs_misc = 0x0c00,
+ .tx = 0x0200,
+ .rx = 0x0400,
+};
+
+static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = {
+ .serdes = 0,
+ .pcs = 0x0a00,
+ .pcs_misc = 0x0e00,
+ .tx = 0x0200,
+ .rx = 0x0400,
+ .tx2 = 0x0600,
+ .rx2 = 0x0800,
+};
+
+static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = {
+ .serdes = 0x1000,
+ .pcs = 0x1200,
+ .pcs_misc = 0x1600,
+ .tx = 0x0000,
+ .rx = 0x0200,
+ .tx2 = 0x0800,
+ .rx2 = 0x0a00,
+};
+
static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = {
.serdes = 0,
.pcs = 0x0200,
@@ -1949,6 +1999,16 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = {
.rx2 = 0x1800,
};
+static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = {
+ .serdes = 0x1000,
+ .pcs = 0x1200,
+ .pcs_misc = 0x1400,
+ .tx = 0x0000,
+ .rx = 0x0200,
+ .tx2 = 0x0800,
+ .rx2 = 0x0a00,
+};
+
static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {
.serdes = 0x1000,
.pcs = 0x1200,
@@ -1963,6 +2023,8 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {
static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
.lanes = 1,
+ .offsets = &qmp_pcie_offsets_v2,
+
.tbls = {
.serdes = ipq8074_pcie_serdes_tbl,
.serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
@@ -1988,6 +2050,8 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
.lanes = 1,
+ .offsets = &qmp_pcie_offsets_v4x1,
+
.tbls = {
.serdes = ipq8074_pcie_gen3_serdes_tbl,
.serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
@@ -2017,6 +2081,8 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
.lanes = 1,
+ .offsets = &qmp_pcie_offsets_v4x1,
+
.tbls = {
.serdes = ipq6018_pcie_serdes_tbl,
.serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
@@ -2044,6 +2110,8 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
.lanes = 1,
+ .offsets = &qmp_pcie_offsets_v3,
+
.tbls = {
.serdes = sdm845_qmp_pcie_serdes_tbl,
.serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
@@ -2071,6 +2139,8 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
.lanes = 1,
+ .offsets = &qmp_pcie_offsets_qhp,
+
.tbls = {
.serdes = sdm845_qhp_pcie_serdes_tbl,
.serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
@@ -2094,6 +2164,8 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
.lanes = 1,
+ .offsets = &qmp_pcie_offsets_v4x1,
+
.tbls = {
.serdes = sm8250_qmp_pcie_serdes_tbl,
.serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
@@ -2131,6 +2203,8 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
.lanes = 2,
+ .offsets = &qmp_pcie_offsets_v4x2,
+
.tbls = {
.serdes = sm8250_qmp_pcie_serdes_tbl,
.serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
@@ -2168,6 +2242,8 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
.lanes = 1,
+ .offsets = &qmp_pcie_offsets_v3,
+
.tbls = {
.serdes = msm8998_pcie_serdes_tbl,
.serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
@@ -2195,6 +2271,8 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
.lanes = 2,
+ .offsets = &qmp_pcie_offsets_v4x2,
+
.tbls = {
.serdes = sc8180x_qmp_pcie_serdes_tbl,
.serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
@@ -2330,6 +2408,8 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = {
static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
.lanes = 2,
+ .offsets = &qmp_pcie_offsets_v4_20,
+
.tbls = {
.serdes = sdx55_qmp_pcie_serdes_tbl,
.serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
@@ -2446,6 +2526,8 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {
static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
.lanes = 1,
+ .offsets = &qmp_pcie_offsets_v5,
+
.tbls = {
.serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
@@ -2481,6 +2563,8 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
.lanes = 2,
+ .offsets = &qmp_pcie_offsets_v5_20,
+
.tbls = {
.serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl,
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 10/41] arm64: dts: qcom: ipq6018: switch USB QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (8 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 09/41] phy: qcom-qmp-pcie: " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 11/41] arm64: dts: qcom: ipq8074: " Dmitry Baryshkov
` (30 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 31 +++++++++++----------------
1 file changed, 12 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 9ff4e9d45065..ff540bfcc062 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -220,31 +220,24 @@ qusb_phy_1: qusb@59000 {
ssphy_0: ssphy@78000 {
compatible = "qcom,ipq6018-qmp-usb3-phy";
- reg = <0x0 0x00078000 0x0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0x0 0x00078000 0x0 0x1000>;
clocks = <&gcc GCC_USB0_AUX_CLK>,
- <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo>,
+ <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "pipe";
+ clock-output-names = "gcc_usb0_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB0_PHY_BCR>,
<&gcc GCC_USB3PHY_0_PHY_BCR>;
reset-names = "phy","common";
status = "disabled";
-
- usb0_ssphy: phy@78200 {
- reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
- <0x0 0x00078400 0x0 0x200>, /* Rx */
- <0x0 0x00078800 0x0 0x1f8>, /* PCS */
- <0x0 0x00078600 0x0 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "gcc_usb0_pipe_clk_src";
- };
};
qusb_phy_0: qusb@79000 {
@@ -553,7 +546,7 @@ dwc_0: usb@8a00000 {
compatible = "snps,dwc3";
reg = <0x0 0x08a00000 0x0 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_0>, <&usb0_ssphy>;
+ phys = <&qusb_phy_0>, <&ssphy_0>;
phy-names = "usb2-phy", "usb3-phy";
clocks = <&xo>;
clock-names = "ref";
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 11/41] arm64: dts: qcom: ipq8074: switch USB QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (9 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 10/41] arm64: dts: qcom: ipq6018: switch USB QMP PHY to new style of bindings Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 12/41] arm64: dts: qcom: msm8996: " Dmitry Baryshkov
` (29 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 60 ++++++++++-----------------
1 file changed, 22 insertions(+), 38 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index fe37dcdc52c8..e7ac3f886611 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -113,32 +113,24 @@ soc: soc {
ssphy_1: phy@58000 {
compatible = "qcom,ipq8074-qmp-usb3-phy";
- reg = <0x00058000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x00058000 0x1000>;
clocks = <&gcc GCC_USB1_AUX_CLK>,
<&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
- <&xo>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&xo>,
+ <&gcc GCC_USB1_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "pipe";
+ clock-output-names = "usb3phy_1_cc_pipe_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB1_PHY_BCR>,
<&gcc GCC_USB3PHY_1_PHY_BCR>;
reset-names = "phy","common";
status = "disabled";
-
- usb1_ssphy: phy@58200 {
- reg = <0x00058200 0x130>, /* Tx */
- <0x00058400 0x200>, /* Rx */
- <0x00058800 0x1f8>, /* PCS */
- <0x00058600 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB1_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3phy_1_cc_pipe_clk";
- };
};
qusb_phy_1: phy@59000 {
@@ -156,32 +148,24 @@ qusb_phy_1: phy@59000 {
ssphy_0: phy@78000 {
compatible = "qcom,ipq8074-qmp-usb3-phy";
- reg = <0x00078000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x00078000 0x1000>;
clocks = <&gcc GCC_USB0_AUX_CLK>,
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
- <&xo>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&xo>,
+ <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "pipe";
+ clock-output-names = "usb3phy_0_cc_pipe_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB0_PHY_BCR>,
<&gcc GCC_USB3PHY_0_PHY_BCR>;
reset-names = "phy","common";
status = "disabled";
-
- usb0_ssphy: phy@78200 {
- reg = <0x00078200 0x130>, /* Tx */
- <0x00078400 0x200>, /* Rx */
- <0x00078800 0x1f8>, /* PCS */
- <0x00078600 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3phy_0_cc_pipe_clk";
- };
};
qusb_phy_0: phy@79000 {
@@ -609,7 +593,7 @@ dwc_0: usb@8a00000 {
compatible = "snps,dwc3";
reg = <0x8a00000 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_0>, <&usb0_ssphy>;
+ phys = <&qusb_phy_0>, <&ssphy_0>;
phy-names = "usb2-phy", "usb3-phy";
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
@@ -651,7 +635,7 @@ dwc_1: usb@8c00000 {
compatible = "snps,dwc3";
reg = <0x8c00000 0xcd00>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_1>, <&usb1_ssphy>;
+ phys = <&qusb_phy_1>, <&ssphy_1>;
phy-names = "usb2-phy", "usb3-phy";
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 12/41] arm64: dts: qcom: msm8996: switch USB QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (10 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 11/41] arm64: dts: qcom: ipq8074: " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 13/41] arm64: dts: qcom: msm8998: " Dmitry Baryshkov
` (28 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 32 ++++++++++-----------------
1 file changed, 12 insertions(+), 20 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 4661a556772e..a811095fe93a 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -725,7 +725,7 @@ gcc: clock-controller@300000 {
<&pciephy_0>,
<&pciephy_1>,
<&pciephy_2>,
- <&ssusb_phy_0>,
+ <&usb3phy>,
<&ufsphy_lane 0>,
<&ufsphy_lane 1>,
<&ufsphy_lane 2>;
@@ -3003,7 +3003,7 @@ usb3_dwc3: usb@6a00000 {
compatible = "snps,dwc3";
reg = <0x06a00000 0xcc00>;
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&hsusb_phy1>, <&ssusb_phy_0>;
+ phys = <&hsusb_phy1>, <&usb3phy>;
phy-names = "usb2-phy", "usb3-phy";
snps,hird-threshold = /bits/ 8 <0>;
snps,dis_u2_susphy_quirk;
@@ -3015,32 +3015,24 @@ usb3_dwc3: usb@6a00000 {
usb3phy: phy@7410000 {
compatible = "qcom,msm8996-qmp-usb3-phy";
- reg = <0x07410000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x07410000 0x1000>;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_CLKREF_CLK>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&gcc GCC_USB3_CLKREF_CLK>,
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "pipe";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy", "common";
status = "disabled";
-
- ssusb_phy_0: phy@7410200 {
- reg = <0x07410200 0x200>,
- <0x07410400 0x130>,
- <0x07410600 0x1a8>;
- #phy-cells = <0>;
-
- #clock-cells = <0>;
- clock-output-names = "usb3_phy_pipe_clk_src";
- clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- };
};
hsusb_phy1: phy@7411000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 13/41] arm64: dts: qcom: msm8998: switch USB QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (11 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 12/41] arm64: dts: qcom: msm8996: " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 14/41] arm64: dts: qcom: sdm845: " Dmitry Baryshkov
` (27 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 31 ++++++++++-----------------
1 file changed, 11 insertions(+), 20 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 09b222f363c2..2ccf28d8e223 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -2032,7 +2032,7 @@ usb3_dwc3: usb@a800000 {
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&qusb2phy>, <&usb1_ssphy>;
+ phys = <&qusb2phy>, <&usb3phy>;
phy-names = "usb2-phy", "usb3-phy";
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
@@ -2041,33 +2041,24 @@ usb3_dwc3: usb@a800000 {
usb3phy: phy@c010000 {
compatible = "qcom,msm8998-qmp-usb3-phy";
- reg = <0x0c010000 0x18c>;
+ reg = <0x0c010000 0x1000>;
status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_CLKREF_CLK>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&gcc GCC_USB3_CLKREF_CLK>,
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "pipe";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy", "common";
-
- usb1_ssphy: phy@c010200 {
- reg = <0xc010200 0x128>,
- <0xc010400 0x200>,
- <0xc010c00 0x20c>,
- <0xc010600 0x128>,
- <0xc010800 0x200>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
- };
};
qusb2phy: phy@c012000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 14/41] arm64: dts: qcom: sdm845: switch USB QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (12 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 13/41] arm64: dts: qcom: msm8998: " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 15/41] arm64: dts: qcom: sm8150: " Dmitry Baryshkov
` (26 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 31 +++++++++++-----------------
1 file changed, 12 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2f32179c7d1b..10c53756a903 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -3956,33 +3956,26 @@ dp_phy: dp-phy@88ea200 {
usb_2_qmpphy: phy@88eb000 {
compatible = "qcom,sdm845-qmp-usb3-uni-phy";
- reg = <0 0x088eb000 0 0x18c>;
+ reg = <0 0x088eb000 0 0x1000>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "com_aux",
+ "pipe";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
-
- usb_2_ssphy: phy@88eb200 {
- reg = <0 0x088eb200 0 0x128>,
- <0 0x088eb400 0 0x1fc>,
- <0 0x088eb800 0 0x218>,
- <0 0x088eb600 0 0x70>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
};
usb_1: usb@a6f8800 {
@@ -4082,7 +4075,7 @@ usb_2_dwc3: usb@a800000 {
iommus = <&apps_smmu 0x760 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
+ phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 15/41] arm64: dts: qcom: sm8150: switch USB QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (13 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 14/41] arm64: dts: qcom: sdm845: " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 16/41] arm64: dts: qcom: sm8250: " Dmitry Baryshkov
` (25 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 67 +++++++++++-----------------
1 file changed, 25 insertions(+), 42 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 9491be4a6bf0..c29bbd5c6fd5 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3391,69 +3391,52 @@ usb_2_hsphy: phy@88e3000 {
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
};
- usb_1_qmpphy: phy@88e9000 {
+ usb_1_qmpphy: phy@88e8000 {
compatible = "qcom,sm8150-qmp-usb3-phy";
- reg = <0 0x088e9000 0 0x18c>,
- <0 0x088e8000 0 0x10>;
+ reg = <0 0x088e8000 0 0x3000>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
- clock-names = "aux", "ref_clk_src", "ref", "com_aux";
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref_clk_src",
+ "ref",
+ "com_aux",
+ "pipe";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
-
- usb_1_ssphy: phy@88e9200 {
- reg = <0 0x088e9200 0 0x200>,
- <0 0x088e9400 0 0x200>,
- <0 0x088e9c00 0 0x218>,
- <0 0x088e9600 0 0x200>,
- <0 0x088e9800 0 0x200>,
- <0 0x088e9a00 0 0x100>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
- };
};
usb_2_qmpphy: phy@88eb000 {
compatible = "qcom,sm8150-qmp-usb3-uni-phy";
- reg = <0 0x088eb000 0 0x200>;
+ reg = <0 0x088eb000 0 0x1000>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
- clock-names = "aux", "ref_clk_src", "ref", "com_aux";
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref_clk_src",
+ "ref",
+ "com_aux",
+ "pipe";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
-
- usb_2_ssphy: phy@88eb200 {
- reg = <0 0x088eb200 0 0x200>,
- <0 0x088eb400 0 0x200>,
- <0 0x088eb800 0 0x800>,
- <0 0x088eb600 0 0x200>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
};
sdhc_2: mmc@8804000 {
@@ -3559,7 +3542,7 @@ usb_1_dwc3: usb@a600000 {
iommus = <&apps_smmu 0x140 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+ phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
@@ -3608,7 +3591,7 @@ usb_2_dwc3: usb@a800000 {
iommus = <&apps_smmu 0x160 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
+ phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 16/41] arm64: dts: qcom: sm8250: switch USB QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (14 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 15/41] arm64: dts: qcom: sm8150: " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 17/41] arm64: dts: qcom: sm8350: " Dmitry Baryshkov
` (24 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 30 +++++++++++-----------------
1 file changed, 12 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 7b78761f2041..0b9ca147c1b4 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3573,32 +3573,26 @@ dp_phy: dp-phy@88ea200 {
usb_2_qmpphy: phy@88eb000 {
compatible = "qcom,sm8250-qmp-usb3-uni-phy";
- reg = <0 0x088eb000 0 0x200>;
+ reg = <0 0x088eb000 0 0x1000>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_EN>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
- clock-names = "aux", "ref_clk_src", "ref", "com_aux";
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref_clk_src",
+ "ref",
+ "com_aux",
+ "pipe";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
-
- usb_2_ssphy: phy@88eb200 {
- reg = <0 0x088eb200 0 0x200>,
- <0 0x088eb400 0 0x200>,
- <0 0x088eb800 0 0x800>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
};
sdhc_2: mmc@8804000 {
@@ -3773,7 +3767,7 @@ usb_2_dwc3: usb@a800000 {
iommus = <&apps_smmu 0x20 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
+ phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 17/41] arm64: dts: qcom: sm8350: switch USB QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (15 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 16/41] arm64: dts: qcom: sm8250: " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 18/41] arm64: dts: qcom: sc7180: switch USB+DP " Dmitry Baryshkov
` (23 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 32 +++++++++++-----------------
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 0dc50170db7b..da764ca42129 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2155,34 +2155,28 @@ usb_1_qmpphy: phy@88e9000 {
status = "disabled";
};
- usb_2_qmpphy: phy-wrapper@88eb000 {
+ usb_2_qmpphy: phy@88eb000 {
compatible = "qcom,sm8350-qmp-usb3-uni-phy";
- reg = <0 0x088eb000 0 0x200>;
+ reg = <0 0x088eb000 0 0x2000>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_EN>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
- clock-names = "aux", "ref_clk_src", "ref", "com_aux";
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref_clk_src",
+ "ref",
+ "com_aux",
+ "pipe";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
-
- usb_2_ssphy: phy@88ebe00 {
- reg = <0 0x088ebe00 0 0x200>,
- <0 0x088ec000 0 0x200>,
- <0 0x088eb200 0 0x1100>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
};
dc_noc: interconnect@90c0000 {
@@ -2327,7 +2321,7 @@ usb_2_dwc3: usb@a800000 {
iommus = <&apps_smmu 0x20 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
+ phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 18/41] arm64: dts: qcom: sc7180: switch USB+DP QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (16 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 17/41] arm64: dts: qcom: sm8350: " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 19/41] arm64: dts: qcom: sc7280: " Dmitry Baryshkov
` (22 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 55 +++++++++-------------------
1 file changed, 18 insertions(+), 37 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 3c799b564b64..369868f613bf 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -14,6 +14,7 @@
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc7180.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
@@ -2713,49 +2714,28 @@ usb_1_hsphy: phy@88e3000 {
nvmem-cells = <&qusb2p_hstx_trim>;
};
- usb_1_qmpphy: phy-wrapper@88e9000 {
+ usb_1_qmpphy: phy@88e8000 {
compatible = "qcom,sc7180-qmp-usb3-dp-phy";
- reg = <0 0x088e9000 0 0x18c>,
- <0 0x088e8000 0 0x3c>,
- <0 0x088ea000 0 0x18c>;
+ reg = <0 0x088e8000 0 0x3000>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common";
- usb_1_ssphy: usb3-phy@88e9200 {
- reg = <0 0x088e9200 0 0x128>,
- <0 0x088e9400 0 0x200>,
- <0 0x088e9c00 0 0x218>,
- <0 0x088e9600 0 0x128>,
- <0 0x088e9800 0 0x200>,
- <0 0x088e9a00 0 0x18>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
- };
-
- dp_phy: dp-phy@88ea200 {
- reg = <0 0x088ea200 0 0x200>,
- <0 0x088ea400 0 0x200>,
- <0 0x088eaa00 0 0x200>,
- <0 0x088ea600 0 0x200>,
- <0 0x088ea800 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
+ #clock-cells = <1>;
+ #phy-cells = <1>;
};
dc_noc: interconnect@9160000 {
@@ -2835,7 +2815,7 @@ usb_1_dwc3: usb@a600000 {
iommus = <&apps_smmu 0x540 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
};
@@ -3143,8 +3123,9 @@ mdss_dp: displayport-controller@ae90000 {
"ctrl_link_iface", "stream_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
- assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
- phys = <&dp_phy>;
+ assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+ phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
operating-points-v2 = <&dp_opp_table>;
@@ -3201,8 +3182,8 @@ dispcc: clock-controller@af00000 {
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&dsi_phy 0>,
<&dsi_phy 1>,
- <&dp_phy 0>,
- <&dp_phy 1>;
+ <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
clock-names = "bi_tcxo",
"gcc_disp_gpll0_clk_src",
"dsi0_phy_pll_out_byteclk",
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 19/41] arm64: dts: qcom: sc7280: switch USB+DP QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (17 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 18/41] arm64: dts: qcom: sc7180: switch USB+DP " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 20/41] arm64: dts: qcom: sdm845: " Dmitry Baryshkov
` (21 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 54 +++++++++-------------------
1 file changed, 17 insertions(+), 37 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 5e6f9f441f1a..62885ac3f11e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -18,6 +18,7 @@
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
@@ -3327,49 +3328,27 @@ usb_2_hsphy: phy@88e4000 {
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
};
- usb_1_qmpphy: phy-wrapper@88e9000 {
+ usb_1_qmpphy: phy@88e8000 {
compatible = "qcom,sc7280-qmp-usb3-dp-phy",
"qcom,sm8250-qmp-usb3-dp-phy";
- reg = <0 0x088e9000 0 0x200>,
- <0 0x088e8000 0 0x40>,
- <0 0x088ea000 0 0x200>;
+ reg = <0 0x088e8000 0 0x3000>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
- clock-names = "aux", "ref_clk_src", "com_aux";
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref_clk_src",
+ "com_aux",
+ "usb3_pipe";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
- usb_1_ssphy: usb3-phy@88e9200 {
- reg = <0 0x088e9200 0 0x200>,
- <0 0x088e9400 0 0x200>,
- <0 0x088e9c00 0 0x400>,
- <0 0x088e9600 0 0x200>,
- <0 0x088e9800 0 0x200>,
- <0 0x088e9a00 0 0x100>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
- };
-
- dp_phy: dp-phy@88ea200 {
- reg = <0 0x088ea200 0 0x200>,
- <0 0x088ea400 0 0x200>,
- <0 0x088eaa00 0 0x200>,
- <0 0x088ea600 0 0x200>,
- <0 0x088ea800 0 0x200>;
- #phy-cells = <0>;
- #clock-cells = <1>;
- };
+ #clock-cells = <1>;
+ #phy-cells = <1>;
};
usb_2: usb@8cf8800 {
@@ -3694,7 +3673,7 @@ usb_1_dwc3: usb@a600000 {
iommus = <&apps_smmu 0xe0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
};
@@ -3799,8 +3778,8 @@ dispcc: clock-controller@af00000 {
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&mdss_dsi_phy 0>,
<&mdss_dsi_phy 1>,
- <&dp_phy 0>,
- <&dp_phy 1>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&mdss_edp_phy 0>,
<&mdss_edp_phy 1>;
clock-names = "bi_tcxo",
@@ -4138,8 +4117,9 @@ mdss_dp: displayport-controller@ae90000 {
"stream_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
- assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
- phys = <&dp_phy>;
+ assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+ phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
operating-points-v2 = <&dp_opp_table>;
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 20/41] arm64: dts: qcom: sdm845: switch USB+DP QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (18 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 19/41] arm64: dts: qcom: sc7280: " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 21/41] arm64: dts: qcom: sm8250: " Dmitry Baryshkov
` (20 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 55 +++++++++-------------------
1 file changed, 18 insertions(+), 37 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 10c53756a903..062790ef7bc9 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -17,6 +17,7 @@
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
@@ -3909,49 +3910,28 @@ usb_2_hsphy: phy@88e3000 {
nvmem-cells = <&qusb2s_hstx_trim>;
};
- usb_1_qmpphy: phy@88e9000 {
+ usb_1_qmpphy: phy@88e8000 {
compatible = "qcom,sdm845-qmp-usb3-dp-phy";
- reg = <0 0x088e9000 0 0x18c>,
- <0 0x088e8000 0 0x38>,
- <0 0x088ea000 0 0x40>;
+ reg = <0 0x088e8000 0 0x3000>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common";
- usb_1_ssphy: usb3-phy@88e9200 {
- reg = <0 0x088e9200 0 0x128>,
- <0 0x088e9400 0 0x200>,
- <0 0x088e9c00 0 0x218>,
- <0 0x088e9600 0 0x128>,
- <0 0x088e9800 0 0x200>,
- <0 0x088e9a00 0 0x100>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
- };
-
- dp_phy: dp-phy@88ea200 {
- reg = <0 0x088ea200 0 0x200>,
- <0 0x088ea400 0 0x200>,
- <0 0x088eaa00 0 0x200>,
- <0 0x088ea600 0 0x200>,
- <0 0x088ea800 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
+ #clock-cells = <1>;
+ #phy-cells = <1>;
};
usb_2_qmpphy: phy@88eb000 {
@@ -4024,7 +4004,7 @@ usb_1_dwc3: usb@a600000 {
iommus = <&apps_smmu 0x740 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
};
};
@@ -4492,8 +4472,9 @@ mdss_dp: displayport-controller@ae90000 {
"ctrl_link_iface", "stream_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
- assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
- phys = <&dp_phy>;
+ assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+ phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
operating-points-v2 = <&dp_opp_table>;
@@ -4831,8 +4812,8 @@ dispcc: clock-controller@af00000 {
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
- <&dp_phy 0>,
- <&dp_phy 1>;
+ <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
clock-names = "bi_tcxo",
"gcc_disp_gpll0_clk_src",
"gcc_disp_gpll0_div_clk_src",
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 21/41] arm64: dts: qcom: sm8250: switch USB+DP QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (19 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 20/41] arm64: dts: qcom: sdm845: " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 22/41] arm64: dts: qcom: msm8996: switch UFS " Dmitry Baryshkov
` (19 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 49 ++++++++--------------------
1 file changed, 14 insertions(+), 35 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 0b9ca147c1b4..e7b1c9fc13c5 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -3527,48 +3528,26 @@ usb_2_hsphy: phy@88e4000 {
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
};
- usb_1_qmpphy: phy@88e9000 {
+ usb_1_qmpphy: phy@88e8000 {
compatible = "qcom,sm8250-qmp-usb3-dp-phy";
- reg = <0 0x088e9000 0 0x200>,
- <0 0x088e8000 0 0x40>,
- <0 0x088ea000 0 0x200>;
+ reg = <0 0x088e8000 0 0x3000>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
- clock-names = "aux", "ref_clk_src", "com_aux";
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref_clk_src",
+ "com_aux",
+ "usb3_pipe";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
- usb_1_ssphy: usb3-phy@88e9200 {
- reg = <0 0x088e9200 0 0x200>,
- <0 0x088e9400 0 0x200>,
- <0 0x088e9c00 0 0x400>,
- <0 0x088e9600 0 0x200>,
- <0 0x088e9800 0 0x200>,
- <0 0x088e9a00 0 0x100>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
- };
-
- dp_phy: dp-phy@88ea200 {
- reg = <0 0x088ea200 0 0x200>,
- <0 0x088ea400 0 0x200>,
- <0 0x088eaa00 0 0x200>,
- <0 0x088ea600 0 0x200>,
- <0 0x088ea800 0 0x200>;
- #phy-cells = <0>;
- #clock-cells = <1>;
- };
+ #clock-cells = <1>;
+ #phy-cells = <1>;
};
usb_2_qmpphy: phy@88eb000 {
@@ -3707,7 +3686,7 @@ usb_1_dwc3: usb@a600000 {
iommus = <&apps_smmu 0x0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
};
};
@@ -4397,8 +4376,8 @@ dispcc: clock-controller@af00000 {
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
- <&dp_phy 0>,
- <&dp_phy 1>;
+ <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
clock-names = "bi_tcxo",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 22/41] arm64: dts: qcom: msm8996: switch UFS QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (20 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 21/41] arm64: dts: qcom: sm8250: " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 23/41] arm64: dts: qcom: msm8998: " Dmitry Baryshkov
` (18 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 25 +++++++++----------------
1 file changed, 9 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index a811095fe93a..11e8d5287e6f 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -726,9 +726,9 @@ gcc: clock-controller@300000 {
<&pciephy_1>,
<&pciephy_2>,
<&usb3phy>,
- <&ufsphy_lane 0>,
- <&ufsphy_lane 1>,
- <&ufsphy_lane 2>;
+ <&ufsphy 0>,
+ <&ufsphy 1>,
+ <&ufsphy 2>;
clock-names = "cxo",
"cxo2",
"sleep_clk",
@@ -1994,7 +1994,7 @@ ufshc: ufshc@624000 {
reg = <0x00624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufsphy_lane>;
+ phys = <&ufsphy>;
phy-names = "ufsphy";
power-domains = <&gcc UFS_GDSC>;
@@ -2047,25 +2047,18 @@ ufshc: ufshc@624000 {
ufsphy: phy@627000 {
compatible = "qcom,msm8996-qmp-ufs-phy";
- reg = <0x00627000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x00627000 0x1000>;
clocks = <&gcc GCC_UFS_CLKREF_CLK>;
clock-names = "ref";
resets = <&ufshc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufsphy_lane: phy@627400 {
- reg = <0x627400 0x12c>,
- <0x627600 0x200>,
- <0x627c00 0x1b4>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
};
camss: camss@a00000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 23/41] arm64: dts: qcom: msm8998: switch UFS QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (21 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 22/41] arm64: dts: qcom: msm8996: switch UFS " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 24/41] arm64: dts: qcom: sdm845: " Dmitry Baryshkov
` (17 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 16 +++-------------
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 2ccf28d8e223..11e7d5b6f6d6 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -980,7 +980,7 @@ ufshc: ufshc@1da4000 {
compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x01da4000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufsphy_lanes>;
+ phys = <&ufsphy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
power-domains = <&gcc UFS_GDSC>;
@@ -1021,11 +1021,8 @@ ufshc: ufshc@1da4000 {
ufsphy: phy@1da7000 {
compatible = "qcom,msm8998-qmp-ufs-phy";
- reg = <0x01da7000 0x18c>;
- #address-cells = <1>;
- #size-cells = <1>;
+ reg = <0x01da7000 0x1000>;
status = "disabled";
- ranges;
clock-names =
"ref",
@@ -1037,14 +1034,7 @@ ufsphy: phy@1da7000 {
reset-names = "ufsphy";
resets = <&ufshc 0>;
- ufsphy_lanes: phy@1da7400 {
- reg = <0x01da7400 0x128>,
- <0x01da7600 0x1fc>,
- <0x01da7c00 0x1dc>,
- <0x01da7800 0x128>,
- <0x01da7a00 0x1fc>;
- #phy-cells = <0>;
- };
+ #phy-cells = <0>;
};
tcsr_mutex: hwlock@1f40000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 24/41] arm64: dts: qcom: sdm845: switch UFS QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (22 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 23/41] arm64: dts: qcom: msm8998: " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 25/41] arm64: dts: qcom: sm6115: " Dmitry Baryshkov
` (16 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 17 ++++-------------
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 062790ef7bc9..6eb82c5641cd 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2559,7 +2559,7 @@ ufs_mem_hc: ufshc@1d84000 {
<0 0x01d90000 0 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
power-domains = <&gcc UFS_PHY_GDSC>;
@@ -2605,10 +2605,8 @@ ufs_mem_hc: ufshc@1d84000 {
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sdm845-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x18c>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01d87000 0 0x1000>;
+
clock-names = "ref",
"ref_aux";
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
@@ -2618,14 +2616,7 @@ ufs_mem_phy: phy@1d87000 {
reset-names = "ufsphy";
status = "disabled";
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x108>,
- <0 0x01d87600 0 0x1e0>,
- <0 0x01d87c00 0 0x1dc>,
- <0 0x01d87800 0 0x108>,
- <0 0x01d87a00 0 0x1e0>;
- #phy-cells = <0>;
- };
+ #phy-cells = <0>;
};
cryptobam: dma-controller@1dc4000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 25/41] arm64: dts: qcom: sm6115: switch UFS QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (23 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 24/41] arm64: dts: qcom: sdm845: " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:24 ` [PATCH 26/41] arm64: dts: qcom: sm6350: " Dmitry Baryshkov
` (15 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 17 +++++------------
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 2a51c938bbcb..eb30e5cb7b4b 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -773,7 +773,7 @@ ufs_mem_hc: ufs@4804000 {
reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <1>;
#reset-cells = <1>;
@@ -814,24 +814,17 @@ ufs_mem_hc: ufs@4804000 {
ufs_mem_phy: phy@4807000 {
compatible = "qcom,sm6115-qmp-ufs-phy";
- reg = <0x0 0x04807000 0x0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0x0 0x04807000 0x0 0x1000>;
clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref", "ref_aux";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@4807400 {
- reg = <0x0 0x04807400 0x0 0x098>,
- <0x0 0x04807600 0x0 0x130>,
- <0x0 0x04807c00 0x0 0x16c>;
- #phy-cells = <0>;
- };
+ #phy-cells = <0>;
+
+ status = "disabled";
};
gpi_dma0: dma-controller@4a00000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 26/41] arm64: dts: qcom: sm6350: switch UFS QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (24 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 25/41] arm64: dts: qcom: sm6115: " Dmitry Baryshkov
@ 2023-03-24 2:24 ` Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 27/41] arm64: dts: qcom: sm8150: " Dmitry Baryshkov
` (14 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 18 ++++--------------
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 18c4616848ce..a816bb212174 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -943,7 +943,7 @@ ufs_mem_hc: ufs@1d84000 {
<0 0x01d90000 0 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -988,10 +988,7 @@ ufs_mem_hc: ufs@1d84000 {
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm6350-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x18c>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01d87000 0 0x1000>;
clock-names = "ref",
"ref_aux";
@@ -1001,16 +998,9 @@ ufs_mem_phy: phy@1d87000 {
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
+ #phy-cells = <0>;
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x128>,
- <0 0x01d87600 0 0x1fc>,
- <0 0x01d87c00 0 0x1dc>,
- <0 0x01d87800 0 0x128>,
- <0 0x01d87a00 0 0x1fc>;
- #phy-cells = <0>;
- };
+ status = "disabled";
};
ipa: ipa@1e40000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 27/41] arm64: dts: qcom: sm8150: switch UFS QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (25 preceding siblings ...)
2023-03-24 2:24 ` [PATCH 26/41] arm64: dts: qcom: sm6350: " Dmitry Baryshkov
@ 2023-03-24 2:25 ` Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 28/41] arm64: dts: qcom: sm8250: " Dmitry Baryshkov
` (13 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 20 ++++++--------------
1 file changed, 6 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index c29bbd5c6fd5..be10b68893e8 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -2011,7 +2011,7 @@ ufs_mem_hc: ufshc@1d84000 {
<0 0x01d90000 0 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -2056,10 +2056,8 @@ ufs_mem_hc: ufshc@1d84000 {
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm8150-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01d87000 0 0x1000>;
+
clock-names = "ref",
"ref_aux";
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
@@ -2069,16 +2067,10 @@ ufs_mem_phy: phy@1d87000 {
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x16c>,
- <0 0x01d87600 0 0x200>,
- <0 0x01d87c00 0 0x200>,
- <0 0x01d87800 0 0x16c>,
- <0 0x01d87a00 0 0x200>;
- #phy-cells = <0>;
- };
+ #phy-cells = <0>;
+
+ status = "disabled";
};
tcsr_mutex: hwlock@1f40000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 28/41] arm64: dts: qcom: sm8250: switch UFS QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (26 preceding siblings ...)
2023-03-24 2:25 ` [PATCH 27/41] arm64: dts: qcom: sm8150: " Dmitry Baryshkov
@ 2023-03-24 2:25 ` Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 29/41] arm64: dts: qcom: sm8350: " Dmitry Baryshkov
` (12 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 20 ++++++--------------
1 file changed, 6 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index e7b1c9fc13c5..1d13864e978a 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2156,7 +2156,7 @@ ufs_mem_hc: ufshc@1d84000 {
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -2200,10 +2200,8 @@ ufs_mem_hc: ufshc@1d84000 {
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm8250-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01d87000 0 0x1000>;
+
clock-names = "ref",
"ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
@@ -2211,16 +2209,10 @@ ufs_mem_phy: phy@1d87000 {
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x16c>,
- <0 0x01d87600 0 0x200>,
- <0 0x01d87c00 0 0x200>,
- <0 0x01d87800 0 0x16c>,
- <0 0x01d87a00 0 0x200>;
- #phy-cells = <0>;
- };
+ #phy-cells = <0>;
+
+ status = "disabled";
};
tcsr_mutex: hwlock@1f40000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 29/41] arm64: dts: qcom: sm8350: switch UFS QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (27 preceding siblings ...)
2023-03-24 2:25 ` [PATCH 28/41] arm64: dts: qcom: sm8250: " Dmitry Baryshkov
@ 2023-03-24 2:25 ` Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 30/41] arm64: dts: qcom: sm8450: " Dmitry Baryshkov
` (11 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++++++++++------------------
1 file changed, 10 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index da764ca42129..9f6f11479777 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -658,9 +658,9 @@ gcc: clock-controller@100000 {
<0>,
<0>,
<0>,
- <&ufs_mem_phy_lanes 0>,
- <&ufs_mem_phy_lanes 1>,
- <&ufs_mem_phy_lanes 2>,
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>,
<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
<0>;
};
@@ -1662,7 +1662,7 @@ ufs_mem_hc: ufshc@1d84000 {
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -1706,10 +1706,8 @@ ufs_mem_hc: ufshc@1d84000 {
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm8350-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01d87000 0 0x1000>;
+
clock-names = "ref",
"ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
@@ -1717,17 +1715,11 @@ ufs_mem_phy: phy@1d87000 {
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x188>,
- <0 0x01d87600 0 0x200>,
- <0 0x01d87c00 0 0x200>,
- <0 0x01d87800 0 0x188>,
- <0 0x01d87a00 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
};
ipa: ipa@1e40000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 30/41] arm64: dts: qcom: sm8450: switch UFS QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (28 preceding siblings ...)
2023-03-24 2:25 ` [PATCH 29/41] arm64: dts: qcom: sm8350: " Dmitry Baryshkov
@ 2023-03-24 2:25 ` Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 31/41] arm64: dts: qcom: ipq6018: switch PCIe " Dmitry Baryshkov
` (10 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the UFS QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 28 ++++++++++------------------
1 file changed, 10 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index db264ceb748b..01fe1108cca2 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -745,9 +745,9 @@ gcc: clock-controller@100000 {
<&pcie0_lane>,
<&pcie1_lane>,
<0>,
- <&ufs_mem_phy_lanes 0>,
- <&ufs_mem_phy_lanes 1>,
- <&ufs_mem_phy_lanes 2>,
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>,
<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
clock-names = "bi_tcxo",
"sleep_clk",
@@ -4075,7 +4075,7 @@ ufs_mem_hc: ufshc@1d84000 {
<0 0x01d88000 0 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -4125,10 +4125,8 @@ ufs_mem_hc: ufshc@1d84000 {
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm8450-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01d87000 0 0x1000>;
+
clock-names = "ref", "ref_aux", "qref";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
@@ -4136,17 +4134,11 @@ ufs_mem_phy: phy@1d87000 {
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x188>,
- <0 0x01d87600 0 0x200>,
- <0 0x01d87c00 0 0x200>,
- <0 0x01d87800 0 0x188>,
- <0 0x01d87a00 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
};
sdhc_2: mmc@8804000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 31/41] arm64: dts: qcom: ipq6018: switch PCIe QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (29 preceding siblings ...)
2023-03-24 2:25 ` [PATCH 30/41] arm64: dts: qcom: sm8450: " Dmitry Baryshkov
@ 2023-03-24 2:25 ` Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 32/41] arm64: dts: qcom: ipq8074: " Dmitry Baryshkov
` (9 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 32 ++++++++++-----------------
1 file changed, 12 insertions(+), 20 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index ff540bfcc062..9a2daab5ff15 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -255,33 +255,25 @@ qusb_phy_0: qusb@79000 {
pcie_phy: phy@84000 {
compatible = "qcom,ipq6018-qmp-pcie-phy";
- reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
+ reg = <0x0 0x00084000 0x0 0x1000>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
clocks = <&gcc GCC_PCIE0_AUX_CLK>,
- <&gcc GCC_PCIE0_AHB_CLK>;
- clock-names = "aux", "cfg_ahb";
+ <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "pipe";
+
+ clock-output-names = "gcc_pcie0_pipe_clk_src";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE0_PHY_BCR>,
<&gcc GCC_PCIE0PHY_PHY_BCR>;
reset-names = "phy",
"common";
-
- pcie_phy0: phy@84200 {
- reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
- <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
- <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
- <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "gcc_pcie0_pipe_clk_src";
- #clock-cells = <0>;
- };
};
mdio: mdio@90000 {
@@ -728,7 +720,7 @@ pcie0: pci@20000000 {
#address-cells = <3>;
#size-cells = <2>;
- phys = <&pcie_phy0>;
+ phys = <&pcie_phy>;
phy-names = "pciephy";
ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 32/41] arm64: dts: qcom: ipq8074: switch PCIe QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (30 preceding siblings ...)
2023-03-24 2:25 ` [PATCH 31/41] arm64: dts: qcom: ipq6018: switch PCIe " Dmitry Baryshkov
@ 2023-03-24 2:25 ` Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 33/41] arm64: dts: qcom: msm8998: " Dmitry Baryshkov
` (8 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 63 +++++++++++----------------
1 file changed, 26 insertions(+), 37 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index e7ac3f886611..cf0d77b55395 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -183,59 +183,48 @@ qusb_phy_0: phy@79000 {
pcie_qmp0: phy@84000 {
compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
- reg = <0x00084000 0x1bc>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x00084000 0x1000>;
clocks = <&gcc GCC_PCIE0_AUX_CLK>,
- <&gcc GCC_PCIE0_AHB_CLK>;
- clock-names = "aux", "cfg_ahb";
+ <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "pipe";
+
+ clock-output-names = "pcie20_phy0_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
+
resets = <&gcc GCC_PCIE0_PHY_BCR>,
<&gcc GCC_PCIE0PHY_PHY_BCR>;
reset-names = "phy",
"common";
status = "disabled";
-
- pcie_phy0: phy@84200 {
- reg = <0x84200 0x16c>,
- <0x84400 0x200>,
- <0x84800 0x1f0>,
- <0x84c00 0xf4>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "pcie20_phy0_pipe_clk";
- };
};
pcie_qmp1: phy@8e000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
- reg = <0x0008e000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x0008e000 0x1000>;
clocks = <&gcc GCC_PCIE1_AUX_CLK>,
- <&gcc GCC_PCIE1_AHB_CLK>;
- clock-names = "aux", "cfg_ahb";
+ <&gcc GCC_PCIE1_AHB_CLK>,
+ <&gcc GCC_PCIE1_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "pipe";
+
+ clock-output-names = "pcie20_phy1_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
+
resets = <&gcc GCC_PCIE1_PHY_BCR>,
<&gcc GCC_PCIE1PHY_PHY_BCR>;
reset-names = "phy",
"common";
status = "disabled";
-
- pcie_phy1: phy@8e200 {
- reg = <0x8e200 0x130>,
- <0x8e400 0x200>,
- <0x8e800 0x1f8>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "pcie20_phy1_pipe_clk";
- };
};
mdio: mdio@90000 {
@@ -760,7 +749,7 @@ pcie1: pci@10000000 {
#address-cells = <3>;
#size-cells = <2>;
- phys = <&pcie_phy1>;
+ phys = <&pcie_qmp1>;
phy-names = "pciephy";
ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
@@ -822,7 +811,7 @@ pcie0: pci@20000000 {
#address-cells = <3>;
#size-cells = <2>;
- phys = <&pcie_phy0>;
+ phys = <&pcie_qmp0>;
phy-names = "pciephy";
ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 33/41] arm64: dts: qcom: msm8998: switch PCIe QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (31 preceding siblings ...)
2023-03-24 2:25 ` [PATCH 32/41] arm64: dts: qcom: ipq8074: " Dmitry Baryshkov
@ 2023-03-24 2:25 ` Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 34/41] arm64: dts: qcom: sc7280: " Dmitry Baryshkov
` (7 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 30 ++++++++++++---------------
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 11e7d5b6f6d6..72221cd5fd1a 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -918,7 +918,7 @@ pcie0: pci@1c00000 {
#address-cells = <3>;
#size-cells = <2>;
num-lanes = <1>;
- phys = <&pciephy>;
+ phys = <&pcie_phy>;
phy-names = "pciephy";
status = "disabled";
@@ -948,32 +948,28 @@ pcie0: pci@1c00000 {
pcie_phy: phy@1c06000 {
compatible = "qcom,msm8998-qmp-pcie-phy";
- reg = <0x01c06000 0x18c>;
- #address-cells = <1>;
- #size-cells = <1>;
+ reg = <0x01c06000 0x1000>;
status = "disabled";
- ranges;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_CLKREF_CLK>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&gcc GCC_PCIE_CLKREF_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "pipe";
+
+ clock-output-names = "pcie_0_pipe_clk_src";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
reset-names = "phy", "common";
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l2a_1p2>;
-
- pciephy: phy@1c06800 {
- reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "pcie_0_pipe_clk_src";
- #clock-cells = <0>;
- };
};
ufshc: ufshc@1da4000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 34/41] arm64: dts: qcom: sc7280: switch PCIe QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (32 preceding siblings ...)
2023-03-24 2:25 ` [PATCH 33/41] arm64: dts: qcom: msm8998: " Dmitry Baryshkov
@ 2023-03-24 2:25 ` Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 35/41] arm64: dts: qcom: sdm845: " Dmitry Baryshkov
` (6 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 36 ++++++++++------------------
1 file changed, 12 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 62885ac3f11e..9d28b087c47b 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -848,7 +848,7 @@ gcc: clock-controller@100000 {
reg = <0 0x00100000 0 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
- <0>, <&pcie1_lane>,
+ <0>, <&pcie1_phy>,
<0>, <0>, <0>, <0>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
"pcie_0_pipe_clk", "pcie_1_pipe_clk",
@@ -2099,7 +2099,7 @@ pcie1: pci@1c08000 {
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
- <&pcie1_lane>,
+ <&pcie1_phy>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
@@ -2133,7 +2133,7 @@ pcie1: pci@1c08000 {
power-domains = <&gcc GCC_PCIE_1_GDSC>;
- phys = <&pcie1_lane>;
+ phys = <&pcie1_phy>;
phy-names = "pciephy";
pinctrl-names = "default";
@@ -2151,15 +2151,18 @@ pcie1: pci@1c08000 {
pcie1_phy: phy@1c0e000 {
compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
- reg = <0 0x01c0e000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01c0e000 0 0x1000>;
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_EN>,
- <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "refgen";
+ <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "refgen", "pipe";
+
+ clock-output-names = "pcie_1_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
@@ -2168,21 +2171,6 @@ pcie1_phy: phy@1c0e000 {
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie1_lane: phy@1c0e200 {
- reg = <0 0x01c0e200 0 0x170>,
- <0 0x01c0e400 0 0x200>,
- <0 0x01c0ea00 0 0x1f0>,
- <0 0x01c0e600 0 0x170>,
- <0 0x01c0e800 0 0x200>,
- <0 0x01c0ee00 0 0xf4>;
- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
- clock-names = "pipe0";
-
- #phy-cells = <0>;
- #clock-cells = <0>;
- clock-output-names = "pcie_1_pipe_clk";
- };
};
ipa: ipa@1e40000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 35/41] arm64: dts: qcom: sdm845: switch PCIe QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (33 preceding siblings ...)
2023-03-24 2:25 ` [PATCH 34/41] arm64: dts: qcom: sc7280: " Dmitry Baryshkov
@ 2023-03-24 2:25 ` Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 36/41] arm64: dts: qcom: sm8150: " Dmitry Baryshkov
` (5 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 71 ++++++++++++----------------
1 file changed, 30 insertions(+), 41 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 6eb82c5641cd..9cad1be584da 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1182,8 +1182,8 @@ gcc: clock-controller@100000 {
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
- <&pcie0_lane>,
- <&pcie1_lane>;
+ <&pcie0_phy>,
+ <&pcie1_phy>;
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"sleep_clk",
@@ -2354,7 +2354,7 @@ pcie0: pci@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_lane>;
+ phys = <&pcie0_phy>;
phy-names = "pciephy";
status = "disabled";
@@ -2362,15 +2362,22 @@ pcie0: pci@1c00000 {
pcie0_phy: phy@1c06000 {
compatible = "qcom,sdm845-qmp-pcie-phy";
- reg = <0 0x01c06000 0 0x18c>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01c06000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
- <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "refgen";
+ <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+
+ clock-output-names = "pcie_0_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
@@ -2379,19 +2386,6 @@ pcie0_phy: phy@1c06000 {
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie0_lane: phy@1c06200 {
- reg = <0 0x01c06200 0 0x128>,
- <0 0x01c06400 0 0x1fc>,
- <0 0x01c06800 0 0x218>,
- <0 0x01c06600 0 0x70>;
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
- clock-names = "pipe0";
-
- #clock-cells = <0>;
- #phy-cells = <0>;
- clock-output-names = "pcie_0_pipe_clk";
- };
};
pcie1: pci@1c08000 {
@@ -2464,7 +2458,7 @@ pcie1: pci@1c08000 {
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_lane>;
+ phys = <&pcie1_phy>;
phy-names = "pciephy";
status = "disabled";
@@ -2472,15 +2466,22 @@ pcie1: pci@1c08000 {
pcie1_phy: phy@1c0a000 {
compatible = "qcom,sdm845-qhp-pcie-phy";
- reg = <0 0x01c0a000 0 0x800>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01c0a000 0 0x2000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_CLKREF_CLK>,
- <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "refgen";
+ <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+
+ clock-output-names = "pcie_1_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
@@ -2489,18 +2490,6 @@ pcie1_phy: phy@1c0a000 {
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie1_lane: phy@1c06200 {
- reg = <0 0x01c0a800 0 0x800>,
- <0 0x01c0a800 0 0x800>,
- <0 0x01c0b800 0 0x400>;
- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
- clock-names = "pipe0";
-
- #clock-cells = <0>;
- #phy-cells = <0>;
- clock-output-names = "pcie_1_pipe_clk";
- };
};
mem_noc: interconnect@1380000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 36/41] arm64: dts: qcom: sm8150: switch PCIe QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (34 preceding siblings ...)
2023-03-24 2:25 ` [PATCH 35/41] arm64: dts: qcom: sdm845: " Dmitry Baryshkov
@ 2023-03-24 2:25 ` Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 37/41] arm64: dts: qcom: sm8250: " Dmitry Baryshkov
` (4 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 66 +++++++++++-----------------
1 file changed, 26 insertions(+), 40 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index be10b68893e8..e4ecc0804cd9 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1859,7 +1859,7 @@ pcie0: pci@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_lane>;
+ phys = <&pcie0_phy>;
phy-names = "pciephy";
perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
@@ -1873,14 +1873,20 @@ pcie0: pci@1c00000 {
pcie0_phy: phy@1c06000 {
compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
- reg = <0 0x01c06000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01c06000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
- <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
- clock-names = "aux", "cfg_ahb", "refgen";
+ <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "refgen",
+ "pipe";
+
+ clock-output-names = "pcie_0_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
@@ -1889,18 +1895,6 @@ pcie0_phy: phy@1c06000 {
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie0_lane: phy@1c06200 {
- reg = <0 0x01c06200 0 0x170>, /* tx */
- <0 0x01c06400 0 0x200>, /* rx */
- <0 0x01c06800 0 0x1f0>, /* pcs */
- <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
- clock-names = "pipe0";
-
- #phy-cells = <0>;
- clock-output-names = "pcie_0_pipe_clk";
- };
};
pcie1: pci@1c08000 {
@@ -1958,7 +1952,7 @@ pcie1: pci@1c08000 {
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_lane>;
+ phys = <&pcie1_phy>;
phy-names = "pciephy";
perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
@@ -1972,14 +1966,20 @@ pcie1: pci@1c08000 {
pcie1_phy: phy@1c0e000 {
compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
- reg = <0 0x01c0e000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01c0e000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
- <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
- clock-names = "aux", "cfg_ahb", "refgen";
+ <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "refgen",
+ "pipe";
+
+ clock-output-names = "pcie_1_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
@@ -1988,20 +1988,6 @@ pcie1_phy: phy@1c0e000 {
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie1_lane: phy@1c0e200 {
- reg = <0 0x01c0e200 0 0x170>, /* tx0 */
- <0 0x01c0e400 0 0x200>, /* rx0 */
- <0 0x01c0ea00 0 0x1f0>, /* pcs */
- <0 0x01c0e600 0 0x170>, /* tx1 */
- <0 0x01c0e800 0 0x200>, /* rx1 */
- <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
- clock-names = "pipe0";
-
- #phy-cells = <0>;
- clock-output-names = "pcie_1_pipe_clk";
- };
};
ufs_mem_hc: ufshc@1d84000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 37/41] arm64: dts: qcom: sm8250: switch PCIe QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (35 preceding siblings ...)
2023-03-24 2:25 ` [PATCH 36/41] arm64: dts: qcom: sm8150: " Dmitry Baryshkov
@ 2023-03-24 2:25 ` Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 38/41] arm64: dts: qcom: sm8450: " Dmitry Baryshkov
` (3 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 112 +++++++++++----------------
1 file changed, 45 insertions(+), 67 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 1d13864e978a..9b53667a0243 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -1888,7 +1888,7 @@ pcie0: pci@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_lane>;
+ phys = <&pcie0_phy>;
phy-names = "pciephy";
perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
@@ -1902,15 +1902,23 @@ pcie0: pci@1c00000 {
pcie0_phy: phy@1c06000 {
compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
- reg = <0 0x01c06000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01c06000 0 0x1000>;
+
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_WIFI_CLKREF_EN>,
- <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "refgen";
+ <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+
+ clock-output-names = "pcie_0_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
@@ -1919,20 +1927,6 @@ pcie0_phy: phy@1c06000 {
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie0_lane: phy@1c06200 {
- reg = <0 0x01c06200 0 0x170>, /* tx */
- <0 0x01c06400 0 0x200>, /* rx */
- <0 0x01c06800 0 0x1f0>, /* pcs */
- <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
- clock-names = "pipe0";
-
- #phy-cells = <0>;
-
- #clock-cells = <0>;
- clock-output-names = "pcie_0_pipe_clk";
- };
};
pcie1: pci@1c08000 {
@@ -1994,7 +1988,7 @@ pcie1: pci@1c08000 {
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_lane>;
+ phys = <&pcie1_phy>;
phy-names = "pciephy";
perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
@@ -2008,15 +2002,23 @@ pcie1: pci@1c08000 {
pcie1_phy: phy@1c0e000 {
compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
- reg = <0 0x01c0e000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01c0e000 0 0x1000>;
+
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
- <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "refgen";
+ <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+
+ clock-output-names = "pcie_1_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
@@ -2025,22 +2027,6 @@ pcie1_phy: phy@1c0e000 {
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie1_lane: phy@1c0e200 {
- reg = <0 0x01c0e200 0 0x170>, /* tx0 */
- <0 0x01c0e400 0 0x200>, /* rx0 */
- <0 0x01c0ea00 0 0x1f0>, /* pcs */
- <0 0x01c0e600 0 0x170>, /* tx1 */
- <0 0x01c0e800 0 0x200>, /* rx1 */
- <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
- clock-names = "pipe0";
-
- #phy-cells = <0>;
-
- #clock-cells = <0>;
- clock-output-names = "pcie_1_pipe_clk";
- };
};
pcie2: pci@1c10000 {
@@ -2102,7 +2088,7 @@ pcie2: pci@1c10000 {
power-domains = <&gcc PCIE_2_GDSC>;
- phys = <&pcie2_lane>;
+ phys = <&pcie2_phy>;
phy-names = "pciephy";
perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
@@ -2116,15 +2102,23 @@ pcie2: pci@1c10000 {
pcie2_phy: phy@1c16000 {
compatible = "qcom,sm8250-qmp-modem-pcie-phy";
- reg = <0 0x01c16000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01c16000 0 0x1000>;
+
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
<&gcc GCC_PCIE_MDM_CLKREF_EN>,
- <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "refgen";
+ <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
+ <&gcc GCC_PCIE_2_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+
+ clock-output-names = "pcie_2_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
reset-names = "phy";
@@ -2133,22 +2127,6 @@ pcie2_phy: phy@1c16000 {
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie2_lane: phy@1c16200 {
- reg = <0 0x01c16200 0 0x170>, /* tx0 */
- <0 0x01c16400 0 0x200>, /* rx0 */
- <0 0x01c16a00 0 0x1f0>, /* pcs */
- <0 0x01c16600 0 0x170>, /* tx1 */
- <0 0x01c16800 0 0x200>, /* rx1 */
- <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
- clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
- clock-names = "pipe0";
-
- #phy-cells = <0>;
-
- #clock-cells = <0>;
- clock-output-names = "pcie_2_pipe_clk";
- };
};
ufs_mem_hc: ufshc@1d84000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 38/41] arm64: dts: qcom: sm8450: switch PCIe QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (36 preceding siblings ...)
2023-03-24 2:25 ` [PATCH 37/41] arm64: dts: qcom: sm8250: " Dmitry Baryshkov
@ 2023-03-24 2:25 ` Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 39/41] ARM: dts: qcom-sdx55: switch USB " Dmitry Baryshkov
` (2 subsequent siblings)
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 82 ++++++++++++----------------
1 file changed, 35 insertions(+), 47 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 01fe1108cca2..e54288e52d70 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -742,8 +742,8 @@ gcc: clock-controller@100000 {
#power-domain-cells = <1>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
- <&pcie0_lane>,
- <&pcie1_lane>,
+ <&pcie0_phy>,
+ <&pcie1_phy>,
<0>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
@@ -1767,7 +1767,7 @@ pcie0: pci@1c00000 {
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
- <&pcie0_lane>,
+ <&pcie0_phy>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
@@ -1800,7 +1800,7 @@ pcie0: pci@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
power-domain-names = "gdsc";
- phys = <&pcie0_lane>;
+ phys = <&pcie0_phy>;
phy-names = "pciephy";
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
@@ -1814,15 +1814,23 @@ pcie0: pci@1c00000 {
pcie0_phy: phy@1c06000 {
compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
- reg = <0 0x01c06000 0 0x200>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01c06000 0 0x2000>;
+
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_EN>,
- <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "refgen";
+ <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+
+ clock-output-names = "pcie_0_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
@@ -1831,19 +1839,6 @@ pcie0_phy: phy@1c06000 {
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie0_lane: phy@1c06200 {
- reg = <0 0x01c06e00 0 0x200>, /* tx */
- <0 0x01c07000 0 0x200>, /* rx */
- <0 0x01c06200 0 0x200>, /* pcs */
- <0 0x01c06600 0 0x200>; /* pcs_pcie */
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
- clock-names = "pipe0";
-
- #clock-cells = <0>;
- #phy-cells = <0>;
- clock-output-names = "pcie_0_pipe_clk";
- };
};
pcie1: pci@1c08000 {
@@ -1883,7 +1878,7 @@ pcie1: pci@1c08000 {
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
- <&pcie1_lane>,
+ <&pcie1_phy>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
@@ -1914,7 +1909,7 @@ pcie1: pci@1c08000 {
power-domains = <&gcc PCIE_1_GDSC>;
power-domain-names = "gdsc";
- phys = <&pcie1_lane>;
+ phys = <&pcie1_phy>;
phy-names = "pciephy";
perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>;
@@ -1926,17 +1921,25 @@ pcie1: pci@1c08000 {
status = "disabled";
};
- pcie1_phy: phy@1c0f000 {
+ pcie1_phy: phy@1c0e000 {
compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
- reg = <0 0x01c0f000 0 0x200>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01c0e000 0 0x2000>;
+
clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_CLKREF_EN>,
- <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "refgen";
+ <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+
+ clock-output-names = "pcie_1_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
@@ -1945,21 +1948,6 @@ pcie1_phy: phy@1c0f000 {
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie1_lane: phy@1c0e000 {
- reg = <0 0x01c0e000 0 0x200>, /* tx */
- <0 0x01c0e200 0 0x300>, /* rx */
- <0 0x01c0f200 0 0x200>, /* pcs */
- <0 0x01c0e800 0 0x200>, /* tx */
- <0 0x01c0ea00 0 0x300>, /* rx */
- <0 0x01c0f400 0 0xc00>; /* pcs_pcie */
- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
- clock-names = "pipe0";
-
- #clock-cells = <0>;
- #phy-cells = <0>;
- clock-output-names = "pcie_1_pipe_clk";
- };
};
config_noc: interconnect@1500000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 39/41] ARM: dts: qcom-sdx55: switch USB QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (37 preceding siblings ...)
2023-03-24 2:25 ` [PATCH 38/41] arm64: dts: qcom: sm8450: " Dmitry Baryshkov
@ 2023-03-24 2:25 ` Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 40/41] ARM: dts: qcom-sdx65: " Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 41/41] ARM: dts: qcom-sdx55: switch PCIe " Dmitry Baryshkov
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 26 +++++++++++---------------
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
index 9148a840b8a0..d69e3e8b280e 100644
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -228,7 +228,7 @@ usb_hsphy: phy@ff4000 {
usb_qmpphy: phy@ff6000 {
compatible = "qcom,sdx55-qmp-usb3-uni-phy";
- reg = <0x00ff6000 0x1c0>;
+ reg = <0x00ff6000 0x1000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
@@ -236,23 +236,19 @@ usb_qmpphy: phy@ff6000 {
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "pipe";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB3PHY_PHY_BCR>,
<&gcc GCC_USB3_PHY_BCR>;
reset-names = "phy", "common";
-
- usb_ssphy: phy@ff6200 {
- reg = <0x00ff6200 0x170>,
- <0x00ff6400 0x200>,
- <0x00ff6800 0x800>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
};
mc_virt: interconnect@1100000 {
@@ -608,7 +604,7 @@ usb_dwc3: dwc3@a600000 {
iommus = <&apps_smmu 0x1a0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_hsphy>, <&usb_ssphy>;
+ phys = <&usb_hsphy>, <&usb_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 40/41] ARM: dts: qcom-sdx65: switch USB QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (38 preceding siblings ...)
2023-03-24 2:25 ` [PATCH 39/41] ARM: dts: qcom-sdx55: switch USB " Dmitry Baryshkov
@ 2023-03-24 2:25 ` Dmitry Baryshkov
2023-03-24 2:25 ` [PATCH 41/41] ARM: dts: qcom-sdx55: switch PCIe " Dmitry Baryshkov
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 29 +++++++++++------------------
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 192f9f94bc8b..87354317b9df 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -231,31 +231,24 @@ usb_hsphy: phy@ff4000 {
usb_qmpphy: phy@ff6000 {
compatible = "qcom,sdx65-qmp-usb3-uni-phy";
- reg = <0x00ff6000 0x1c8>;
+ reg = <0x00ff6000 0x2000>;
status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_PRIM_CLKREF_EN>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&gcc GCC_USB3_PRIM_CLKREF_EN>,
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "pipe";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB3PHY_PHY_BCR>,
<&gcc GCC_USB3_PHY_BCR>;
reset-names = "phy", "common";
-
- usb_ssphy: phy@ff6200 {
- reg = <0x00ff6e00 0x160>,
- <0x00ff7000 0x1ec>,
- <0x00ff6200 0x1e00>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
};
system_noc: interconnect@1620000 {
@@ -392,7 +385,7 @@ usb_dwc3: usb@a600000 {
iommus = <&apps_smmu 0x1a0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_hsphy>, <&usb_ssphy>;
+ phys = <&usb_hsphy>, <&usb_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH 41/41] ARM: dts: qcom-sdx55: switch PCIe QMP PHY to new style of bindings
2023-03-24 2:24 [PATCH 00/41] phy: qcom-qmp: convert to newer style of bindings Dmitry Baryshkov
` (39 preceding siblings ...)
2023-03-24 2:25 ` [PATCH 40/41] ARM: dts: qcom-sdx65: " Dmitry Baryshkov
@ 2023-03-24 2:25 ` Dmitry Baryshkov
40 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-03-24 2:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, Johan Hovold
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 31 ++++++++++++-------------------
1 file changed, 12 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
index d69e3e8b280e..30a58521a3d3 100644
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -375,7 +375,7 @@ pcie_rc: pcie@1c00000 {
power-domains = <&gcc PCIE_GDSC>;
- phys = <&pcie_lane>;
+ phys = <&pcie_phy>;
phy-names = "pciephy";
status = "disabled";
@@ -422,7 +422,7 @@ pcie_ep: pcie-ep@1c00000 {
resets = <&gcc GCC_PCIE_BCR>;
reset-names = "core";
power-domains = <&gcc PCIE_GDSC>;
- phys = <&pcie_lane>;
+ phys = <&pcie_phy>;
phy-names = "pciephy";
max-link-speed = <3>;
num-lanes = <2>;
@@ -432,18 +432,25 @@ pcie_ep: pcie-ep@1c00000 {
pcie_phy: phy@1c07000 {
compatible = "qcom,sdx55-qmp-pcie-phy";
- reg = <0x01c07000 0x1c4>;
+ reg = <0x01c07000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
- <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
+ <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
+ <&gcc GCC_PCIE_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
- "refgen";
+ "refgen",
+ "pipe";
+
+ clock-output-names = "pcie_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_PHY_BCR>;
reset-names = "phy";
@@ -452,20 +459,6 @@ pcie_phy: phy@1c07000 {
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie_lane: lanes@1c06000 {
- reg = <0x01c06000 0x104>, /* tx0 */
- <0x01c06200 0x328>, /* rx0 */
- <0x01c07200 0x1e8>, /* pcs */
- <0x01c06800 0x104>, /* tx1 */
- <0x01c06a00 0x328>, /* rx1 */
- <0x01c07600 0x800>; /* pcs_misc */
- clocks = <&gcc GCC_PCIE_PIPE_CLK>;
- clock-names = "pipe0";
-
- #phy-cells = <0>;
- clock-output-names = "pcie_pipe_clk";
- };
};
ipa: ipa@1e40000 {
--
2.30.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread