From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 3/6] clk: renesas: r9a07g043: Add USB clocks/resets
Date: Mon, 25 Apr 2022 10:52:41 +0100 [thread overview]
Message-ID: <20220425095244.156720-4-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20220425095244.156720-1-biju.das.jz@bp.renesas.com>
Add clock/reset entries for USB PHY control, USB2.0 host and device.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g043-cpg.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index d54bccf7b61b..ea826f000d8d 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -160,6 +160,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x570, 6),
DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0,
0x570, 7),
+ DEF_MOD("usb0_host", R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1,
+ 0x578, 0),
+ DEF_MOD("usb1_host", R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1,
+ 0x578, 1),
+ DEF_MOD("usb0_func", R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1,
+ 0x578, 2),
+ DEF_MOD("usb_pclk", R9A07G043_USB_PCLK, R9A07G043_CLK_P1,
+ 0x578, 3),
DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0,
0x57c, 0),
DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT,
@@ -206,6 +214,10 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1),
DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2),
DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3),
+ DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0),
+ DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1),
+ DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2),
+ DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3),
DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),
--
2.25.1
next prev parent reply other threads:[~2022-04-25 9:53 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-25 9:52 [PATCH 0/6] Add RZ/G2UL CLK and Reset entries for I2C,SSI,USB,CANFD,OSTM and WDT Biju Das
2022-04-25 9:52 ` [PATCH 1/6] clk: renesas: r9a07g043: Add I2C clocks/resets Biju Das
2022-04-28 12:21 ` Geert Uytterhoeven
2022-04-25 9:52 ` [PATCH 2/6] clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries Biju Das
2022-04-28 12:21 ` Geert Uytterhoeven
2022-04-25 9:52 ` Biju Das [this message]
2022-04-28 12:21 ` [PATCH 3/6] clk: renesas: r9a07g043: Add USB clocks/resets Geert Uytterhoeven
2022-04-25 9:52 ` [PATCH 4/6] clk: renesas: r9a07g043: Add clock and reset entries for CANFD Biju Das
2022-04-28 12:20 ` Geert Uytterhoeven
2022-04-25 9:52 ` [PATCH 5/6] clk: renesas: r9a07g043: Add OSTM clock and reset entries Biju Das
2022-04-28 12:19 ` Geert Uytterhoeven
2022-04-28 12:23 ` Biju Das
2022-04-25 9:52 ` [PATCH 6/6] clk: renesas: r9a07g043: Add WDT " Biju Das
2022-04-28 12:18 ` Geert Uytterhoeven
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