From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 5/6] clk: renesas: r9a07g043: Add OSTM clock and reset entries
Date: Mon, 25 Apr 2022 10:52:43 +0100 [thread overview]
Message-ID: <20220425095244.156720-6-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20220425095244.156720-1-biju.das.jz@bp.renesas.com>
Add OSTM{0,1,2} clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g043-cpg.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 59d5405474a5..ac2b361efbb6 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -129,6 +129,12 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x52c, 0),
DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
0x52c, 1),
+ DEF_MOD("ostm0", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0,
+ 0x534, 0),
+ DEF_MOD("ostm1", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0,
+ 0x534, 1),
+ DEF_MOD("ostm2", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
+ 0x534, 2),
DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4,
0x554, 0),
DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4,
@@ -211,6 +217,9 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
+ DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
+ DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
+ DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),
--
2.25.1
next prev parent reply other threads:[~2022-04-25 9:53 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-25 9:52 [PATCH 0/6] Add RZ/G2UL CLK and Reset entries for I2C,SSI,USB,CANFD,OSTM and WDT Biju Das
2022-04-25 9:52 ` [PATCH 1/6] clk: renesas: r9a07g043: Add I2C clocks/resets Biju Das
2022-04-28 12:21 ` Geert Uytterhoeven
2022-04-25 9:52 ` [PATCH 2/6] clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries Biju Das
2022-04-28 12:21 ` Geert Uytterhoeven
2022-04-25 9:52 ` [PATCH 3/6] clk: renesas: r9a07g043: Add USB clocks/resets Biju Das
2022-04-28 12:21 ` Geert Uytterhoeven
2022-04-25 9:52 ` [PATCH 4/6] clk: renesas: r9a07g043: Add clock and reset entries for CANFD Biju Das
2022-04-28 12:20 ` Geert Uytterhoeven
2022-04-25 9:52 ` Biju Das [this message]
2022-04-28 12:19 ` [PATCH 5/6] clk: renesas: r9a07g043: Add OSTM clock and reset entries Geert Uytterhoeven
2022-04-28 12:23 ` Biju Das
2022-04-25 9:52 ` [PATCH 6/6] clk: renesas: r9a07g043: Add WDT " Biju Das
2022-04-28 12:18 ` Geert Uytterhoeven
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