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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Biju Das <biju.das@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 4/6] clk: renesas: r9a07g043: Add clock and reset entries for CANFD
Date: Mon, 25 Apr 2022 10:52:42 +0100	[thread overview]
Message-ID: <20220425095244.156720-5-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20220425095244.156720-1-biju.das.jz@bp.renesas.com>

Add clock and reset entries for CANFD in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g043-cpg.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index ea826f000d8d..59d5405474a5 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -100,6 +100,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
 		CLK_DIVIDER_HIWORD_MASK),
 	DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
 		dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+	DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2),
 	DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4,
 		DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
 	DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2),
@@ -198,6 +199,8 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
 				0x588, 0),
 	DEF_MOD("sci1",		R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0,
 				0x588, 1),
+	DEF_MOD("canfd",	R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0,
+				0x594, 0),
 	DEF_MOD("gpio",		R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,
 				0x598, 0),
 };
@@ -231,6 +234,8 @@ static struct rzg2l_reset r9a07g043_resets[] = {
 	DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),
 	DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),
 	DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),
+	DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0),
+	DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1),
 	DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),
 	DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1),
 	DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2),
-- 
2.25.1


  parent reply	other threads:[~2022-04-25  9:53 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-25  9:52 [PATCH 0/6] Add RZ/G2UL CLK and Reset entries for I2C,SSI,USB,CANFD,OSTM and WDT Biju Das
2022-04-25  9:52 ` [PATCH 1/6] clk: renesas: r9a07g043: Add I2C clocks/resets Biju Das
2022-04-28 12:21   ` Geert Uytterhoeven
2022-04-25  9:52 ` [PATCH 2/6] clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries Biju Das
2022-04-28 12:21   ` Geert Uytterhoeven
2022-04-25  9:52 ` [PATCH 3/6] clk: renesas: r9a07g043: Add USB clocks/resets Biju Das
2022-04-28 12:21   ` Geert Uytterhoeven
2022-04-25  9:52 ` Biju Das [this message]
2022-04-28 12:20   ` [PATCH 4/6] clk: renesas: r9a07g043: Add clock and reset entries for CANFD Geert Uytterhoeven
2022-04-25  9:52 ` [PATCH 5/6] clk: renesas: r9a07g043: Add OSTM clock and reset entries Biju Das
2022-04-28 12:19   ` Geert Uytterhoeven
2022-04-28 12:23     ` Biju Das
2022-04-25  9:52 ` [PATCH 6/6] clk: renesas: r9a07g043: Add WDT " Biju Das
2022-04-28 12:18   ` Geert Uytterhoeven

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