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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	Magnus Damm <magnus.damm@gmail.com>,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Prabhakar <prabhakar.csengg@gmail.com>,
	Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v3 2/4] pinctrl: renesas: Add RZ/G2L pin and gpio controller driver
Date: Mon, 26 Jul 2021 15:25:07 +0200	[thread overview]
Message-ID: <CAMuHMdWD+p7w2_KSsM-sYoZfK-7z4BM7yXAOf+5amxkmq4xvPg@mail.gmail.com> (raw)
In-Reply-To: <20210721191558.22484-3-prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi Prabhakar,

On Wed, Jul 21, 2021 at 9:16 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add support for pin and gpio controller driver for RZ/G2L SoC.
>
> Based on a patch in the BSP by Hien Huynh <hien.huynh.px@renesas.com>.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for the update!

> --- /dev/null
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c

> +#define RZG2L_MPXED_PIN_FUNCS          (PIN_CFG_IOLH | \
> +                                        PIN_CFG_SR | \
> +                                        PIN_CFG_PUPD | \
> +                                        PIN_CFG_FILONOFF | \
> +                                        PIN_CFG_FILNUM | \
> +                                        PIN_CFG_FILCLKSEL)
> +
> +#define RZG2L_MPXED_ETH_PIN_FUNCS(x)   ((x) | \
> +                                        PIN_CFG_FILONOFF | \
> +                                        PIN_CFG_FILNUM | \
> +                                        PIN_CFG_FILCLKSEL)

I thought you were going for MULTI? ;-)

> +
> +/*
> + * n indicates number of pins in the port, a is the register index
> + * and f is pin configuration capabilities supported.
> + */
> +#define RZG2L_GPIO_PORT_PACK(n, a, f)  (((n) << 28) | ((a) << 20) | (f))
> +#define RZG2L_GPIO_PORT_GET_PINCNT(x)  (((x) >> 28) & 0x7)
> +#define RZG2L_GPIO_PORT_GET_INDEX(x)   ((((x) & GENMASK(27, 20)) >> 20) & 0x7f)

Actually the "& 0x7f" can be removed, too, if you adjust the mask:

    (((x) & GENMASK(26, 20)) >> 20)

> +#define RZG2L_GPIO_PORT_GET_CFGS(x)    ((x) & GENMASK(19, 0))
> +
> +/*
> + * BIT(31) indicates dedicated pin, p is the register index while
> + * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits
> + * (b * 8) and f is the pin configuration capabilities supported.
> + */
> +#define RZG2L_SINGLE_PIN               BIT(31)
> +#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
> +                                        ((p) << 24) | ((b) << 20) | (f))
> +#define RZG2L_SINGLE_PIN_GET_PORT(x)   (((x) >> 24) & 0x7f)
> +#define RZG2L_SINGLE_PIN_GET_BIT(x)    ((((x) & GENMASK(23, 20)) >> 20) & 0x7)

Likewise:

    (((x) & GENMASK(22, 20)) >> 20)

> +#define RZG2L_SINGLE_PIN_GET_CFGS(x)   ((x) & GENMASK(19, 0))

> +       struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> +       struct function_desc *func;
> +       unsigned int i, *psel_val;
> +       struct group_desc *group;
> +       unsigned long data;
> +       int *pins;
> +
> +       func = pinmux_generic_get_function(pctldev, func_selector);
> +       if (!func)
> +               return -EINVAL;
> +       group = pinctrl_generic_get_group(pctldev, group_selector);
> +       if (!group)
> +               return -EINVAL;
> +
> +       psel_val = func->data;
> +       pins = group->pins;
> +       data = (unsigned long)group->data;

Lkp reports data is unused.
Which matches with passing NULL as the last parameter of
pinctrl_generic_add_group().

> +
> +       for (i = 0; i < group->num_pins; i++) {
> +               dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n",
> +                       RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]),
> +                       psel_val[i]);
> +               rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]),
> +                                          RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]);
> +       }
> +
> +       return 0;
> +};

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

  parent reply	other threads:[~2021-07-26 13:25 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-21 19:15 [PATCH v3 0/4] pin and gpio controller driver for Renesas RZ/G2L Lad Prabhakar
2021-07-21 19:15 ` [PATCH v3 1/4] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Add DT bindings for RZ/G2L pinctrl Lad Prabhakar
2021-07-22 14:37   ` Rob Herring
2021-07-27  9:26     ` Lad, Prabhakar
2021-07-27 14:42       ` Rob Herring
2021-07-27 14:43   ` Rob Herring
2021-07-21 19:15 ` [PATCH v3 2/4] pinctrl: renesas: Add RZ/G2L pin and gpio controller driver Lad Prabhakar
2021-07-21 20:34   ` kernel test robot
2021-07-26 13:25   ` Geert Uytterhoeven [this message]
2021-07-26 13:34     ` Andy Shevchenko
2021-07-26 16:03       ` Lad, Prabhakar
2021-07-26 16:02     ` Lad, Prabhakar
2021-07-21 19:15 ` [PATCH v3 3/4] arm64: dts: renesas: r9a07g044: Add pinctrl node Lad Prabhakar
2021-07-21 19:15 ` [PATCH v3 4/4] arm64: dts: renesas: rzg2l-smarc: Add scif0 pins Lad Prabhakar

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