* [PATCH RFC 1/7] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-09-29 10:30 [PATCH RFC 0/7] Add RZ/G2L MTU3 PWM driver Biju Das
@ 2022-09-29 10:30 ` Biju Das
2022-09-29 17:53 ` Lee Jones
2022-09-29 10:30 ` [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2L MTU3 counter Biju Das
` (5 subsequent siblings)
6 siblings, 1 reply; 28+ messages in thread
From: Biju Das @ 2022-09-29 10:30 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Lee Jones, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
channels and one 32-bit timer channel. It supports the following
functions
- Counter
- Timer
- PWM
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
It is same as [1]. Just sending this patch to avoid any bot error for
the subsequent patches.
[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220926132114.60396-3-biju.das.jz@bp.renesas.com/
---
.../bindings/mfd/renesas,rzg2l-mtu3.yaml | 275 ++++++++++++++++++
1 file changed, 275 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
new file mode 100644
index 000000000000..c1fae8e8d9f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
@@ -0,0 +1,275 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/renesas,rzg2l-mtu3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a) bindings
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+ This hardware block pconsisting of eight 16-bit timer channels and one
+ 32- bit timer channel. It supports the following specifications:
+ - Pulse input/output: 28 lines max.
+ - Pulse input 3 lines
+ - Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks
+ for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
+ (when LWA = 1))
+ - Operating frequency Up to 100 MHz
+ - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
+ - Waveform output on compare match
+ - Input capture function (noise filter setting available)
+ - Counter-clearing operation
+ - Simultaneous writing to multiple timer counters (TCNT)
+ (excluding MTU8).
+ - Simultaneous clearing on compare match or input capture
+ (excluding MTU8).
+ - Simultaneous input and output to registers in synchronization with
+ counter operations (excluding MTU8).
+ - Up to 12-phase PWM output in combination with synchronous operation
+ (excluding MTU8)
+ - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
+ - Buffer operation specifiable
+ - [MTU1, MTU2]
+ - Phase counting mode can be specified independently
+ - 32-bit phase counting mode can be specified for interlocked operation
+ of MTU1 and MTU2 (when TMDR3.LWA = 1)
+ - Cascade connection operation available
+ - [MTU3, MTU4, MTU6, and MTU7]
+ - Through interlocked operation of MTU3/4 and MTU6/7, the positive and
+ negative signals in six phases (12 phases in total) can be output in
+ complementary PWM and reset-synchronized PWM operation.
+ - In complementary PWM mode, values can be transferred from buffer
+ registers to temporary registers at crests and troughs of the timer-
+ counter values or when the buffer registers (TGRD registers in MTU4
+ and MTU7) are written to.
+ - Double-buffering selectable in complementary PWM mode.
+ - [MTU3 and MTU4]
+ - Through interlocking with MTU0, a mode for driving AC synchronous
+ motors (brushless DC motors) by using complementary PWM output and
+ reset-synchronized PWM output is settable and allows the selection
+ of two types of waveform output (chopping or level).
+ - [MTU5]
+ - Capable of operation as a dead-time compensation counter.
+ - [MTU0/MTU5, MTU1, MTU2, and MTU8]
+ - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
+ through interlocked operation with MTU0/MTU5 and MTU8.
+ - Interrupt-skipping function
+ - In complementary PWM mode, interrupts on crests and troughs of counter
+ values and triggers to start conversion by the A/D converter can be
+ skipped.
+ - Interrupt sources: 43 sources.
+ - Buffer operation:
+ - Automatic transfer of register data (transfer from the buffer
+ register to the timer register).
+ - Trigger generation
+ - A/D converter start triggers can be generated
+ - A/D converter start request delaying function enables A/D converter
+ to be started with any desired timing and to be synchronized with
+ PWM output.
+ - Low power consumption function
+ - The MTU3a can be placed in the module-stop state.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
+ - renesas,r9a07g054-mtu3 # RZ/V2L
+ - const: renesas,rzg2l-mtu3
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: MTU0.TGRA input capture/compare match
+ - description: MTU0.TGRB input capture/compare match
+ - description: MTU0.TGRC input capture/compare match
+ - description: MTU0.TGRD input capture/compare match
+ - description: MTU0.TCNT overflow
+ - description: MTU0.TGRE compare match
+ - description: MTU0.TGRF compare match
+ - description: MTU1.TGRA input capture/compare match
+ - description: MTU1.TGRB input capture/compare match
+ - description: MTU1.TCNT overflow
+ - description: MTU1.TCNT underflow
+ - description: MTU2.TGRA input capture/compare match
+ - description: MTU2.TGRB input capture/compare match
+ - description: MTU2.TCNT overflow
+ - description: MTU2.TCNT underflow
+ - description: MTU3.TGRA input capture/compare match
+ - description: MTU3.TGRB input capture/compare match
+ - description: MTU3.TGRC input capture/compare match
+ - description: MTU3.TGRD input capture/compare match
+ - description: MTU3.TCNT overflow
+ - description: MTU4.TGRA input capture/compare match
+ - description: MTU4.TGRB input capture/compare match
+ - description: MTU4.TGRC input capture/compare match
+ - description: MTU4.TGRD input capture/compare match
+ - description: MTU4.TCNT overflow/underflow
+ - description: MTU5.TGRU input capture/compare match
+ - description: MTU5.TGRV input capture/compare match
+ - description: MTU5.TGRW input capture/compare match
+ - description: MTU6.TGRA input capture/compare match
+ - description: MTU6.TGRB input capture/compare match
+ - description: MTU6.TGRC input capture/compare match
+ - description: MTU6.TGRD input capture/compare match
+ - description: MTU6.TCNT overflow
+ - description: MTU7.TGRA input capture/compare match
+ - description: MTU7.TGRB input capture/compare match
+ - description: MTU7.TGRC input capture/compare match
+ - description: MTU7.TGRD input capture/compare match
+ - description: MTU7.TCNT overflow/underflow
+ - description: MTU8.TGRA input capture/compare match
+ - description: MTU8.TGRB input capture/compare match
+ - description: MTU8.TGRC input capture/compare match
+ - description: MTU8.TGRD input capture/compare match
+ - description: MTU8.TCNT overflow
+ - description: MTU8.TCNT underflow
+
+ interrupt-names:
+ items:
+ - const: tgia0
+ - const: tgib0
+ - const: tgic0
+ - const: tgid0
+ - const: tgiv0
+ - const: tgie0
+ - const: tgif0
+ - const: tgia1
+ - const: tgib1
+ - const: tgiv1
+ - const: tgiu1
+ - const: tgia2
+ - const: tgib2
+ - const: tgiv2
+ - const: tgiu2
+ - const: tgia3
+ - const: tgib3
+ - const: tgic3
+ - const: tgid3
+ - const: tgiv3
+ - const: tgia4
+ - const: tgib4
+ - const: tgic4
+ - const: tgid4
+ - const: tgiv4
+ - const: tgiu5
+ - const: tgiv5
+ - const: tgiw5
+ - const: tgia6
+ - const: tgib6
+ - const: tgic6
+ - const: tgid6
+ - const: tgiv6
+ - const: tgia7
+ - const: tgib7
+ - const: tgic7
+ - const: tgid7
+ - const: tgiv7
+ - const: tgia8
+ - const: tgib8
+ - const: tgic8
+ - const: tgid8
+ - const: tgiv8
+ - const: tgiu8
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - power-domains
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ mtu3: timer@10001200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,r9a07g044-mtu3", "renesas,rzg2l-mtu3";
+ reg = <0x10001200 0xb00>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tgiv0", "tgie0",
+ "tgif0",
+ "tgia1", "tgib1", "tgiv1", "tgiu1",
+ "tgia2", "tgib2", "tgiv2", "tgiu2",
+ "tgia3", "tgib3", "tgic3", "tgid3", "tgiv3",
+ "tgia4", "tgib4", "tgic4", "tgid4", "tgiv4",
+ "tgiu5", "tgiv5", "tgiw5",
+ "tgia6", "tgib6", "tgic6", "tgid6", "tgiv6",
+ "tgia7", "tgib7", "tgic7", "tgid7", "tgiv7",
+ "tgia8", "tgib8", "tgic8", "tgid8", "tgiv8", "tgiu8";
+ clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
+ };
+
+...
--
2.25.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH RFC 1/7] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-09-29 10:30 ` [PATCH RFC 1/7] dt-bindings: mfd: Document RZ/G2L MTU3a bindings Biju Das
@ 2022-09-29 17:53 ` Lee Jones
2022-09-30 17:47 ` Rob Herring
0 siblings, 1 reply; 28+ messages in thread
From: Lee Jones @ 2022-09-29 17:53 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
On Thu, 29 Sep 2022, Biju Das wrote:
> The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
> the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
> channels and one 32-bit timer channel. It supports the following
> functions
> - Counter
> - Timer
> - PWM
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> It is same as [1]. Just sending this patch to avoid any bot error for
> the subsequent patches.
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220926132114.60396-3-biju.das.jz@bp.renesas.com/
> ---
> .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 275 ++++++++++++++++++
> 1 file changed, 275 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> new file mode 100644
> index 000000000000..c1fae8e8d9f9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> @@ -0,0 +1,275 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/renesas,rzg2l-mtu3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a) bindings
> +
> +maintainers:
> + - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +description: |
> + This hardware block pconsisting of eight 16-bit timer channels and one
> + 32- bit timer channel. It supports the following specifications:
> + - Pulse input/output: 28 lines max.
> + - Pulse input 3 lines
> + - Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks
> + for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
> + (when LWA = 1))
> + - Operating frequency Up to 100 MHz
> + - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
> + - Waveform output on compare match
> + - Input capture function (noise filter setting available)
> + - Counter-clearing operation
> + - Simultaneous writing to multiple timer counters (TCNT)
> + (excluding MTU8).
> + - Simultaneous clearing on compare match or input capture
> + (excluding MTU8).
> + - Simultaneous input and output to registers in synchronization with
> + counter operations (excluding MTU8).
> + - Up to 12-phase PWM output in combination with synchronous operation
> + (excluding MTU8)
> + - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
> + - Buffer operation specifiable
> + - [MTU1, MTU2]
> + - Phase counting mode can be specified independently
> + - 32-bit phase counting mode can be specified for interlocked operation
> + of MTU1 and MTU2 (when TMDR3.LWA = 1)
> + - Cascade connection operation available
> + - [MTU3, MTU4, MTU6, and MTU7]
> + - Through interlocked operation of MTU3/4 and MTU6/7, the positive and
> + negative signals in six phases (12 phases in total) can be output in
> + complementary PWM and reset-synchronized PWM operation.
> + - In complementary PWM mode, values can be transferred from buffer
> + registers to temporary registers at crests and troughs of the timer-
> + counter values or when the buffer registers (TGRD registers in MTU4
> + and MTU7) are written to.
> + - Double-buffering selectable in complementary PWM mode.
> + - [MTU3 and MTU4]
> + - Through interlocking with MTU0, a mode for driving AC synchronous
> + motors (brushless DC motors) by using complementary PWM output and
> + reset-synchronized PWM output is settable and allows the selection
> + of two types of waveform output (chopping or level).
> + - [MTU5]
> + - Capable of operation as a dead-time compensation counter.
> + - [MTU0/MTU5, MTU1, MTU2, and MTU8]
> + - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
> + through interlocked operation with MTU0/MTU5 and MTU8.
> + - Interrupt-skipping function
> + - In complementary PWM mode, interrupts on crests and troughs of counter
> + values and triggers to start conversion by the A/D converter can be
> + skipped.
> + - Interrupt sources: 43 sources.
> + - Buffer operation:
> + - Automatic transfer of register data (transfer from the buffer
> + register to the timer register).
> + - Trigger generation
> + - A/D converter start triggers can be generated
> + - A/D converter start request delaying function enables A/D converter
> + to be started with any desired timing and to be synchronized with
> + PWM output.
> + - Low power consumption function
> + - The MTU3a can be placed in the module-stop state.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
> + - renesas,r9a07g054-mtu3 # RZ/V2L
> + - const: renesas,rzg2l-mtu3
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + items:
> + - description: MTU0.TGRA input capture/compare match
> + - description: MTU0.TGRB input capture/compare match
> + - description: MTU0.TGRC input capture/compare match
> + - description: MTU0.TGRD input capture/compare match
> + - description: MTU0.TCNT overflow
> + - description: MTU0.TGRE compare match
> + - description: MTU0.TGRF compare match
> + - description: MTU1.TGRA input capture/compare match
> + - description: MTU1.TGRB input capture/compare match
> + - description: MTU1.TCNT overflow
> + - description: MTU1.TCNT underflow
> + - description: MTU2.TGRA input capture/compare match
> + - description: MTU2.TGRB input capture/compare match
> + - description: MTU2.TCNT overflow
> + - description: MTU2.TCNT underflow
> + - description: MTU3.TGRA input capture/compare match
> + - description: MTU3.TGRB input capture/compare match
> + - description: MTU3.TGRC input capture/compare match
> + - description: MTU3.TGRD input capture/compare match
> + - description: MTU3.TCNT overflow
> + - description: MTU4.TGRA input capture/compare match
> + - description: MTU4.TGRB input capture/compare match
> + - description: MTU4.TGRC input capture/compare match
> + - description: MTU4.TGRD input capture/compare match
> + - description: MTU4.TCNT overflow/underflow
> + - description: MTU5.TGRU input capture/compare match
> + - description: MTU5.TGRV input capture/compare match
> + - description: MTU5.TGRW input capture/compare match
> + - description: MTU6.TGRA input capture/compare match
> + - description: MTU6.TGRB input capture/compare match
> + - description: MTU6.TGRC input capture/compare match
> + - description: MTU6.TGRD input capture/compare match
> + - description: MTU6.TCNT overflow
> + - description: MTU7.TGRA input capture/compare match
> + - description: MTU7.TGRB input capture/compare match
> + - description: MTU7.TGRC input capture/compare match
> + - description: MTU7.TGRD input capture/compare match
> + - description: MTU7.TCNT overflow/underflow
> + - description: MTU8.TGRA input capture/compare match
> + - description: MTU8.TGRB input capture/compare match
> + - description: MTU8.TGRC input capture/compare match
> + - description: MTU8.TGRD input capture/compare match
> + - description: MTU8.TCNT overflow
> + - description: MTU8.TCNT underflow
> +
> + interrupt-names:
> + items:
> + - const: tgia0
> + - const: tgib0
> + - const: tgic0
> + - const: tgid0
> + - const: tgiv0
> + - const: tgie0
> + - const: tgif0
> + - const: tgia1
> + - const: tgib1
> + - const: tgiv1
> + - const: tgiu1
> + - const: tgia2
> + - const: tgib2
> + - const: tgiv2
> + - const: tgiu2
> + - const: tgia3
> + - const: tgib3
> + - const: tgic3
> + - const: tgid3
> + - const: tgiv3
> + - const: tgia4
> + - const: tgib4
> + - const: tgic4
> + - const: tgid4
> + - const: tgiv4
> + - const: tgiu5
> + - const: tgiv5
> + - const: tgiw5
> + - const: tgia6
> + - const: tgib6
> + - const: tgic6
> + - const: tgid6
> + - const: tgiv6
> + - const: tgia7
> + - const: tgib7
> + - const: tgic7
> + - const: tgid7
> + - const: tgiv7
> + - const: tgia8
> + - const: tgib8
> + - const: tgic8
> + - const: tgid8
> + - const: tgiv8
> + - const: tgiu8
> +
> + clocks:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> + - clocks
> + - power-domains
> + - resets
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/r9a07g044-cpg.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + mtu3: timer@10001200 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "renesas,r9a07g044-mtu3", "renesas,rzg2l-mtu3";
> + reg = <0x10001200 0xb00>;
> + interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tgiv0", "tgie0",
> + "tgif0",
> + "tgia1", "tgib1", "tgiv1", "tgiu1",
> + "tgia2", "tgib2", "tgiv2", "tgiu2",
> + "tgia3", "tgib3", "tgic3", "tgid3", "tgiv3",
> + "tgia4", "tgib4", "tgic4", "tgid4", "tgiv4",
> + "tgiu5", "tgiv5", "tgiw5",
> + "tgia6", "tgib6", "tgic6", "tgid6", "tgiv6",
> + "tgia7", "tgib7", "tgic7", "tgid7", "tgiv7",
> + "tgia8", "tgib8", "tgic8", "tgid8", "tgiv8", "tgiu8";
Not sure you need to list all of the IRQs in the example.
> + clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
> + };
> +
> +...
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH RFC 1/7] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-09-29 17:53 ` Lee Jones
@ 2022-09-30 17:47 ` Rob Herring
2022-10-03 7:34 ` Lee Jones
0 siblings, 1 reply; 28+ messages in thread
From: Rob Herring @ 2022-09-30 17:47 UTC (permalink / raw)
To: Lee Jones
Cc: Biju Das, Krzysztof Kozlowski, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
On Thu, Sep 29, 2022 at 06:53:49PM +0100, Lee Jones wrote:
> On Thu, 29 Sep 2022, Biju Das wrote:
>
> > The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
> > the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
> > channels and one 32-bit timer channel. It supports the following
> > functions
> > - Counter
> > - Timer
> > - PWM
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > It is same as [1]. Just sending this patch to avoid any bot error for
> > the subsequent patches.
> > [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220926132114.60396-3-biju.das.jz@bp.renesas.com/
> > ---
> > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 275 ++++++++++++++++++
> > 1 file changed, 275 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > new file mode 100644
> > index 000000000000..c1fae8e8d9f9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > @@ -0,0 +1,275 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/mfd/renesas,rzg2l-mtu3.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a) bindings
> > +
> > +maintainers:
> > + - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +description: |
> > + This hardware block pconsisting of eight 16-bit timer channels and one
> > + 32- bit timer channel. It supports the following specifications:
> > + - Pulse input/output: 28 lines max.
> > + - Pulse input 3 lines
> > + - Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks
> > + for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
> > + (when LWA = 1))
> > + - Operating frequency Up to 100 MHz
> > + - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
> > + - Waveform output on compare match
> > + - Input capture function (noise filter setting available)
> > + - Counter-clearing operation
> > + - Simultaneous writing to multiple timer counters (TCNT)
> > + (excluding MTU8).
> > + - Simultaneous clearing on compare match or input capture
> > + (excluding MTU8).
> > + - Simultaneous input and output to registers in synchronization with
> > + counter operations (excluding MTU8).
> > + - Up to 12-phase PWM output in combination with synchronous operation
> > + (excluding MTU8)
> > + - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
> > + - Buffer operation specifiable
> > + - [MTU1, MTU2]
> > + - Phase counting mode can be specified independently
> > + - 32-bit phase counting mode can be specified for interlocked operation
> > + of MTU1 and MTU2 (when TMDR3.LWA = 1)
> > + - Cascade connection operation available
> > + - [MTU3, MTU4, MTU6, and MTU7]
> > + - Through interlocked operation of MTU3/4 and MTU6/7, the positive and
> > + negative signals in six phases (12 phases in total) can be output in
> > + complementary PWM and reset-synchronized PWM operation.
> > + - In complementary PWM mode, values can be transferred from buffer
> > + registers to temporary registers at crests and troughs of the timer-
> > + counter values or when the buffer registers (TGRD registers in MTU4
> > + and MTU7) are written to.
> > + - Double-buffering selectable in complementary PWM mode.
> > + - [MTU3 and MTU4]
> > + - Through interlocking with MTU0, a mode for driving AC synchronous
> > + motors (brushless DC motors) by using complementary PWM output and
> > + reset-synchronized PWM output is settable and allows the selection
> > + of two types of waveform output (chopping or level).
> > + - [MTU5]
> > + - Capable of operation as a dead-time compensation counter.
> > + - [MTU0/MTU5, MTU1, MTU2, and MTU8]
> > + - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
> > + through interlocked operation with MTU0/MTU5 and MTU8.
> > + - Interrupt-skipping function
> > + - In complementary PWM mode, interrupts on crests and troughs of counter
> > + values and triggers to start conversion by the A/D converter can be
> > + skipped.
> > + - Interrupt sources: 43 sources.
> > + - Buffer operation:
> > + - Automatic transfer of register data (transfer from the buffer
> > + register to the timer register).
> > + - Trigger generation
> > + - A/D converter start triggers can be generated
> > + - A/D converter start request delaying function enables A/D converter
> > + to be started with any desired timing and to be synchronized with
> > + PWM output.
> > + - Low power consumption function
> > + - The MTU3a can be placed in the module-stop state.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
> > + - renesas,r9a07g054-mtu3 # RZ/V2L
> > + - const: renesas,rzg2l-mtu3
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + items:
> > + - description: MTU0.TGRA input capture/compare match
> > + - description: MTU0.TGRB input capture/compare match
> > + - description: MTU0.TGRC input capture/compare match
> > + - description: MTU0.TGRD input capture/compare match
> > + - description: MTU0.TCNT overflow
> > + - description: MTU0.TGRE compare match
> > + - description: MTU0.TGRF compare match
> > + - description: MTU1.TGRA input capture/compare match
> > + - description: MTU1.TGRB input capture/compare match
> > + - description: MTU1.TCNT overflow
> > + - description: MTU1.TCNT underflow
> > + - description: MTU2.TGRA input capture/compare match
> > + - description: MTU2.TGRB input capture/compare match
> > + - description: MTU2.TCNT overflow
> > + - description: MTU2.TCNT underflow
> > + - description: MTU3.TGRA input capture/compare match
> > + - description: MTU3.TGRB input capture/compare match
> > + - description: MTU3.TGRC input capture/compare match
> > + - description: MTU3.TGRD input capture/compare match
> > + - description: MTU3.TCNT overflow
> > + - description: MTU4.TGRA input capture/compare match
> > + - description: MTU4.TGRB input capture/compare match
> > + - description: MTU4.TGRC input capture/compare match
> > + - description: MTU4.TGRD input capture/compare match
> > + - description: MTU4.TCNT overflow/underflow
> > + - description: MTU5.TGRU input capture/compare match
> > + - description: MTU5.TGRV input capture/compare match
> > + - description: MTU5.TGRW input capture/compare match
> > + - description: MTU6.TGRA input capture/compare match
> > + - description: MTU6.TGRB input capture/compare match
> > + - description: MTU6.TGRC input capture/compare match
> > + - description: MTU6.TGRD input capture/compare match
> > + - description: MTU6.TCNT overflow
> > + - description: MTU7.TGRA input capture/compare match
> > + - description: MTU7.TGRB input capture/compare match
> > + - description: MTU7.TGRC input capture/compare match
> > + - description: MTU7.TGRD input capture/compare match
> > + - description: MTU7.TCNT overflow/underflow
> > + - description: MTU8.TGRA input capture/compare match
> > + - description: MTU8.TGRB input capture/compare match
> > + - description: MTU8.TGRC input capture/compare match
> > + - description: MTU8.TGRD input capture/compare match
> > + - description: MTU8.TCNT overflow
> > + - description: MTU8.TCNT underflow
> > +
> > + interrupt-names:
> > + items:
> > + - const: tgia0
> > + - const: tgib0
> > + - const: tgic0
> > + - const: tgid0
> > + - const: tgiv0
> > + - const: tgie0
> > + - const: tgif0
> > + - const: tgia1
> > + - const: tgib1
> > + - const: tgiv1
> > + - const: tgiu1
> > + - const: tgia2
> > + - const: tgib2
> > + - const: tgiv2
> > + - const: tgiu2
> > + - const: tgia3
> > + - const: tgib3
> > + - const: tgic3
> > + - const: tgid3
> > + - const: tgiv3
> > + - const: tgia4
> > + - const: tgib4
> > + - const: tgic4
> > + - const: tgid4
> > + - const: tgiv4
> > + - const: tgiu5
> > + - const: tgiv5
> > + - const: tgiw5
> > + - const: tgia6
> > + - const: tgib6
> > + - const: tgic6
> > + - const: tgid6
> > + - const: tgiv6
> > + - const: tgia7
> > + - const: tgib7
> > + - const: tgic7
> > + - const: tgid7
> > + - const: tgiv7
> > + - const: tgia8
> > + - const: tgib8
> > + - const: tgic8
> > + - const: tgid8
> > + - const: tgiv8
> > + - const: tgiu8
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + "#address-cells":
> > + const: 1
> > +
> > + "#size-cells":
> > + const: 0
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - interrupt-names
> > + - clocks
> > + - power-domains
> > + - resets
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + mtu3: timer@10001200 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "renesas,r9a07g044-mtu3", "renesas,rzg2l-mtu3";
> > + reg = <0x10001200 0xb00>;
> > + interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tgiv0", "tgie0",
> > + "tgif0",
> > + "tgia1", "tgib1", "tgiv1", "tgiu1",
> > + "tgia2", "tgib2", "tgiv2", "tgiu2",
> > + "tgia3", "tgib3", "tgic3", "tgid3", "tgiv3",
> > + "tgia4", "tgib4", "tgic4", "tgid4", "tgiv4",
> > + "tgiu5", "tgiv5", "tgiw5",
> > + "tgia6", "tgib6", "tgic6", "tgid6", "tgiv6",
> > + "tgia7", "tgib7", "tgic7", "tgid7", "tgiv7",
> > + "tgia8", "tgib8", "tgic8", "tgid8", "tgiv8", "tgiu8";
>
> Not sure you need to list all of the IRQs in the example.
You do, because that's what the schema says is valid.
Rob
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH RFC 1/7] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-09-30 17:47 ` Rob Herring
@ 2022-10-03 7:34 ` Lee Jones
2022-10-03 7:38 ` Geert Uytterhoeven
0 siblings, 1 reply; 28+ messages in thread
From: Lee Jones @ 2022-10-03 7:34 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Krzysztof Kozlowski, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
On Fri, 30 Sep 2022, Rob Herring wrote:
> On Thu, Sep 29, 2022 at 06:53:49PM +0100, Lee Jones wrote:
> > On Thu, 29 Sep 2022, Biju Das wrote:
> >
> > > The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
> > > the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
> > > channels and one 32-bit timer channel. It supports the following
> > > functions
> > > - Counter
> > > - Timer
> > > - PWM
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > > It is same as [1]. Just sending this patch to avoid any bot error for
> > > the subsequent patches.
> > > [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220926132114.60396-3-biju.das.jz@bp.renesas.com/
> > > ---
> > > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 275 ++++++++++++++++++
> > > 1 file changed, 275 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > > new file mode 100644
> > > index 000000000000..c1fae8e8d9f9
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > > @@ -0,0 +1,275 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/mfd/renesas,rzg2l-mtu3.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a) bindings
> > > +
> > > +maintainers:
> > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > +
> > > +description: |
> > > + This hardware block pconsisting of eight 16-bit timer channels and one
> > > + 32- bit timer channel. It supports the following specifications:
> > > + - Pulse input/output: 28 lines max.
> > > + - Pulse input 3 lines
> > > + - Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks
> > > + for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
> > > + (when LWA = 1))
> > > + - Operating frequency Up to 100 MHz
> > > + - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
> > > + - Waveform output on compare match
> > > + - Input capture function (noise filter setting available)
> > > + - Counter-clearing operation
> > > + - Simultaneous writing to multiple timer counters (TCNT)
> > > + (excluding MTU8).
> > > + - Simultaneous clearing on compare match or input capture
> > > + (excluding MTU8).
> > > + - Simultaneous input and output to registers in synchronization with
> > > + counter operations (excluding MTU8).
> > > + - Up to 12-phase PWM output in combination with synchronous operation
> > > + (excluding MTU8)
> > > + - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
> > > + - Buffer operation specifiable
> > > + - [MTU1, MTU2]
> > > + - Phase counting mode can be specified independently
> > > + - 32-bit phase counting mode can be specified for interlocked operation
> > > + of MTU1 and MTU2 (when TMDR3.LWA = 1)
> > > + - Cascade connection operation available
> > > + - [MTU3, MTU4, MTU6, and MTU7]
> > > + - Through interlocked operation of MTU3/4 and MTU6/7, the positive and
> > > + negative signals in six phases (12 phases in total) can be output in
> > > + complementary PWM and reset-synchronized PWM operation.
> > > + - In complementary PWM mode, values can be transferred from buffer
> > > + registers to temporary registers at crests and troughs of the timer-
> > > + counter values or when the buffer registers (TGRD registers in MTU4
> > > + and MTU7) are written to.
> > > + - Double-buffering selectable in complementary PWM mode.
> > > + - [MTU3 and MTU4]
> > > + - Through interlocking with MTU0, a mode for driving AC synchronous
> > > + motors (brushless DC motors) by using complementary PWM output and
> > > + reset-synchronized PWM output is settable and allows the selection
> > > + of two types of waveform output (chopping or level).
> > > + - [MTU5]
> > > + - Capable of operation as a dead-time compensation counter.
> > > + - [MTU0/MTU5, MTU1, MTU2, and MTU8]
> > > + - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
> > > + through interlocked operation with MTU0/MTU5 and MTU8.
> > > + - Interrupt-skipping function
> > > + - In complementary PWM mode, interrupts on crests and troughs of counter
> > > + values and triggers to start conversion by the A/D converter can be
> > > + skipped.
> > > + - Interrupt sources: 43 sources.
> > > + - Buffer operation:
> > > + - Automatic transfer of register data (transfer from the buffer
> > > + register to the timer register).
> > > + - Trigger generation
> > > + - A/D converter start triggers can be generated
> > > + - A/D converter start request delaying function enables A/D converter
> > > + to be started with any desired timing and to be synchronized with
> > > + PWM output.
> > > + - Low power consumption function
> > > + - The MTU3a can be placed in the module-stop state.
> > > +
> > > +properties:
> > > + compatible:
> > > + items:
> > > + - enum:
> > > + - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
> > > + - renesas,r9a07g054-mtu3 # RZ/V2L
> > > + - const: renesas,rzg2l-mtu3
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + interrupts:
> > > + items:
> > > + - description: MTU0.TGRA input capture/compare match
> > > + - description: MTU0.TGRB input capture/compare match
> > > + - description: MTU0.TGRC input capture/compare match
> > > + - description: MTU0.TGRD input capture/compare match
> > > + - description: MTU0.TCNT overflow
> > > + - description: MTU0.TGRE compare match
> > > + - description: MTU0.TGRF compare match
> > > + - description: MTU1.TGRA input capture/compare match
> > > + - description: MTU1.TGRB input capture/compare match
> > > + - description: MTU1.TCNT overflow
> > > + - description: MTU1.TCNT underflow
> > > + - description: MTU2.TGRA input capture/compare match
> > > + - description: MTU2.TGRB input capture/compare match
> > > + - description: MTU2.TCNT overflow
> > > + - description: MTU2.TCNT underflow
> > > + - description: MTU3.TGRA input capture/compare match
> > > + - description: MTU3.TGRB input capture/compare match
> > > + - description: MTU3.TGRC input capture/compare match
> > > + - description: MTU3.TGRD input capture/compare match
> > > + - description: MTU3.TCNT overflow
> > > + - description: MTU4.TGRA input capture/compare match
> > > + - description: MTU4.TGRB input capture/compare match
> > > + - description: MTU4.TGRC input capture/compare match
> > > + - description: MTU4.TGRD input capture/compare match
> > > + - description: MTU4.TCNT overflow/underflow
> > > + - description: MTU5.TGRU input capture/compare match
> > > + - description: MTU5.TGRV input capture/compare match
> > > + - description: MTU5.TGRW input capture/compare match
> > > + - description: MTU6.TGRA input capture/compare match
> > > + - description: MTU6.TGRB input capture/compare match
> > > + - description: MTU6.TGRC input capture/compare match
> > > + - description: MTU6.TGRD input capture/compare match
> > > + - description: MTU6.TCNT overflow
> > > + - description: MTU7.TGRA input capture/compare match
> > > + - description: MTU7.TGRB input capture/compare match
> > > + - description: MTU7.TGRC input capture/compare match
> > > + - description: MTU7.TGRD input capture/compare match
> > > + - description: MTU7.TCNT overflow/underflow
> > > + - description: MTU8.TGRA input capture/compare match
> > > + - description: MTU8.TGRB input capture/compare match
> > > + - description: MTU8.TGRC input capture/compare match
> > > + - description: MTU8.TGRD input capture/compare match
> > > + - description: MTU8.TCNT overflow
> > > + - description: MTU8.TCNT underflow
> > > +
> > > + interrupt-names:
> > > + items:
> > > + - const: tgia0
> > > + - const: tgib0
> > > + - const: tgic0
> > > + - const: tgid0
> > > + - const: tgiv0
> > > + - const: tgie0
> > > + - const: tgif0
> > > + - const: tgia1
> > > + - const: tgib1
> > > + - const: tgiv1
> > > + - const: tgiu1
> > > + - const: tgia2
> > > + - const: tgib2
> > > + - const: tgiv2
> > > + - const: tgiu2
> > > + - const: tgia3
> > > + - const: tgib3
> > > + - const: tgic3
> > > + - const: tgid3
> > > + - const: tgiv3
> > > + - const: tgia4
> > > + - const: tgib4
> > > + - const: tgic4
> > > + - const: tgid4
> > > + - const: tgiv4
> > > + - const: tgiu5
> > > + - const: tgiv5
> > > + - const: tgiw5
> > > + - const: tgia6
> > > + - const: tgib6
> > > + - const: tgic6
> > > + - const: tgid6
> > > + - const: tgiv6
> > > + - const: tgia7
> > > + - const: tgib7
> > > + - const: tgic7
> > > + - const: tgid7
> > > + - const: tgiv7
> > > + - const: tgia8
> > > + - const: tgib8
> > > + - const: tgic8
> > > + - const: tgid8
> > > + - const: tgiv8
> > > + - const: tgiu8
> > > +
> > > + clocks:
> > > + maxItems: 1
> > > +
> > > + power-domains:
> > > + maxItems: 1
> > > +
> > > + resets:
> > > + maxItems: 1
> > > +
> > > + "#address-cells":
> > > + const: 1
> > > +
> > > + "#size-cells":
> > > + const: 0
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - interrupts
> > > + - interrupt-names
> > > + - clocks
> > > + - power-domains
> > > + - resets
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +
> > > + mtu3: timer@10001200 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "renesas,r9a07g044-mtu3", "renesas,rzg2l-mtu3";
> > > + reg = <0x10001200 0xb00>;
> > > + interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
> > > + <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
> > > + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tgiv0", "tgie0",
> > > + "tgif0",
> > > + "tgia1", "tgib1", "tgiv1", "tgiu1",
> > > + "tgia2", "tgib2", "tgiv2", "tgiu2",
> > > + "tgia3", "tgib3", "tgic3", "tgid3", "tgiv3",
> > > + "tgia4", "tgib4", "tgic4", "tgid4", "tgiv4",
> > > + "tgiu5", "tgiv5", "tgiw5",
> > > + "tgia6", "tgib6", "tgic6", "tgid6", "tgiv6",
> > > + "tgia7", "tgib7", "tgic7", "tgid7", "tgiv7",
> > > + "tgia8", "tgib8", "tgic8", "tgid8", "tgiv8", "tgiu8";
> >
> > Not sure you need to list all of the IRQs in the example.
>
> You do, because that's what the schema says is valid.
You have to use the exhaustive list?
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH RFC 1/7] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-10-03 7:34 ` Lee Jones
@ 2022-10-03 7:38 ` Geert Uytterhoeven
2022-10-03 8:51 ` Lee Jones
0 siblings, 1 reply; 28+ messages in thread
From: Geert Uytterhoeven @ 2022-10-03 7:38 UTC (permalink / raw)
To: Lee Jones
Cc: Rob Herring, Biju Das, Krzysztof Kozlowski, devicetree,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Lee,
On Mon, Oct 3, 2022 at 9:34 AM Lee Jones <lee@kernel.org> wrote:
> On Fri, 30 Sep 2022, Rob Herring wrote:
> > On Thu, Sep 29, 2022 at 06:53:49PM +0100, Lee Jones wrote:
> > > On Thu, 29 Sep 2022, Biju Das wrote:
> > >
> > > > The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
> > > > the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
> > > > channels and one 32-bit timer channel. It supports the following
> > > > functions
> > > > - Counter
> > > > - Timer
> > > > - PWM
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Not sure you need to list all of the IRQs in the example.
> >
> > You do, because that's what the schema says is valid.
>
> You have to use the exhaustive list?
Yes, else "make dt_binding_check" fails to validate the example,
as the schema says all interrupts must be present.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH RFC 1/7] dt-bindings: mfd: Document RZ/G2L MTU3a bindings
2022-10-03 7:38 ` Geert Uytterhoeven
@ 2022-10-03 8:51 ` Lee Jones
0 siblings, 0 replies; 28+ messages in thread
From: Lee Jones @ 2022-10-03 8:51 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Biju Das, Krzysztof Kozlowski, devicetree,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
On Mon, 03 Oct 2022, Geert Uytterhoeven wrote:
> Hi Lee,
>
> On Mon, Oct 3, 2022 at 9:34 AM Lee Jones <lee@kernel.org> wrote:
> > On Fri, 30 Sep 2022, Rob Herring wrote:
> > > On Thu, Sep 29, 2022 at 06:53:49PM +0100, Lee Jones wrote:
> > > > On Thu, 29 Sep 2022, Biju Das wrote:
> > > >
> > > > > The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
> > > > > the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
> > > > > channels and one 32-bit timer channel. It supports the following
> > > > > functions
> > > > > - Counter
> > > > > - Timer
> > > > > - PWM
> > > > >
> > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>
> > > > Not sure you need to list all of the IRQs in the example.
> > >
> > > You do, because that's what the schema says is valid.
> >
> > You have to use the exhaustive list?
>
> Yes, else "make dt_binding_check" fails to validate the example,
> as the schema says all interrupts must be present.
Okay, so all of those IRQs are compulsory?
Makes sense then, thanks for the clarification.
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2L MTU3 counter
2022-09-29 10:30 [PATCH RFC 0/7] Add RZ/G2L MTU3 PWM driver Biju Das
2022-09-29 10:30 ` [PATCH RFC 1/7] dt-bindings: mfd: Document RZ/G2L MTU3a bindings Biju Das
@ 2022-09-29 10:30 ` Biju Das
2022-09-29 17:52 ` Lee Jones
2022-09-30 19:03 ` Rob Herring
2022-09-29 10:30 ` [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM Biju Das
` (4 subsequent siblings)
6 siblings, 2 replies; 28+ messages in thread
From: Biju Das @ 2022-09-29 10:30 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Lee Jones, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
Document 16-bit and 32-bit phase counting mode support on
RZ/G2L MTU3 IP.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
* Updated commit header.
---
.../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35 +++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
index c1fae8e8d9f9..c4bcf28623d6 100644
--- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
+++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
@@ -192,6 +192,37 @@ properties:
"#size-cells":
const: 0
+patternProperties:
+ "^counter@[1-2]+$":
+ type: object
+
+ properties:
+ compatible:
+ const: renesas,rzg2l-mtu3-counter
+
+ reg:
+ description: Identify counter channels.
+ items:
+ enum: [ 1, 2 ]
+
+ renesas,32bit-phase-counting:
+ type: boolean
+ description: Enable 32-bit phase counting mode.
+
+ renesas,ext-input-phase-clock-select:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1 ]
+ default: 1
+ description: |
+ Selects the external clock pin for phase counting mode.
+ <0> : MTCLKA and MTCLKB are selected for the external phase clock.
+ <1> : MTCLKC and MTCLKD are selected for the external phase clock
+ (default)
+
+ required:
+ - compatible
+ - reg
+
required:
- compatible
- reg
@@ -270,6 +301,10 @@ examples:
clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
+ counter@1 {
+ compatible = "renesas,rzg2l-mtu3-counter";
+ reg = <1>;
+ };
};
...
--
2.25.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2L MTU3 counter
2022-09-29 10:30 ` [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2L MTU3 counter Biju Das
@ 2022-09-29 17:52 ` Lee Jones
2022-09-30 19:03 ` Rob Herring
1 sibling, 0 replies; 28+ messages in thread
From: Lee Jones @ 2022-09-29 17:52 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
On Thu, 29 Sep 2022, Biju Das wrote:
> Document 16-bit and 32-bit phase counting mode support on
> RZ/G2L MTU3 IP.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> * Updated commit header.
> ---
> .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35 +++++++++++++++++++
> 1 file changed, 35 insertions(+)
Counter binding?
> diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> index c1fae8e8d9f9..c4bcf28623d6 100644
> --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> @@ -192,6 +192,37 @@ properties:
> "#size-cells":
> const: 0
>
> +patternProperties:
> + "^counter@[1-2]+$":
> + type: object
> +
> + properties:
> + compatible:
> + const: renesas,rzg2l-mtu3-counter
> +
> + reg:
> + description: Identify counter channels.
> + items:
> + enum: [ 1, 2 ]
> +
> + renesas,32bit-phase-counting:
> + type: boolean
> + description: Enable 32-bit phase counting mode.
> +
> + renesas,ext-input-phase-clock-select:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [ 0, 1 ]
> + default: 1
> + description: |
> + Selects the external clock pin for phase counting mode.
> + <0> : MTCLKA and MTCLKB are selected for the external phase clock.
> + <1> : MTCLKC and MTCLKD are selected for the external phase clock
> + (default)
> +
> + required:
> + - compatible
> + - reg
> +
> required:
> - compatible
> - reg
> @@ -270,6 +301,10 @@ examples:
> clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
> power-domains = <&cpg>;
> resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
> + counter@1 {
> + compatible = "renesas,rzg2l-mtu3-counter";
> + reg = <1>;
> + };
> };
>
> ...
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2L MTU3 counter
2022-09-29 10:30 ` [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2L MTU3 counter Biju Das
2022-09-29 17:52 ` Lee Jones
@ 2022-09-30 19:03 ` Rob Herring
2022-10-01 16:36 ` Biju Das
1 sibling, 1 reply; 28+ messages in thread
From: Rob Herring @ 2022-09-30 19:03 UTC (permalink / raw)
To: Biju Das
Cc: Krzysztof Kozlowski, Lee Jones, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
On Thu, Sep 29, 2022 at 11:30:38AM +0100, Biju Das wrote:
> Document 16-bit and 32-bit phase counting mode support on
> RZ/G2L MTU3 IP.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> * Updated commit header.
> ---
> .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35 +++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> index c1fae8e8d9f9..c4bcf28623d6 100644
> --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> @@ -192,6 +192,37 @@ properties:
> "#size-cells":
> const: 0
>
> +patternProperties:
> + "^counter@[1-2]+$":
> + type: object
> +
> + properties:
> + compatible:
> + const: renesas,rzg2l-mtu3-counter
> +
> + reg:
> + description: Identify counter channels.
> + items:
> + enum: [ 1, 2 ]
> +
> + renesas,32bit-phase-counting:
> + type: boolean
> + description: Enable 32-bit phase counting mode.
> +
> + renesas,ext-input-phase-clock-select:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [ 0, 1 ]
> + default: 1
> + description: |
> + Selects the external clock pin for phase counting mode.
> + <0> : MTCLKA and MTCLKB are selected for the external phase clock.
> + <1> : MTCLKC and MTCLKD are selected for the external phase clock
> + (default)
Why do these belong in DT?
> +
> + required:
> + - compatible
> + - reg
> +
> required:
> - compatible
> - reg
> @@ -270,6 +301,10 @@ examples:
> clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
> power-domains = <&cpg>;
> resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
> + counter@1 {
> + compatible = "renesas,rzg2l-mtu3-counter";
> + reg = <1>;
> + };
> };
>
> ...
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 28+ messages in thread* RE: [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2L MTU3 counter
2022-09-30 19:03 ` Rob Herring
@ 2022-10-01 16:36 ` Biju Das
2022-10-02 16:50 ` Biju Das
0 siblings, 1 reply; 28+ messages in thread
From: Biju Das @ 2022-10-01 16:36 UTC (permalink / raw)
To: Rob Herring
Cc: Krzysztof Kozlowski, Lee Jones, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
Hi Rob,
Thanks for the feedback.
> Subject: Re: [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document
> RZ/G2L MTU3 counter
>
> On Thu, Sep 29, 2022 at 11:30:38AM +0100, Biju Das wrote:
> > Document 16-bit and 32-bit phase counting mode support on RZ/G2L
> MTU3
> > IP.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > * Updated commit header.
> > ---
> > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35
> +++++++++++++++++++
> > 1 file changed, 35 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > index c1fae8e8d9f9..c4bcf28623d6 100644
> > --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > @@ -192,6 +192,37 @@ properties:
> > "#size-cells":
> > const: 0
> >
> > +patternProperties:
> > + "^counter@[1-2]+$":
> > + type: object
> > +
> > + properties:
> > + compatible:
> > + const: renesas,rzg2l-mtu3-counter
> > +
> > + reg:
> > + description: Identify counter channels.
> > + items:
> > + enum: [ 1, 2 ]
> > +
> > + renesas,32bit-phase-counting:
> > + type: boolean
> > + description: Enable 32-bit phase counting mode.
> > +
> > + renesas,ext-input-phase-clock-select:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [ 0, 1 ]
> > + default: 1
> > + description: |
> > + Selects the external clock pin for phase counting mode.
> > + <0> : MTCLKA and MTCLKB are selected for the external
> phase clock.
> > + <1> : MTCLKC and MTCLKD are selected for the external
> phase clock
> > + (default)
>
> Why do these belong in DT?
Hardware supports 4 pins for phase counting mode,
MTCLKA Input External clock A input pin (MTU1/MTU2 phase counting mode A phase input)
MTCLKB Input External clock B input pin (MTU1/MTU2 phase counting mode B phase input)
MTCLKC Input External clock C input pin (MTU2 phase counting mode A phase input)
MTCLKD Input External clock D input pin (MTU2 phase counting mode B phase input)
For MTU1, it is fixed MTCLKA and MTCLKB.
But for MTU2, it can be either 0-{ MTCLKA, MTCLKB} or 1 - { MTCLKC , MTCLKD}
On reset it is set to { MTCLKC , MTCLKD}.
If user want to change based on board design, they can use this property.
Otherwise, runtime using sysfs. If sysfs, do we need to document here?
Cheers,
Biju
>
>
> > +
> > + required:
> > + - compatible
> > + - reg
> > +
> > required:
> > - compatible
> > - reg
> > @@ -270,6 +301,10 @@ examples:
> > clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
> > power-domains = <&cpg>;
> > resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
> > + counter@1 {
> > + compatible = "renesas,rzg2l-mtu3-counter";
> > + reg = <1>;
> > + };
> > };
> >
> > ...
> > --
> > 2.25.1
> >
> >
^ permalink raw reply [flat|nested] 28+ messages in thread* RE: [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2L MTU3 counter
2022-10-01 16:36 ` Biju Das
@ 2022-10-02 16:50 ` Biju Das
0 siblings, 0 replies; 28+ messages in thread
From: Biju Das @ 2022-10-02 16:50 UTC (permalink / raw)
To: Rob Herring
Cc: Krzysztof Kozlowski, Lee Jones, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc, William Breathitt Gray
Hi Rob,
> Subject: RE: [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document
> RZ/G2L MTU3 counter
>
> Hi Rob,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document
> > RZ/G2L MTU3 counter
> >
> > On Thu, Sep 29, 2022 at 11:30:38AM +0100, Biju Das wrote:
> > > Document 16-bit and 32-bit phase counting mode support on RZ/G2L
> > MTU3
> > > IP.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > > * Updated commit header.
> > > ---
> > > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35
> > +++++++++++++++++++
> > > 1 file changed, 35 insertions(+)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > > b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > > index c1fae8e8d9f9..c4bcf28623d6 100644
> > > --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-
> mtu3.yaml
> > > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-
> mtu3.yaml
> > > @@ -192,6 +192,37 @@ properties:
> > > "#size-cells":
> > > const: 0
> > >
> > > +patternProperties:
> > > + "^counter@[1-2]+$":
> > > + type: object
> > > +
> > > + properties:
> > > + compatible:
> > > + const: renesas,rzg2l-mtu3-counter
> > > +
> > > + reg:
> > > + description: Identify counter channels.
> > > + items:
> > > + enum: [ 1, 2 ]
> > > +
> > > + renesas,32bit-phase-counting:
> > > + type: boolean
> > > + description: Enable 32-bit phase counting mode.
> > > +
> > > + renesas,ext-input-phase-clock-select:
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + enum: [ 0, 1 ]
> > > + default: 1
> > > + description: |
> > > + Selects the external clock pin for phase counting mode.
> > > + <0> : MTCLKA and MTCLKB are selected for the external
> > phase clock.
> > > + <1> : MTCLKC and MTCLKD are selected for the external
> > phase clock
> > > + (default)
> >
> > Why do these belong in DT?
>
> Hardware supports 4 pins for phase counting mode,
>
> MTCLKA Input External clock A input pin (MTU1/MTU2 phase counting mode
> A phase input) MTCLKB Input External clock B input pin (MTU1/MTU2
> phase counting mode B phase input) MTCLKC Input External clock C input
> pin (MTU2 phase counting mode A phase input) MTCLKD Input External
> clock D input pin (MTU2 phase counting mode B phase input)
>
> For MTU1, it is fixed MTCLKA and MTCLKB.
> But for MTU2, it can be either 0-{ MTCLKA, MTCLKB} or 1 - { MTCLKC ,
> MTCLKD} On reset it is set to { MTCLKC , MTCLKD}.
>
> If user want to change based on board design, they can use this
> property.
> Otherwise, runtime using sysfs. If sysfs, do we need to document here?
As per [1], it is going to be modelled as
counter:
type: object
properties:
compatible:
const: renesas,rzg2l-mtu3-counter
With the following counters taken care internally.
count0 :- MTU1 (16-bit phase counting mode)
count1 :- MTU2 (16-bit phase counting mode)
count2 :- MTU1 + MTU2 (32-bit phase counting mode)
and there will be a sysfs property for Selecting the external clock pin for phase counting mode.
Is it ok for you?
[1]
https://lore.kernel.org/linux-renesas-soc/OS0PR01MB59223F69EA3215528519F49086599@OS0PR01MB5922.jpnprd01.prod.outlook.com/T/#m1ee6f933603c7acd480d7652d1ec2e0d9858c842
Cheers,
Biju
>
>
> >
> >
> > > +
> > > + required:
> > > + - compatible
> > > + - reg
> > > +
> > > required:
> > > - compatible
> > > - reg
> > > @@ -270,6 +301,10 @@ examples:
> > > clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
> > > power-domains = <&cpg>;
> > > resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
> > > + counter@1 {
> > > + compatible = "renesas,rzg2l-mtu3-counter";
> > > + reg = <1>;
> > > + };
> > > };
> > >
> > > ...
> > > --
> > > 2.25.1
> > >
> > >
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM
2022-09-29 10:30 [PATCH RFC 0/7] Add RZ/G2L MTU3 PWM driver Biju Das
2022-09-29 10:30 ` [PATCH RFC 1/7] dt-bindings: mfd: Document RZ/G2L MTU3a bindings Biju Das
2022-09-29 10:30 ` [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2L MTU3 counter Biju Das
@ 2022-09-29 10:30 ` Biju Das
2022-09-29 17:52 ` Lee Jones
2022-09-30 18:35 ` Rob Herring
2022-09-29 10:30 ` [PATCH RFC 4/7] pwm: Add support for " Biju Das
` (3 subsequent siblings)
6 siblings, 2 replies; 28+ messages in thread
From: Biju Das @ 2022-09-29 10:30 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Thierry Reding
Cc: Biju Das, Lee Jones, Uwe Kleine-König, linux-pwm,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Document RZ/G2L MTU3 PWM support. It supports following pwm modes.
1) PWM mode 1
2) PWM mode 2
3) Reset-synchronized PWM mode
4) Complementary PWM mode 1 (transfer at crest)
5) Complementary PWM mode 2 (transfer at trough)
6) Complementary PWM mode 3 (transfer at crest and trough)
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../bindings/mfd/renesas,rzg2l-mtu3.yaml | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
index c4bcf28623d6..362fedf5bedb 100644
--- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
+++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
@@ -223,6 +223,50 @@ patternProperties:
- compatible
- reg
+ "^pwm@([0-4]|[6-7])+$":
+ type: object
+
+ properties:
+ compatible:
+ const: renesas,rz-mtu3-pwm
+
+ reg:
+ description: Identify pwm channels.
+ items:
+ enum: [ 0, 1, 2, 3, 4, 6, 7 ]
+
+ "#pwm-cells":
+ const: 2
+
+ renesas,pwm-mode1:
+ type: boolean
+ description: Enable PWM mode 1.
+
+ renesas,pwm-mode2:
+ type: boolean
+ description: Enable PWM mode 2.
+
+ renesas,reset-synchronized-pwm-mode:
+ type: boolean
+ description: Enable Reset-synchronized PWM mode.
+
+ renesas,complementary-pwm-mode1:
+ type: boolean
+ description: Complementary PWM mode 1 (transfer at crest).
+
+ renesas,complementary-pwm-mode2:
+ type: boolean
+ description: Complementary PWM mode 2 (transfer at trough).
+
+ renesas,complementary-pwm-mode3:
+ type: boolean
+ description: Complementary PWM mode 3 (transfer at crest and trough).
+
+ required:
+ - compatible
+ - reg
+ - "#pwm-cells"
+
required:
- compatible
- reg
@@ -305,6 +349,12 @@ examples:
compatible = "renesas,rzg2l-mtu3-counter";
reg = <1>;
};
+ pwm@3 {
+ compatible = "renesas,rz-mtu3-pwm";
+ reg = <3>;
+ #pwm-cells = <2>;
+ renesas,pwm-mode1;
+ };
};
...
--
2.25.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM
2022-09-29 10:30 ` [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM Biju Das
@ 2022-09-29 17:52 ` Lee Jones
2022-09-29 17:59 ` Biju Das
2022-09-30 18:35 ` Rob Herring
1 sibling, 1 reply; 28+ messages in thread
From: Lee Jones @ 2022-09-29 17:52 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Thierry Reding,
Uwe Kleine-König, linux-pwm, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
On Thu, 29 Sep 2022, Biju Das wrote:
> Document RZ/G2L MTU3 PWM support. It supports following pwm modes.
> 1) PWM mode 1
> 2) PWM mode 2
> 3) Reset-synchronized PWM mode
> 4) Complementary PWM mode 1 (transfer at crest)
> 5) Complementary PWM mode 2 (transfer at trough)
> 6) Complementary PWM mode 3 (transfer at crest and trough)
Shouldn't all this go in the PWM driver binding?
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 50 +++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> index c4bcf28623d6..362fedf5bedb 100644
> --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> @@ -223,6 +223,50 @@ patternProperties:
> - compatible
> - reg
>
> + "^pwm@([0-4]|[6-7])+$":
> + type: object
> +
> + properties:
> + compatible:
> + const: renesas,rz-mtu3-pwm
> +
> + reg:
> + description: Identify pwm channels.
> + items:
> + enum: [ 0, 1, 2, 3, 4, 6, 7 ]
> +
> + "#pwm-cells":
> + const: 2
> +
> + renesas,pwm-mode1:
> + type: boolean
> + description: Enable PWM mode 1.
> +
> + renesas,pwm-mode2:
> + type: boolean
> + description: Enable PWM mode 2.
> +
> + renesas,reset-synchronized-pwm-mode:
> + type: boolean
> + description: Enable Reset-synchronized PWM mode.
> +
> + renesas,complementary-pwm-mode1:
> + type: boolean
> + description: Complementary PWM mode 1 (transfer at crest).
> +
> + renesas,complementary-pwm-mode2:
> + type: boolean
> + description: Complementary PWM mode 2 (transfer at trough).
> +
> + renesas,complementary-pwm-mode3:
> + type: boolean
> + description: Complementary PWM mode 3 (transfer at crest and trough).
> +
> + required:
> + - compatible
> + - reg
> + - "#pwm-cells"
> +
> required:
> - compatible
> - reg
> @@ -305,6 +349,12 @@ examples:
> compatible = "renesas,rzg2l-mtu3-counter";
> reg = <1>;
> };
> + pwm@3 {
> + compatible = "renesas,rz-mtu3-pwm";
> + reg = <3>;
> + #pwm-cells = <2>;
> + renesas,pwm-mode1;
> + };
> };
>
> ...
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 28+ messages in thread* RE: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM
2022-09-29 17:52 ` Lee Jones
@ 2022-09-29 17:59 ` Biju Das
2022-09-30 12:10 ` Lee Jones
0 siblings, 1 reply; 28+ messages in thread
From: Biju Das @ 2022-09-29 17:59 UTC (permalink / raw)
To: Lee Jones
Cc: Rob Herring, Krzysztof Kozlowski, Thierry Reding,
Uwe Kleine-König, linux-pwm, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
Hi Lee Jones,
Thanks for the feedback.
> Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> RZ/G2L MTU3 PWM
>
> On Thu, 29 Sep 2022, Biju Das wrote:
>
> > Document RZ/G2L MTU3 PWM support. It supports following pwm modes.
> > 1) PWM mode 1
> > 2) PWM mode 2
> > 3) Reset-synchronized PWM mode
> > 4) Complementary PWM mode 1 (transfer at crest)
> > 5) Complementary PWM mode 2 (transfer at trough)
> > 6) Complementary PWM mode 3 (transfer at crest and trough)
>
> Shouldn't all this go in the PWM driver binding?
Looks like at top level MTU3 IP provides similar HW functionality like below
binding [1], where there is a core MFD driver and pwm, counter and timer
as child devices.
[1] https://elixir.bootlin.com/linux/v6.0-rc7/source/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
Cheers,
Biju
>
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 50
> +++++++++++++++++++
> > 1 file changed, 50 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-
> mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-
> mtu3.yaml
> > index c4bcf28623d6..362fedf5bedb 100644
> > --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > @@ -223,6 +223,50 @@ patternProperties:
> > - compatible
> > - reg
> >
> > + "^pwm@([0-4]|[6-7])+$":
> > + type: object
> > +
> > + properties:
> > + compatible:
> > + const: renesas,rz-mtu3-pwm
> > +
> > + reg:
> > + description: Identify pwm channels.
> > + items:
> > + enum: [ 0, 1, 2, 3, 4, 6, 7 ]
> > +
> > + "#pwm-cells":
> > + const: 2
> > +
> > + renesas,pwm-mode1:
> > + type: boolean
> > + description: Enable PWM mode 1.
> > +
> > + renesas,pwm-mode2:
> > + type: boolean
> > + description: Enable PWM mode 2.
> > +
> > + renesas,reset-synchronized-pwm-mode:
> > + type: boolean
> > + description: Enable Reset-synchronized PWM mode.
> > +
> > + renesas,complementary-pwm-mode1:
> > + type: boolean
> > + description: Complementary PWM mode 1 (transfer at crest).
> > +
> > + renesas,complementary-pwm-mode2:
> > + type: boolean
> > + description: Complementary PWM mode 2 (transfer at trough).
> > +
> > + renesas,complementary-pwm-mode3:
> > + type: boolean
> > + description: Complementary PWM mode 3 (transfer at crest
> and trough).
> > +
> > + required:
> > + - compatible
> > + - reg
> > + - "#pwm-cells"
> > +
> > required:
> > - compatible
> > - reg
> > @@ -305,6 +349,12 @@ examples:
> > compatible = "renesas,rzg2l-mtu3-counter";
> > reg = <1>;
> > };
> > + pwm@3 {
> > + compatible = "renesas,rz-mtu3-pwm";
> > + reg = <3>;
> > + #pwm-cells = <2>;
> > + renesas,pwm-mode1;
> > + };
> > };
> >
> > ...
>
> --
> Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM
2022-09-29 17:59 ` Biju Das
@ 2022-09-30 12:10 ` Lee Jones
2022-10-01 19:26 ` Biju Das
0 siblings, 1 reply; 28+ messages in thread
From: Lee Jones @ 2022-09-30 12:10 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Thierry Reding,
Uwe Kleine-König, linux-pwm, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
On Thu, 29 Sep 2022, Biju Das wrote:
> Hi Lee Jones,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> > RZ/G2L MTU3 PWM
> >
> > On Thu, 29 Sep 2022, Biju Das wrote:
> >
> > > Document RZ/G2L MTU3 PWM support. It supports following pwm modes.
> > > 1) PWM mode 1
> > > 2) PWM mode 2
> > > 3) Reset-synchronized PWM mode
> > > 4) Complementary PWM mode 1 (transfer at crest)
> > > 5) Complementary PWM mode 2 (transfer at trough)
> > > 6) Complementary PWM mode 3 (transfer at crest and trough)
> >
> > Shouldn't all this go in the PWM driver binding?
>
> Looks like at top level MTU3 IP provides similar HW functionality like below
> binding [1], where there is a core MFD driver and pwm, counter and timer
> as child devices.
Previous mistakes are not good references for what should happen in
the present and the future. =;)
> [1] https://elixir.bootlin.com/linux/v6.0-rc7/source/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
>
> Cheers,
> Biju
> >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 50
> > +++++++++++++++++++
> > > 1 file changed, 50 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-
> > mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-
> > mtu3.yaml
> > > index c4bcf28623d6..362fedf5bedb 100644
> > > --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > > @@ -223,6 +223,50 @@ patternProperties:
> > > - compatible
> > > - reg
> > >
> > > + "^pwm@([0-4]|[6-7])+$":
> > > + type: object
> > > +
> > > + properties:
> > > + compatible:
> > > + const: renesas,rz-mtu3-pwm
> > > +
> > > + reg:
> > > + description: Identify pwm channels.
> > > + items:
> > > + enum: [ 0, 1, 2, 3, 4, 6, 7 ]
> > > +
> > > + "#pwm-cells":
> > > + const: 2
> > > +
> > > + renesas,pwm-mode1:
> > > + type: boolean
> > > + description: Enable PWM mode 1.
> > > +
> > > + renesas,pwm-mode2:
> > > + type: boolean
> > > + description: Enable PWM mode 2.
> > > +
> > > + renesas,reset-synchronized-pwm-mode:
> > > + type: boolean
> > > + description: Enable Reset-synchronized PWM mode.
> > > +
> > > + renesas,complementary-pwm-mode1:
> > > + type: boolean
> > > + description: Complementary PWM mode 1 (transfer at crest).
> > > +
> > > + renesas,complementary-pwm-mode2:
> > > + type: boolean
> > > + description: Complementary PWM mode 2 (transfer at trough).
> > > +
> > > + renesas,complementary-pwm-mode3:
> > > + type: boolean
> > > + description: Complementary PWM mode 3 (transfer at crest
> > and trough).
> > > +
> > > + required:
> > > + - compatible
> > > + - reg
> > > + - "#pwm-cells"
> > > +
> > > required:
> > > - compatible
> > > - reg
> > > @@ -305,6 +349,12 @@ examples:
> > > compatible = "renesas,rzg2l-mtu3-counter";
> > > reg = <1>;
> > > };
> > > + pwm@3 {
> > > + compatible = "renesas,rz-mtu3-pwm";
> > > + reg = <3>;
> > > + #pwm-cells = <2>;
> > > + renesas,pwm-mode1;
> > > + };
> > > };
> > >
> > > ...
> >
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 28+ messages in thread* RE: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM
2022-09-30 12:10 ` Lee Jones
@ 2022-10-01 19:26 ` Biju Das
2022-10-03 7:32 ` Lee Jones
0 siblings, 1 reply; 28+ messages in thread
From: Biju Das @ 2022-10-01 19:26 UTC (permalink / raw)
To: Lee Jones
Cc: Rob Herring, Krzysztof Kozlowski, Thierry Reding,
Uwe Kleine-König, linux-pwm, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
Hi Lee Jones,
> Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> RZ/G2L MTU3 PWM
>
> On Thu, 29 Sep 2022, Biju Das wrote:
>
> > Hi Lee Jones,
> >
> > Thanks for the feedback.
> >
> > > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> > > RZ/G2L MTU3 PWM
> > >
> > > On Thu, 29 Sep 2022, Biju Das wrote:
> > >
> > > > Document RZ/G2L MTU3 PWM support. It supports following pwm
> modes.
> > > > 1) PWM mode 1
> > > > 2) PWM mode 2
> > > > 3) Reset-synchronized PWM mode
> > > > 4) Complementary PWM mode 1 (transfer at crest)
> > > > 5) Complementary PWM mode 2 (transfer at trough)
> > > > 6) Complementary PWM mode 3 (transfer at crest and trough)
> > >
> > > Shouldn't all this go in the PWM driver binding?
> >
> > Looks like at top level MTU3 IP provides similar HW functionality
> like
> > below binding [1], where there is a core MFD driver and pwm, counter
> > and timer as child devices.
>
> Previous mistakes are not good references for what should happen in
> the present and the future. =;)
Why do you think that reference is not a good one? I believe there
should be some reason for it.
Cheers,
Biju
>
> > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > ---
> > > > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 50
> > > +++++++++++++++++++
> > > > 1 file changed, 50 insertions(+)
> > > >
> > > > diff --git
> a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-
> > > mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-
> > > mtu3.yaml
> > > > index c4bcf28623d6..362fedf5bedb 100644
> > > > ---
> > > > a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > > > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-
> mtu3.yam
> > > > +++ l
> > > > @@ -223,6 +223,50 @@ patternProperties:
> > > > - compatible
> > > > - reg
> > > >
> > > > + "^pwm@([0-4]|[6-7])+$":
> > > > + type: object
> > > > +
> > > > + properties:
> > > > + compatible:
> > > > + const: renesas,rz-mtu3-pwm
> > > > +
> > > > + reg:
> > > > + description: Identify pwm channels.
> > > > + items:
> > > > + enum: [ 0, 1, 2, 3, 4, 6, 7 ]
> > > > +
> > > > + "#pwm-cells":
> > > > + const: 2
> > > > +
> > > > + renesas,pwm-mode1:
> > > > + type: boolean
> > > > + description: Enable PWM mode 1.
> > > > +
> > > > + renesas,pwm-mode2:
> > > > + type: boolean
> > > > + description: Enable PWM mode 2.
> > > > +
> > > > + renesas,reset-synchronized-pwm-mode:
> > > > + type: boolean
> > > > + description: Enable Reset-synchronized PWM mode.
> > > > +
> > > > + renesas,complementary-pwm-mode1:
> > > > + type: boolean
> > > > + description: Complementary PWM mode 1 (transfer at
> crest).
> > > > +
> > > > + renesas,complementary-pwm-mode2:
> > > > + type: boolean
> > > > + description: Complementary PWM mode 2 (transfer at
> trough).
> > > > +
> > > > + renesas,complementary-pwm-mode3:
> > > > + type: boolean
> > > > + description: Complementary PWM mode 3 (transfer at
> crest
> > > and trough).
> > > > +
> > > > + required:
> > > > + - compatible
> > > > + - reg
> > > > + - "#pwm-cells"
> > > > +
> > > > required:
> > > > - compatible
> > > > - reg
> > > > @@ -305,6 +349,12 @@ examples:
> > > > compatible = "renesas,rzg2l-mtu3-counter";
> > > > reg = <1>;
> > > > };
> > > > + pwm@3 {
> > > > + compatible = "renesas,rz-mtu3-pwm";
> > > > + reg = <3>;
> > > > + #pwm-cells = <2>;
> > > > + renesas,pwm-mode1;
> > > > + };
> > > > };
> > > >
> > > > ...
> > >
>
> --
> Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM
2022-10-01 19:26 ` Biju Das
@ 2022-10-03 7:32 ` Lee Jones
2022-10-03 8:16 ` Biju Das
0 siblings, 1 reply; 28+ messages in thread
From: Lee Jones @ 2022-10-03 7:32 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Thierry Reding,
Uwe Kleine-König, linux-pwm, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
On Sat, 01 Oct 2022, Biju Das wrote:
> Hi Lee Jones,
>
> > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> > RZ/G2L MTU3 PWM
> >
> > On Thu, 29 Sep 2022, Biju Das wrote:
> >
> > > Hi Lee Jones,
> > >
> > > Thanks for the feedback.
> > >
> > > > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> > > > RZ/G2L MTU3 PWM
> > > >
> > > > On Thu, 29 Sep 2022, Biju Das wrote:
> > > >
> > > > > Document RZ/G2L MTU3 PWM support. It supports following pwm
> > modes.
> > > > > 1) PWM mode 1
> > > > > 2) PWM mode 2
> > > > > 3) Reset-synchronized PWM mode
> > > > > 4) Complementary PWM mode 1 (transfer at crest)
> > > > > 5) Complementary PWM mode 2 (transfer at trough)
> > > > > 6) Complementary PWM mode 3 (transfer at crest and trough)
> > > >
> > > > Shouldn't all this go in the PWM driver binding?
> > >
> > > Looks like at top level MTU3 IP provides similar HW functionality
> > like
> > > below binding [1], where there is a core MFD driver and pwm, counter
> > > and timer as child devices.
> >
> > Previous mistakes are not good references for what should happen in
> > the present and the future. =;)
>
> Why do you think that reference is not a good one? I believe there
> should be some reason for it.
I didn't even look at it.
What I "believe" is that documentation for each functionality
belonging to a particular subsystem should live in subsystem's
associated documentation directory and be reviewed/maintained by that
subsystem's associated maintainer.
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM
2022-10-03 7:32 ` Lee Jones
@ 2022-10-03 8:16 ` Biju Das
2022-10-03 8:57 ` Lee Jones
0 siblings, 1 reply; 28+ messages in thread
From: Biju Das @ 2022-10-03 8:16 UTC (permalink / raw)
To: Lee Jones
Cc: Rob Herring, Krzysztof Kozlowski, Thierry Reding,
Uwe Kleine-König, linux-pwm, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
Hi Lee,
> Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> RZ/G2L MTU3 PWM
>
> On Sat, 01 Oct 2022, Biju Das wrote:
>
> > Hi Lee Jones,
> >
> > > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> > > RZ/G2L MTU3 PWM
> > >
> > > On Thu, 29 Sep 2022, Biju Das wrote:
> > >
> > > > Hi Lee Jones,
> > > >
> > > > Thanks for the feedback.
> > > >
> > > > > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3:
> Document
> > > > > RZ/G2L MTU3 PWM
> > > > >
> > > > > On Thu, 29 Sep 2022, Biju Das wrote:
> > > > >
> > > > > > Document RZ/G2L MTU3 PWM support. It supports following pwm
> > > modes.
> > > > > > 1) PWM mode 1
> > > > > > 2) PWM mode 2
> > > > > > 3) Reset-synchronized PWM mode
> > > > > > 4) Complementary PWM mode 1 (transfer at crest)
> > > > > > 5) Complementary PWM mode 2 (transfer at trough)
> > > > > > 6) Complementary PWM mode 3 (transfer at crest and trough)
> > > > >
> > > > > Shouldn't all this go in the PWM driver binding?
> > > >
> > > > Looks like at top level MTU3 IP provides similar HW
> functionality
> > > like
> > > > below binding [1], where there is a core MFD driver and pwm,
> > > > counter and timer as child devices.
> > >
> > > Previous mistakes are not good references for what should happen
> in
> > > the present and the future. =;)
> >
> > Why do you think that reference is not a good one? I believe there
> > should be some reason for it.
>
> I didn't even look at it.
>
> What I "believe" is that documentation for each functionality
> belonging to a particular subsystem should live in subsystem's
> associated documentation directory and be reviewed/maintained by that
> subsystem's associated maintainer.
If I am correct, MFD is subsystem for calling shared resources
across subsystems.
Here shared resources are channels which is shared by timer, counter and pwm
They are child objects of MFD subsystems. That is the reason it is in MFDndings.
Cheers,
Biju
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM
2022-10-03 8:16 ` Biju Das
@ 2022-10-03 8:57 ` Lee Jones
2022-10-03 9:04 ` Biju Das
0 siblings, 1 reply; 28+ messages in thread
From: Lee Jones @ 2022-10-03 8:57 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Thierry Reding,
Uwe Kleine-König, linux-pwm, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
On Mon, 03 Oct 2022, Biju Das wrote:
> Hi Lee,
>
> > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> > RZ/G2L MTU3 PWM
> >
> > On Sat, 01 Oct 2022, Biju Das wrote:
> >
> > > Hi Lee Jones,
> > >
> > > > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> > > > RZ/G2L MTU3 PWM
> > > >
> > > > On Thu, 29 Sep 2022, Biju Das wrote:
> > > >
> > > > > Hi Lee Jones,
> > > > >
> > > > > Thanks for the feedback.
> > > > >
> > > > > > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3:
> > Document
> > > > > > RZ/G2L MTU3 PWM
> > > > > >
> > > > > > On Thu, 29 Sep 2022, Biju Das wrote:
> > > > > >
> > > > > > > Document RZ/G2L MTU3 PWM support. It supports following pwm
> > > > modes.
> > > > > > > 1) PWM mode 1
> > > > > > > 2) PWM mode 2
> > > > > > > 3) Reset-synchronized PWM mode
> > > > > > > 4) Complementary PWM mode 1 (transfer at crest)
> > > > > > > 5) Complementary PWM mode 2 (transfer at trough)
> > > > > > > 6) Complementary PWM mode 3 (transfer at crest and trough)
> > > > > >
> > > > > > Shouldn't all this go in the PWM driver binding?
> > > > >
> > > > > Looks like at top level MTU3 IP provides similar HW
> > functionality
> > > > like
> > > > > below binding [1], where there is a core MFD driver and pwm,
> > > > > counter and timer as child devices.
> > > >
> > > > Previous mistakes are not good references for what should happen
> > in
> > > > the present and the future. =;)
> > >
> > > Why do you think that reference is not a good one? I believe there
> > > should be some reason for it.
> >
> > I didn't even look at it.
> >
> > What I "believe" is that documentation for each functionality
> > belonging to a particular subsystem should live in subsystem's
> > associated documentation directory and be reviewed/maintained by that
> > subsystem's associated maintainer.
>
> If I am correct, MFD is subsystem for calling shared resources
> across subsystems.
>
> Here shared resources are channels which is shared by timer, counter and pwm
Which API do the consumers use to obtain these shared resources?
> They are child objects of MFD subsystems. That is the reason it is in MFDndings.
If the properties belong to the child, they should be documented in
the child's bindings. Shoving all functionality and by extension all
documentation into the MFD driver and/or binding is incorrect
behaviour.
Looking at it from another perspective, I cannot/should not review
PWM, Reset, Counter or Timer bindings, since I do not have the level
of subject area knowledge as the assigned maintainers do.
Please place all sub-system specific bindings in their correct (leaf)
bindings and link to them from this one (run this):
git grep \$ref -- Documentation/devicetree/bindings/mfd/
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM
2022-10-03 8:57 ` Lee Jones
@ 2022-10-03 9:04 ` Biju Das
2022-10-03 9:34 ` Biju Das
0 siblings, 1 reply; 28+ messages in thread
From: Biju Das @ 2022-10-03 9:04 UTC (permalink / raw)
To: Lee Jones
Cc: Rob Herring, Krzysztof Kozlowski, Thierry Reding,
Uwe Kleine-König, linux-pwm, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
Hi Lee,
> Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> RZ/G2L MTU3 PWM
>
> On Mon, 03 Oct 2022, Biju Das wrote:
>
> > Hi Lee,
> >
> > > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> > > RZ/G2L MTU3 PWM
> > >
> > > On Sat, 01 Oct 2022, Biju Das wrote:
> > >
> > > > Hi Lee Jones,
> > > >
> > > > > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3:
> Document
> > > > > RZ/G2L MTU3 PWM
> > > > >
> > > > > On Thu, 29 Sep 2022, Biju Das wrote:
> > > > >
> > > > > > Hi Lee Jones,
> > > > > >
> > > > > > Thanks for the feedback.
> > > > > >
> > > > > > > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3:
> > > Document
> > > > > > > RZ/G2L MTU3 PWM
> > > > > > >
> > > > > > > On Thu, 29 Sep 2022, Biju Das wrote:
> > > > > > >
> > > > > > > > Document RZ/G2L MTU3 PWM support. It supports following
> > > > > > > > pwm
> > > > > modes.
> > > > > > > > 1) PWM mode 1
> > > > > > > > 2) PWM mode 2
> > > > > > > > 3) Reset-synchronized PWM mode
> > > > > > > > 4) Complementary PWM mode 1 (transfer at crest)
> > > > > > > > 5) Complementary PWM mode 2 (transfer at trough)
> > > > > > > > 6) Complementary PWM mode 3 (transfer at crest and
> > > > > > > > trough)
> > > > > > >
> > > > > > > Shouldn't all this go in the PWM driver binding?
> > > > > >
> > > > > > Looks like at top level MTU3 IP provides similar HW
> > > functionality
> > > > > like
> > > > > > below binding [1], where there is a core MFD driver and pwm,
> > > > > > counter and timer as child devices.
> > > > >
> > > > > Previous mistakes are not good references for what should
> happen
> > > in
> > > > > the present and the future. =;)
> > > >
> > > > Why do you think that reference is not a good one? I believe
> there
> > > > should be some reason for it.
> > >
> > > I didn't even look at it.
> > >
> > > What I "believe" is that documentation for each functionality
> > > belonging to a particular subsystem should live in subsystem's
> > > associated documentation directory and be reviewed/maintained by
> > > that subsystem's associated maintainer.
> >
> > If I am correct, MFD is subsystem for calling shared resources
> across
> > subsystems.
> >
> > Here shared resources are channels which is shared by timer, counter
> > and pwm
>
> Which API do the consumers use to obtain these shared resources?
They need to use MFD driver API to get shared resources.
>
> > They are child objects of MFD subsystems. That is the reason it is
> in MFDndings.
>
> If the properties belong to the child, they should be documented in
> the child's bindings. Shoving all functionality and by extension all
> documentation into the MFD driver and/or binding is incorrect
> behaviour.
Do you have an example, how will it look like, if the below binding to be part of
pwm and linked against the parent MFD driver?
+ "^pwm@([0-4]|[6-7])+$":
+ type: object
+
+ properties:
+ compatible:
+ const: renesas,rz-mtu3-pwm
+
+ reg:
+ description: Identify pwm channels.
+ items:
+ enum: [ 0, 1, 2, 3, 4, 6, 7 ]
+
+ "#pwm-cells":
+ const: 2
+
+ renesas,pwm-mode1:
+ type: boolean
+ description: Enable PWM mode 1.
+
+ renesas,pwm-mode2:
+ type: boolean
+ description: Enable PWM mode 2.
+
+ renesas,reset-synchronized-pwm-mode:
+ type: boolean
+ description: Enable Reset-synchronized PWM mode.
+
+ renesas,complementary-pwm-mode1:
+ type: boolean
+ description: Complementary PWM mode 1 (transfer at crest).
+
+ renesas,complementary-pwm-mode2:
+ type: boolean
+ description: Complementary PWM mode 2 (transfer at trough).
+
+ renesas,complementary-pwm-mode3:
+ type: boolean
+ description: Complementary PWM mode 3 (transfer at crest and trough).
+
+ required:
+ - compatible
+ - reg
+ - "#pwm-cells"
+
examples:
+ pwm@3 {
+ compatible = "renesas,rz-mtu3-pwm";
+ reg = <3>;
+ #pwm-cells = <2>;
+ renesas,pwm-mode1;
+ };
};
Cheers,
Biju
>
> Looking at it from another perspective, I cannot/should not review
> PWM, Reset, Counter or Timer bindings, since I do not have the level
> of subject area knowledge as the assigned maintainers do.
>
> Please place all sub-system specific bindings in their correct (leaf)
> bindings and link to them from this one (run this):
>
> git grep \$ref -- Documentation/devicetree/bindings/mfd/
>
> --
> Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 28+ messages in thread* RE: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM
2022-10-03 9:04 ` Biju Das
@ 2022-10-03 9:34 ` Biju Das
0 siblings, 0 replies; 28+ messages in thread
From: Biju Das @ 2022-10-03 9:34 UTC (permalink / raw)
To: Lee Jones
Cc: Rob Herring, Krzysztof Kozlowski, Thierry Reding,
Uwe Kleine-König, linux-pwm, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
Hi Lee Jpnes,
Thanks for the feedback.
> Subject: RE: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> RZ/G2L MTU3 PWM
>
> Hi Lee,
>
> > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> > RZ/G2L MTU3 PWM
> >
> > On Mon, 03 Oct 2022, Biju Das wrote:
> >
> > > Hi Lee,
> > >
> > > > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> > > > RZ/G2L MTU3 PWM
> > > >
> > > > On Sat, 01 Oct 2022, Biju Das wrote:
> > > >
> > > > > Hi Lee Jones,
> > > > >
> > > > > > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3:
> > Document
> > > > > > RZ/G2L MTU3 PWM
> > > > > >
> > > > > > On Thu, 29 Sep 2022, Biju Das wrote:
> > > > > >
> > > > > > > Hi Lee Jones,
> > > > > > >
> > > > > > > Thanks for the feedback.
> > > > > > >
> > > > > > > > Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3:
> > > > Document
> > > > > > > > RZ/G2L MTU3 PWM
> > > > > > > >
> > > > > > > > On Thu, 29 Sep 2022, Biju Das wrote:
> > > > > > > >
> > > > > > > > > Document RZ/G2L MTU3 PWM support. It supports
> following
> > > > > > > > > pwm
> > > > > > modes.
> > > > > > > > > 1) PWM mode 1
> > > > > > > > > 2) PWM mode 2
> > > > > > > > > 3) Reset-synchronized PWM mode
> > > > > > > > > 4) Complementary PWM mode 1 (transfer at crest)
> > > > > > > > > 5) Complementary PWM mode 2 (transfer at trough)
> > > > > > > > > 6) Complementary PWM mode 3 (transfer at crest and
> > > > > > > > > trough)
> > > > > > > >
> > > > > > > > Shouldn't all this go in the PWM driver binding?
> > > > > > >
> > > > > > > Looks like at top level MTU3 IP provides similar HW
> > > > functionality
> > > > > > like
> > > > > > > below binding [1], where there is a core MFD driver and
> pwm,
> > > > > > > counter and timer as child devices.
> > > > > >
> > > > > > Previous mistakes are not good references for what should
> > happen
> > > > in
> > > > > > the present and the future. =;)
> > > > >
> > > > > Why do you think that reference is not a good one? I believe
> > there
> > > > > should be some reason for it.
> > > >
> > > > I didn't even look at it.
> > > >
> > > > What I "believe" is that documentation for each functionality
> > > > belonging to a particular subsystem should live in subsystem's
> > > > associated documentation directory and be reviewed/maintained by
> > > > that subsystem's associated maintainer.
> > >
> > > If I am correct, MFD is subsystem for calling shared resources
> > across
> > > subsystems.
> > >
> > > Here shared resources are channels which is shared by timer,
> counter
> > > and pwm
> >
> > Which API do the consumers use to obtain these shared resources?
>
> They need to use MFD driver API to get shared resources.
>
> >
> > > They are child objects of MFD subsystems. That is the reason it is
> > in MFDndings.
> >
> > If the properties belong to the child, they should be documented in
> > the child's bindings. Shoving all functionality and by extension
> all
> > documentation into the MFD driver and/or binding is incorrect
> > behaviour.
>
> Do you have an example, how will it look like, if the below binding to
> be part of pwm and linked against the parent MFD driver?
>
>
> + "^pwm@([0-4]|[6-7])+$":
> + type: object
> +
> + properties:
> + compatible:
> + const: renesas,rz-mtu3-pwm
> +
> + reg:
> + description: Identify pwm channels.
> + items:
> + enum: [ 0, 1, 2, 3, 4, 6, 7 ]
> +
> + "#pwm-cells":
> + const: 2
> +
> + renesas,pwm-mode1:
> + type: boolean
> + description: Enable PWM mode 1.
> +
> + renesas,pwm-mode2:
> + type: boolean
> + description: Enable PWM mode 2.
> +
> + renesas,reset-synchronized-pwm-mode:
> + type: boolean
> + description: Enable Reset-synchronized PWM mode.
> +
> + renesas,complementary-pwm-mode1:
> + type: boolean
> + description: Complementary PWM mode 1 (transfer at crest).
> +
> + renesas,complementary-pwm-mode2:
> + type: boolean
> + description: Complementary PWM mode 2 (transfer at trough).
> +
> + renesas,complementary-pwm-mode3:
> + type: boolean
> + description: Complementary PWM mode 3 (transfer at crest and
> trough).
> +
> + required:
> + - compatible
> + - reg
> + - "#pwm-cells"
> +
>
> examples:
> + pwm@3 {
> + compatible = "renesas,rz-mtu3-pwm";
> + reg = <3>;
> + #pwm-cells = <2>;
> + renesas,pwm-mode1;
> + };
> };
>
>
> Cheers,
> Biju
>
> >
> > Looking at it from another perspective, I cannot/should not review
> > PWM, Reset, Counter or Timer bindings, since I do not have the level
> > of subject area knowledge as the assigned maintainers do.
> >
> > Please place all sub-system specific bindings in their correct
> (leaf)
> > bindings and link to them from this one (run this):
> >
> > git grep \$ref -- Documentation/devicetree/bindings/mfd/
Thanks for the pointer, I got references [1] and [2]. I can model like this,
If everyone ok with it.
[1] Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml
[2] Documentation/devicetree/bindings/pwm/kontron,sl28cpld-pwm.yaml
Cheers,
Biju
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM
2022-09-29 10:30 ` [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM Biju Das
2022-09-29 17:52 ` Lee Jones
@ 2022-09-30 18:35 ` Rob Herring
2022-10-01 16:30 ` Biju Das
1 sibling, 1 reply; 28+ messages in thread
From: Rob Herring @ 2022-09-30 18:35 UTC (permalink / raw)
To: Biju Das
Cc: Krzysztof Kozlowski, Thierry Reding, Lee Jones,
Uwe Kleine-König, linux-pwm, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
On Thu, Sep 29, 2022 at 11:30:39AM +0100, Biju Das wrote:
> Document RZ/G2L MTU3 PWM support. It supports following pwm modes.
> 1) PWM mode 1
> 2) PWM mode 2
> 3) Reset-synchronized PWM mode
> 4) Complementary PWM mode 1 (transfer at crest)
> 5) Complementary PWM mode 2 (transfer at trough)
> 6) Complementary PWM mode 3 (transfer at crest and trough)
What does 'complementary' mean here?
Mode 1, 2, 3 isn't very meaningful. Do other PWMs have similar modes? No
way to tell without better descriptions.
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 50 +++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> index c4bcf28623d6..362fedf5bedb 100644
> --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> @@ -223,6 +223,50 @@ patternProperties:
> - compatible
> - reg
>
> + "^pwm@([0-4]|[6-7])+$":
> + type: object
> +
> + properties:
> + compatible:
> + const: renesas,rz-mtu3-pwm
> +
> + reg:
> + description: Identify pwm channels.
> + items:
> + enum: [ 0, 1, 2, 3, 4, 6, 7 ]
At any given level in DT, there is only 1 address space. You've created
2 with pwms and counters.
> +
> + "#pwm-cells":
> + const: 2
> +
> + renesas,pwm-mode1:
> + type: boolean
> + description: Enable PWM mode 1.
> +
> + renesas,pwm-mode2:
> + type: boolean
> + description: Enable PWM mode 2.
> +
> + renesas,reset-synchronized-pwm-mode:
> + type: boolean
> + description: Enable Reset-synchronized PWM mode.
> +
> + renesas,complementary-pwm-mode1:
> + type: boolean
> + description: Complementary PWM mode 1 (transfer at crest).
> +
> + renesas,complementary-pwm-mode2:
> + type: boolean
> + description: Complementary PWM mode 2 (transfer at trough).
> +
> + renesas,complementary-pwm-mode3:
> + type: boolean
> + description: Complementary PWM mode 3 (transfer at crest and trough).
These all look like client configuration and should be either runtime
config or part of pwm cells args.
> +
> + required:
> + - compatible
> + - reg
> + - "#pwm-cells"
> +
> required:
> - compatible
> - reg
> @@ -305,6 +349,12 @@ examples:
> compatible = "renesas,rzg2l-mtu3-counter";
> reg = <1>;
> };
> + pwm@3 {
> + compatible = "renesas,rz-mtu3-pwm";
> + reg = <3>;
> + #pwm-cells = <2>;
> + renesas,pwm-mode1;
> + };
> };
>
> ...
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 28+ messages in thread* RE: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM
2022-09-30 18:35 ` Rob Herring
@ 2022-10-01 16:30 ` Biju Das
0 siblings, 0 replies; 28+ messages in thread
From: Biju Das @ 2022-10-01 16:30 UTC (permalink / raw)
To: Rob Herring
Cc: Krzysztof Kozlowski, Thierry Reding, Lee Jones,
Uwe Kleine-König, linux-pwm, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
Hi Rob,
Thanks for the feedback.
> Subject: Re: [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document
> RZ/G2L MTU3 PWM
>
> On Thu, Sep 29, 2022 at 11:30:39AM +0100, Biju Das wrote:
> > Document RZ/G2L MTU3 PWM support. It supports following pwm modes.
> > 1) PWM mode 1
> > 2) PWM mode 2
> > 3) Reset-synchronized PWM mode
> > 4) Complementary PWM mode 1 (transfer at crest)
> > 5) Complementary PWM mode 2 (transfer at trough)
> > 6) Complementary PWM mode 3 (transfer at crest and trough)
>
> What does 'complementary' mean here?
Through interlocked operation of MTU3/4 and MTU6/7, the positive and negative signals in six
phases (12 phases in total) can be output in complementary PWM
>
> Mode 1, 2, 3 isn't very meaningful. Do other PWMs have similar modes?
In complementary PWM mode, buffer registers are used to update the data in five compare registers for PWM duty
and PWM cycle. The update data can be written to the buffer registers at any time.
There is a temporary register between each of these registers and its buffer register.
The temporary register value is transferred to the compare register at the data update timing set with
Mode bits(MTU3.TMDR1.MD[3:0] (MTU6.TMDR1.MD[3:0]). Mode 1, 2, 3 corresponding to these modes.
> No way to tell without better descriptions.
OK will update description.
>
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 50
> +++++++++++++++++++
> > 1 file changed, 50 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > index c4bcf28623d6..362fedf5bedb 100644
> > --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> > @@ -223,6 +223,50 @@ patternProperties:
> > - compatible
> > - reg
> >
> > + "^pwm@([0-4]|[6-7])+$":
> > + type: object
> > +
> > + properties:
> > + compatible:
> > + const: renesas,rz-mtu3-pwm
> > +
> > + reg:
> > + description: Identify pwm channels.
> > + items:
> > + enum: [ 0, 1, 2, 3, 4, 6, 7 ]
>
> At any given level in DT, there is only 1 address space. You've
> created
> 2 with pwms and counters.
pwm and counters are mutually exclusive on the same channel which is taken care
at higher level(eg: board level, we enable either pwm or counter, not both).
Is it wrong to specify same channel for counter or pwm with same address?
If needed, I could add logical addresses for these channels and
on implementation side, will map these logical channels with actual hardware channels.
Please let me know.
>
> > +
> > + "#pwm-cells":
> > + const: 2
> > +
> > + renesas,pwm-mode1:
> > + type: boolean
> > + description: Enable PWM mode 1.
> > +
> > + renesas,pwm-mode2:
> > + type: boolean
> > + description: Enable PWM mode 2.
> > +
> > + renesas,reset-synchronized-pwm-mode:
> > + type: boolean
> > + description: Enable Reset-synchronized PWM mode.
> > +
> > + renesas,complementary-pwm-mode1:
> > + type: boolean
> > + description: Complementary PWM mode 1 (transfer at crest).
> > +
> > + renesas,complementary-pwm-mode2:
> > + type: boolean
> > + description: Complementary PWM mode 2 (transfer at trough).
> > +
> > + renesas,complementary-pwm-mode3:
> > + type: boolean
> > + description: Complementary PWM mode 3 (transfer at crest
> and trough).
>
> These all look like client configuration and should be either runtime
> config or part of pwm cells args.
HW supports 6 modes, as mentioned above. How do we switch between modes??
Could it be a sysfs option?? If sysfs, do we need to document here?
Cheers,
Biju
>
> > +
> > + required:
> > + - compatible
> > + - reg
> > + - "#pwm-cells"
> > +
> > required:
> > - compatible
> > - reg
> > @@ -305,6 +349,12 @@ examples:
> > compatible = "renesas,rzg2l-mtu3-counter";
> > reg = <1>;
> > };
> > + pwm@3 {
> > + compatible = "renesas,rz-mtu3-pwm";
> > + reg = <3>;
> > + #pwm-cells = <2>;
> > + renesas,pwm-mode1;
> > + };
> > };
> >
> > ...
> > --
> > 2.25.1
> >
> >
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH RFC 4/7] pwm: Add support for RZ/G2L MTU3 PWM
2022-09-29 10:30 [PATCH RFC 0/7] Add RZ/G2L MTU3 PWM driver Biju Das
` (2 preceding siblings ...)
2022-09-29 10:30 ` [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM Biju Das
@ 2022-09-29 10:30 ` Biju Das
2022-09-29 10:30 ` [PATCH RFC 5/7] arm64: dts: renesas: r9a07g044: Add MTU3 PWM support Biju Das
` (2 subsequent siblings)
6 siblings, 0 replies; 28+ messages in thread
From: Biju Das @ 2022-09-29 10:30 UTC (permalink / raw)
To: Thierry Reding
Cc: Biju Das, Uwe Kleine-König, linux-pwm, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
Add support for RZ/G2L MTU3 PWM driver. The IP supports
following PWM modes
1) PWM mode 1
2) PWM mode 2
3) Reset-synchronized PWM mode
4) Complementary PWM mode 1 (transfer at crest)
5) Complementary PWM mode 2 (transfer at trough)
6) Complementary PWM mode 3 (transfer at crest and trough)
This patch adds basic pwm mode 1 support for RZ/G2L MTU3 driver
by creating separate logical channels for each IOs.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/pwm/Kconfig | 11 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-rz-mtu3.c | 384 ++++++++++++++++++++++++++++++++++++++
3 files changed, 396 insertions(+)
create mode 100644 drivers/pwm/pwm-rz-mtu3.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 2723a3e9ff65..a32e2a20bd1d 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -492,6 +492,17 @@ config PWM_RZG2L_GPT
To compile this driver as a module, choose M here: the module
will be called pwm-rzg2l-gpt.
+config PWM_RZ_MTU3
+ tristate "Renesas RZ/G2L MTU3 PWM Timer support"
+ depends on ARCH_RZG2L || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ This driver exposes the MTU3 PWM Timer controller found in Renesas
+ RZ/G2L like chips through the PWM API.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-rz-mtu3.
+
config PWM_SAMSUNG
tristate "Samsung PWM support"
depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index cac39b18d1ee..e307fec041f7 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o
obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
obj-$(CONFIG_PWM_RZG2L_GPT) += pwm-rzg2l-gpt.o
+obj-$(CONFIG_PWM_RZ_MTU3) += pwm-rz-mtu3.o
obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
diff --git a/drivers/pwm/pwm-rz-mtu3.c b/drivers/pwm/pwm-rz-mtu3.c
new file mode 100644
index 000000000000..228665530745
--- /dev/null
+++ b/drivers/pwm/pwm-rz-mtu3.c
@@ -0,0 +1,384 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2L MTU3 PWM Timer driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ *
+ * Hardware manual for this IP can be found here
+ * https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?language=en
+ *
+ * Limitations:
+ * - When PWM is disabled, the output is driven to Hi-Z.
+ * - While the hardware supports both polarities, the driver (for now)
+ * only handles normal polarity.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/mfd/rzg2l-mtu3.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/limits.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/time.h>
+
+#define RZ_MTU3_TMDR1_MD_NORMAL (0)
+#define RZ_MTU3_TMDR1_MD_PWM_MODE_1 (2)
+
+#define RZ_MTU3_TIOR_OC_RETAIN (0)
+#define RZ_MTU3_TIOR_OC_0_H_COMP_MATCH (2)
+#define RZ_MTU3_TIOR_OC_1_TOGGLE (7)
+
+#define RZ_MTU3_TCR_CCLR_TGRA (1 << 5)
+#define RZ_MTU3_TCR_CCLR_TGRC (5 << 5)
+#define RZ_MTU3_TCR_CKEG_RISING (0 << 3)
+
+#define RZ_MTU3_TCR_TPCS GENMASK(2, 0)
+
+struct rz_mtu3_pwm_chip {
+ struct pwm_chip chip;
+ struct clk *clk;
+ struct rzg2l_mtu3_channel *ch;
+ struct mutex lock;
+ u32 user_count;
+ unsigned long rate;
+ bool pwm_enabled_by_bootloader;
+};
+
+static inline struct rz_mtu3_pwm_chip *to_rz_mtu3_pwm_chip(struct pwm_chip *chip)
+{
+ return container_of(chip, struct rz_mtu3_pwm_chip, chip);
+}
+
+static u8 rz_mtu3_pwm_calculate_prescale(struct rz_mtu3_pwm_chip *rzg2l_mtu3,
+ u64 period_cycles)
+{
+ u32 prescaled_period_cycles;
+ u8 prescale;
+
+ prescaled_period_cycles = period_cycles >> 16;
+
+ if (prescaled_period_cycles >= 16)
+ prescale = 3;
+ else
+ prescale = (roundup_pow_of_two(prescaled_period_cycles + 1) + 1) / 2;
+
+ return prescale;
+}
+
+static int rz_mtu3_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
+
+ mutex_lock(&rz_mtu3_pwm->lock);
+ rz_mtu3_pwm->user_count++;
+ mutex_unlock(&rz_mtu3_pwm->lock);
+
+ return 0;
+}
+
+static void rz_mtu3_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
+
+ mutex_lock(&rz_mtu3_pwm->lock);
+ rz_mtu3_pwm->user_count--;
+ mutex_unlock(&rz_mtu3_pwm->lock);
+}
+
+static int rz_mtu3_pwm_enable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm,
+ struct pwm_device *pwm)
+{
+ u8 val;
+
+ val = (RZ_MTU3_TIOR_OC_1_TOGGLE << 4) | RZ_MTU3_TIOR_OC_0_H_COMP_MATCH;
+ if (rz_mtu3_pwm->ch->function == RZG2L_MTU3_PWM_MODE_1) {
+ rzg2l_mtu3_8bit_ch_write(rz_mtu3_pwm->ch, RZG2L_MTU3_TMDR1,
+ RZ_MTU3_TMDR1_MD_PWM_MODE_1);
+ if (pwm->hwpwm)
+ rzg2l_mtu3_8bit_ch_write(rz_mtu3_pwm->ch,
+ RZG2L_MTU3_TIORL, val);
+ else
+ rzg2l_mtu3_8bit_ch_write(rz_mtu3_pwm->ch,
+ RZG2L_MTU3_TIORH, val);
+
+ rzg2l_mtu3_enable(rz_mtu3_pwm->ch);
+ }
+
+ return 0;
+}
+
+static void rz_mtu3_pwm_disable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm,
+ struct pwm_device *pwm)
+{
+ /* Return to normal mode and disable output pins of MTU3 channel */
+ if (rz_mtu3_pwm->user_count <= 1)
+ rzg2l_mtu3_8bit_ch_write(rz_mtu3_pwm->ch, RZG2L_MTU3_TMDR1,
+ RZ_MTU3_TMDR1_MD_NORMAL);
+
+ if (rz_mtu3_pwm->ch->function == RZG2L_MTU3_PWM_MODE_1) {
+ if (pwm->hwpwm)
+ rzg2l_mtu3_8bit_ch_write(rz_mtu3_pwm->ch,
+ RZG2L_MTU3_TIORL,
+ RZ_MTU3_TIOR_OC_RETAIN);
+ else
+ rzg2l_mtu3_8bit_ch_write(rz_mtu3_pwm->ch,
+ RZG2L_MTU3_TIORH,
+ RZ_MTU3_TIOR_OC_RETAIN);
+
+ rzg2l_mtu3_disable(rz_mtu3_pwm->ch);
+ }
+}
+
+static int rz_mtu3_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
+ unsigned long pv, dc;
+ u64 period_cycles;
+ u64 duty_cycles;
+ u8 prescale;
+ int ret;
+ u8 val;
+
+ /*
+ * Refuse clk rates > 1 GHz to prevent overflowing the following
+ * calculation.
+ */
+ if (rz_mtu3_pwm->rate > NSEC_PER_SEC)
+ return -EINVAL;
+
+ ret = clk_prepare_enable(rz_mtu3_pwm->clk);
+ if (ret)
+ return ret;
+
+ duty_cycles = state->duty_cycle;
+ if (!state->enabled)
+ duty_cycles = 0;
+
+ period_cycles = mul_u64_u32_div(state->period, rz_mtu3_pwm->rate,
+ NSEC_PER_SEC);
+ prescale = rz_mtu3_pwm_calculate_prescale(rz_mtu3_pwm, period_cycles);
+
+ if (period_cycles >> (2 * prescale) <= U16_MAX)
+ pv = period_cycles >> (2 * prescale);
+ else
+ pv = U16_MAX;
+
+ duty_cycles = mul_u64_u32_div(duty_cycles, rz_mtu3_pwm->rate,
+ NSEC_PER_SEC);
+ if (duty_cycles >> (2 * prescale) <= U16_MAX)
+ dc = duty_cycles >> (2 * prescale);
+ else
+ dc = U16_MAX;
+
+ val = RZ_MTU3_TCR_CKEG_RISING | prescale;
+ if (pwm->hwpwm) {
+ rzg2l_mtu3_8bit_ch_write(rz_mtu3_pwm->ch, RZG2L_MTU3_TCR,
+ RZ_MTU3_TCR_CCLR_TGRC | val);
+ rzg2l_mtu3_16bit_ch_write(rz_mtu3_pwm->ch, RZG2L_MTU3_TGRD, dc);
+ rzg2l_mtu3_16bit_ch_write(rz_mtu3_pwm->ch, RZG2L_MTU3_TGRC, pv);
+ } else {
+ rzg2l_mtu3_8bit_ch_write(rz_mtu3_pwm->ch, RZG2L_MTU3_TCR,
+ RZ_MTU3_TCR_CCLR_TGRA | val);
+ rzg2l_mtu3_16bit_ch_write(rz_mtu3_pwm->ch, RZG2L_MTU3_TGRB, dc);
+ rzg2l_mtu3_16bit_ch_write(rz_mtu3_pwm->ch, RZG2L_MTU3_TGRA, pv);
+ }
+
+ clk_disable(rz_mtu3_pwm->clk);
+
+ return 0;
+}
+
+static void rz_mtu3_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
+ u8 prescale, val;
+ u16 dc, pv;
+ u64 tmp;
+
+ clk_prepare_enable(rz_mtu3_pwm->clk);
+ state->enabled = rzg2l_mtu3_is_enabled(rz_mtu3_pwm->ch);
+ if (state->enabled) {
+ val = rzg2l_mtu3_8bit_ch_read(rz_mtu3_pwm->ch, RZG2L_MTU3_TCR);
+ prescale = FIELD_GET(RZ_MTU3_TCR_TPCS, val);
+
+ if (pwm->hwpwm) {
+ dc = rzg2l_mtu3_16bit_ch_read(rz_mtu3_pwm->ch,
+ RZG2L_MTU3_TGRD);
+ pv = rzg2l_mtu3_16bit_ch_read(rz_mtu3_pwm->ch,
+ RZG2L_MTU3_TGRC);
+ } else {
+ dc = rzg2l_mtu3_16bit_ch_read(rz_mtu3_pwm->ch,
+ RZG2L_MTU3_TGRB);
+ pv = rzg2l_mtu3_16bit_ch_read(rz_mtu3_pwm->ch,
+ RZG2L_MTU3_TGRA);
+ }
+
+ tmp = NSEC_PER_SEC * (u64)pv << (2 * prescale);
+ state->period = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate);
+
+ tmp = NSEC_PER_SEC * (u64)dc << (2 * prescale);
+ state->duty_cycle = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate);
+
+ if (state->duty_cycle > state->period)
+ state->duty_cycle = state->period;
+ }
+
+ state->polarity = PWM_POLARITY_NORMAL;
+ clk_disable(rz_mtu3_pwm->clk);
+}
+
+static int rz_mtu3_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
+ struct pwm_state cur_state;
+ bool enabled;
+ int ret;
+
+ cur_state = pwm->state;
+ enabled = cur_state.enabled;
+
+ if (state->polarity != PWM_POLARITY_NORMAL)
+ return -EINVAL;
+
+ ret = rz_mtu3_pwm_config(chip, pwm, state);
+ if (ret)
+ goto done;
+
+ if (!state->enabled) {
+ if (rz_mtu3_pwm->pwm_enabled_by_bootloader) {
+ /*
+ * For PWM enabled by bootloader case, decrement the clk
+ * usage count and set the pwm_enabled_by_bootloader
+ * variable to false.
+ */
+ rz_mtu3_pwm->pwm_enabled_by_bootloader = false;
+ clk_disable(rz_mtu3_pwm->clk);
+ }
+
+ if (enabled)
+ rz_mtu3_pwm_disable(rz_mtu3_pwm, pwm);
+ ret = 0;
+ goto done;
+ }
+
+ return rz_mtu3_pwm_enable(rz_mtu3_pwm, pwm);
+
+done:
+ return ret;
+}
+
+static const struct pwm_ops rz_mtu3_pwm_ops = {
+ .request = rz_mtu3_pwm_request,
+ .free = rz_mtu3_pwm_free,
+ .get_state = rz_mtu3_pwm_get_state,
+ .apply = rz_mtu3_pwm_apply,
+ .owner = THIS_MODULE,
+};
+
+static const struct of_device_id rz_mtu3_pwm_of_table[] = {
+ { .compatible = "renesas,rz-mtu3-pwm", },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rz_mtu3_pwm_of_table);
+
+static void rz_mtu3_pwm_clk_disable(void *data)
+{
+ struct rz_mtu3_pwm_chip *rz_mtu3_pwm = data;
+
+ if (rz_mtu3_pwm->pwm_enabled_by_bootloader)
+ clk_disable(rz_mtu3_pwm->clk);
+}
+
+static int rz_mtu3_pwm_probe(struct platform_device *pdev)
+{
+ struct rzg2l_mtu3 *ddata = dev_get_drvdata(pdev->dev.parent);
+ struct rz_mtu3_pwm_chip *rz_mtu3_pwm;
+ struct device *dev = &pdev->dev;
+ u32 ch, tmp;
+ int ret;
+
+ rz_mtu3_pwm = devm_kzalloc(&pdev->dev, sizeof(*rz_mtu3_pwm), GFP_KERNEL);
+ if (!rz_mtu3_pwm)
+ return -ENOMEM;
+
+ ret = of_property_read_u32(dev->of_node, "reg", &ch);
+ if (ret)
+ return dev_err_probe(&pdev->dev, -EINVAL,
+ "%pOF: No reg property found\n",
+ dev->of_node);
+
+ if (ch == RZG2L_MTU5 || ch == RZG2L_MTU8)
+ return dev_err_probe(&pdev->dev, -EINVAL,
+ "%pOF: Invalid channel '%u'\n",
+ dev->of_node, ch);
+
+ if (!of_get_property(dev->of_node, "renesas,pwm-mode1", &tmp))
+ return dev_err_probe(&pdev->dev, -EINVAL,
+ "%pOF: pwm-mode1 not defined ch='%u'\n",
+ dev->of_node, ch);
+
+ rz_mtu3_pwm->clk = ddata->clk;
+ rz_mtu3_pwm->ch = &ddata->channels[ch];
+ rz_mtu3_pwm->ch->dev = &pdev->dev;
+ if (rz_mtu3_pwm->ch->function != RZG2L_MTU3_NORMAL)
+ return dev_err_probe(&pdev->dev, -EINVAL,
+ "channel '%u' is already claimed\n", ch);
+
+ rz_mtu3_pwm->ch->function = RZG2L_MTU3_PWM_MODE_1;
+ rz_mtu3_pwm->rate = clk_get_rate(rz_mtu3_pwm->clk);
+
+ mutex_init(&rz_mtu3_pwm->lock);
+
+ rz_mtu3_pwm->chip.dev = &pdev->dev;
+ rz_mtu3_pwm->chip.ops = &rz_mtu3_pwm_ops;
+ if (ch == RZG2L_MTU1 || ch == RZG2L_MTU2)
+ rz_mtu3_pwm->chip.npwm = 1;
+ else
+ rz_mtu3_pwm->chip.npwm = 2;
+
+ /*
+ * We need to keep the clock on, in case the bootloader has enabled the
+ * PWM and is running during probe(). A variable pwm_enabled_by_
+ * bootloader is set to true in that case and during first
+ * pwm_disable(), it is set to false and decrement the clk usage count.
+ */
+ if (rzg2l_mtu3_is_enabled(rz_mtu3_pwm->ch)) {
+ rz_mtu3_pwm->pwm_enabled_by_bootloader = true;
+ /* Increment clock ref count */
+ ret = clk_prepare_enable(rz_mtu3_pwm->clk);
+ if (ret)
+ return ret;
+
+ ret = devm_add_action_or_reset(&pdev->dev,
+ rz_mtu3_pwm_clk_disable,
+ rz_mtu3_pwm);
+ if (ret < 0)
+ return ret;
+ }
+
+ ret = devm_pwmchip_add(&pdev->dev, &rz_mtu3_pwm->chip);
+ if (ret)
+ dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
+
+ return ret;
+}
+
+static struct platform_driver rz_mtu3_pwm_driver = {
+ .driver = {
+ .name = "pwm-rz-mtu3",
+ .of_match_table = of_match_ptr(rz_mtu3_pwm_of_table),
+ },
+ .probe = rz_mtu3_pwm_probe,
+};
+module_platform_driver(rz_mtu3_pwm_driver);
+
+MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/G2L MTU3 PWM Timer Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pwm-rz-mtu3");
--
2.25.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH RFC 5/7] arm64: dts: renesas: r9a07g044: Add MTU3 PWM support
2022-09-29 10:30 [PATCH RFC 0/7] Add RZ/G2L MTU3 PWM driver Biju Das
` (3 preceding siblings ...)
2022-09-29 10:30 ` [PATCH RFC 4/7] pwm: Add support for " Biju Das
@ 2022-09-29 10:30 ` Biju Das
2022-09-29 10:30 ` [PATCH RFC 6/7] arm64: dts: renesas: r9a07g054: " Biju Das
2022-09-29 10:30 ` [PATCH RFC 7/7] arm64: dts: renesas: rzg2l-smarc: [HACK] Enable MTU3 PWM channel 3 for PWM mode 1 testing Biju Das
6 siblings, 0 replies; 28+ messages in thread
From: Biju Das @ 2022-09-29 10:30 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add MTU3 pwm support by adding pwm nodes to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 42 ++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 05193457502a..f853b2d0b8ff 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -249,6 +249,48 @@ counter@2 {
reg = <2>;
status = "disabled";
};
+
+ pwm@1 {
+ compatible = "renesas,rz-mtu3-pwm";
+ reg = <1>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm@2 {
+ compatible = "renesas,rz-mtu3-pwm";
+ reg = <2>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm@3 {
+ compatible = "renesas,rz-mtu3-pwm";
+ reg = <3>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm@4 {
+ compatible = "renesas,rz-mtu3-pwm";
+ reg = <4>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm@6 {
+ compatible = "renesas,rz-mtu3-pwm";
+ reg = <6>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm@7 {
+ compatible = "renesas,rz-mtu3-pwm";
+ reg = <7>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
};
gpt0: pwm@10048000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH RFC 6/7] arm64: dts: renesas: r9a07g054: Add MTU3 PWM support
2022-09-29 10:30 [PATCH RFC 0/7] Add RZ/G2L MTU3 PWM driver Biju Das
` (4 preceding siblings ...)
2022-09-29 10:30 ` [PATCH RFC 5/7] arm64: dts: renesas: r9a07g044: Add MTU3 PWM support Biju Das
@ 2022-09-29 10:30 ` Biju Das
2022-09-29 10:30 ` [PATCH RFC 7/7] arm64: dts: renesas: rzg2l-smarc: [HACK] Enable MTU3 PWM channel 3 for PWM mode 1 testing Biju Das
6 siblings, 0 replies; 28+ messages in thread
From: Biju Das @ 2022-09-29 10:30 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add MTU3 pwm support by adding pwm nodes to RZ/V2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 42 ++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 3f25e1b280eb..3aa527a003cb 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -249,6 +249,48 @@ counter@2 {
reg = <2>;
status = "disabled";
};
+
+ pwm@1 {
+ compatible = "renesas,rz-mtu3-pwm";
+ reg = <1>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm@2 {
+ compatible = "renesas,rz-mtu3-pwm";
+ reg = <2>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm@3 {
+ compatible = "renesas,rz-mtu3-pwm";
+ reg = <3>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm@4 {
+ compatible = "renesas,rz-mtu3-pwm";
+ reg = <4>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm@6 {
+ compatible = "renesas,rz-mtu3-pwm";
+ reg = <6>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm@7 {
+ compatible = "renesas,rz-mtu3-pwm";
+ reg = <7>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
};
gpt0: pwm@10048000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH RFC 7/7] arm64: dts: renesas: rzg2l-smarc: [HACK] Enable MTU3 PWM channel 3 for PWM mode 1 testing
2022-09-29 10:30 [PATCH RFC 0/7] Add RZ/G2L MTU3 PWM driver Biju Das
` (5 preceding siblings ...)
2022-09-29 10:30 ` [PATCH RFC 6/7] arm64: dts: renesas: r9a07g054: " Biju Das
@ 2022-09-29 10:30 ` Biju Das
6 siblings, 0 replies; 28+ messages in thread
From: Biju Das @ 2022-09-29 10:30 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../boot/dts/renesas/rz-smarc-common.dtsi | 2 ++
.../dts/renesas/rzg2l-smarc-pinfunction.dtsi | 11 ++++++++++
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 5 +++++
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 20 +++++++++++++++++++
4 files changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
index 3962d47b3e59..1414cc8e99ca 100644
--- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
@@ -160,12 +160,14 @@ &sdhi1 {
status = "okay";
};
+#if 0
&spi1 {
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
status = "okay";
};
+#endif
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
index bd81028d5462..40772bde9d05 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
@@ -64,6 +64,15 @@ mtu3_clk {
pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */
<RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTLCKB */
};
+
+ mtu3_pwm {
+ pinmux =
+
+ <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */
+ <RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */
+ <RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */
+ <RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */
+ };
};
#endif
@@ -125,12 +134,14 @@ sound_clk_pins: sound_clk {
input-enable;
};
+#if 0
spi1_pins: spi1 {
pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
<RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
<RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
<RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
};
+#endif
ssi0_pins: ssi0 {
pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 6ce6e9434873..b9f8f1759fce 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -62,6 +62,11 @@ counter@1 {
counter@2 {
status = "okay";
};
+
+ pwm@3 {
+ renesas,pwm-mode1;
+ status = "okay";
+ };
};
#endif
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index 6be25a8a28db..f17428c5826d 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -18,6 +18,8 @@
* Please change below macros according to SW1 setting
*/
+#define MTU3_PHASE_COUNTING_SUPPORT 1
+
#define SW_SD0_DEV_SEL 1
#define SW_SCIF_CAN 0
@@ -78,6 +80,24 @@ wm8978: codec@1a {
};
};
+#if (MTU3_PHASE_COUNTING_SUPPORT)
+&mtu3 {
+ status = "okay";
+ counter@1 {
+ status = "okay";
+ };
+
+ counter@2 {
+ status = "okay";
+ };
+
+ pwm@3 {
+ renesas,pwm-mode1;
+ status = "okay";
+ };
+};
+#endif
+
/*
* To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
* SW1 should be at position 2->3 so that SER0_CTS# line is activated
--
2.25.1
^ permalink raw reply related [flat|nested] 28+ messages in thread