From: anup@brainfault.org (Anup Patel) To: linux-riscv@lists.infradead.org Subject: [PATCH 3/4] irqchip: sifive-plic: Differentiate between PLIC handler and context Date: Mon, 22 Oct 2018 17:15:16 +0530 [thread overview] Message-ID: <20181022114517.22748-4-anup@brainfault.org> (raw) In-Reply-To: <20181022114517.22748-1-anup@brainfault.org> We explicitly differentiate between PLIC handler and context because PLIC context is for given mode of HART whereas PLIC handler is per-CPU software construct meant to handling interrupts from a particular PLIC context. Signed-off-by: Anup Patel <anup@brainfault.org> --- drivers/irqchip/irq-sifive-plic.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 869355d2a713..eb9e8aee1a1a 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -64,8 +64,8 @@ struct plic_handler { struct plic_hw { u32 nr_irqs; + u32 nr_contexts; u32 nr_handlers; - u32 nr_mapped; void __iomem *regs; struct plic_handler *handlers; struct irq_domain *irqdomain; @@ -190,10 +190,10 @@ static int __init plic_init(struct device_node *node, if (WARN_ON(!plic.nr_irqs)) goto out_iounmap; - plic.nr_handlers = of_irq_count(node); - if (WARN_ON(!plic.nr_handlers)) + plic.nr_contexts = of_irq_count(node); + if (WARN_ON(!plic.nr_contexts)) goto out_iounmap; - if (WARN_ON(plic.nr_handlers < num_possible_cpus())) + if (WARN_ON(plic.nr_contexts < num_possible_cpus())) goto out_iounmap; error = -ENOMEM; @@ -206,7 +206,7 @@ static int __init plic_init(struct device_node *node, if (WARN_ON(!plic.irqdomain)) goto out_free_handlers; - for (i = 0; i < plic.nr_handlers; i++) { + for (i = 0; i < plic.nr_contexts; i++) { struct of_phandle_args parent; struct plic_handler *handler; irq_hw_number_t hwirq; @@ -229,6 +229,11 @@ static int __init plic_init(struct device_node *node, cpu = riscv_hartid_to_cpuid(hartid); handler = per_cpu_ptr(plic.handlers, cpu); + if (handler->present) { + pr_warn("handler not available for context %d.\n", i); + continue; + } + handler->present = true; handler->hart_base = plic.regs + CONTEXT_BASE + i * CONTEXT_PER_HART; @@ -241,11 +246,11 @@ static int __init plic_init(struct device_node *node, for (hwirq = 1; hwirq <= plic.nr_irqs; hwirq++) plic_toggle(handler, hwirq, 0); - plic.nr_mapped++; + plic.nr_handlers++; } - pr_info("mapped %d interrupts to %d (out of %d) handlers.\n", - plic.nr_irqs, plic.nr_mapped, plic.nr_handlers); + pr_info("mapped %d interrupts with %d handlers for %d contexts.\n", + plic.nr_irqs, plic.nr_handlers, plic.nr_contexts); set_handle_irq(plic_handle_irq); return 0; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org> To: Palmer Dabbelt <palmer@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <marc.zyngier@arm.com> Cc: Christoph Hellwig <hch@infradead.org>, Atish Patra <atish.patra@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel <anup@brainfault.org> Subject: [PATCH 3/4] irqchip: sifive-plic: Differentiate between PLIC handler and context Date: Mon, 22 Oct 2018 17:15:16 +0530 [thread overview] Message-ID: <20181022114517.22748-4-anup@brainfault.org> (raw) Message-ID: <20181022114516.6Ra6YHvTXoPgXEoSHpgV4fufZOSS_WLDvd2dgVhndoA@z> (raw) In-Reply-To: <20181022114517.22748-1-anup@brainfault.org> We explicitly differentiate between PLIC handler and context because PLIC context is for given mode of HART whereas PLIC handler is per-CPU software construct meant to handling interrupts from a particular PLIC context. Signed-off-by: Anup Patel <anup@brainfault.org> --- drivers/irqchip/irq-sifive-plic.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 869355d2a713..eb9e8aee1a1a 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -64,8 +64,8 @@ struct plic_handler { struct plic_hw { u32 nr_irqs; + u32 nr_contexts; u32 nr_handlers; - u32 nr_mapped; void __iomem *regs; struct plic_handler *handlers; struct irq_domain *irqdomain; @@ -190,10 +190,10 @@ static int __init plic_init(struct device_node *node, if (WARN_ON(!plic.nr_irqs)) goto out_iounmap; - plic.nr_handlers = of_irq_count(node); - if (WARN_ON(!plic.nr_handlers)) + plic.nr_contexts = of_irq_count(node); + if (WARN_ON(!plic.nr_contexts)) goto out_iounmap; - if (WARN_ON(plic.nr_handlers < num_possible_cpus())) + if (WARN_ON(plic.nr_contexts < num_possible_cpus())) goto out_iounmap; error = -ENOMEM; @@ -206,7 +206,7 @@ static int __init plic_init(struct device_node *node, if (WARN_ON(!plic.irqdomain)) goto out_free_handlers; - for (i = 0; i < plic.nr_handlers; i++) { + for (i = 0; i < plic.nr_contexts; i++) { struct of_phandle_args parent; struct plic_handler *handler; irq_hw_number_t hwirq; @@ -229,6 +229,11 @@ static int __init plic_init(struct device_node *node, cpu = riscv_hartid_to_cpuid(hartid); handler = per_cpu_ptr(plic.handlers, cpu); + if (handler->present) { + pr_warn("handler not available for context %d.\n", i); + continue; + } + handler->present = true; handler->hart_base = plic.regs + CONTEXT_BASE + i * CONTEXT_PER_HART; @@ -241,11 +246,11 @@ static int __init plic_init(struct device_node *node, for (hwirq = 1; hwirq <= plic.nr_irqs; hwirq++) plic_toggle(handler, hwirq, 0); - plic.nr_mapped++; + plic.nr_handlers++; } - pr_info("mapped %d interrupts to %d (out of %d) handlers.\n", - plic.nr_irqs, plic.nr_mapped, plic.nr_handlers); + pr_info("mapped %d interrupts with %d handlers for %d contexts.\n", + plic.nr_irqs, plic.nr_handlers, plic.nr_contexts); set_handle_irq(plic_handle_irq); return 0; -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2018-10-22 11:45 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-10-22 11:45 [PATCH 0/4] IRQ affinity support in PLIC driver Anup Patel 2018-10-22 11:45 ` Anup Patel 2018-10-22 11:45 ` [PATCH 1/4] irqchip: sifive-plic: Pre-compute context hart base and enable base Anup Patel 2018-10-22 11:45 ` Anup Patel 2018-11-09 8:42 ` Christoph Hellwig 2018-11-09 8:42 ` Christoph Hellwig 2018-11-12 4:27 ` Anup Patel 2018-11-12 4:27 ` Anup Patel 2018-10-22 11:45 ` [PATCH 2/4] irqchip: sifive-plic: More flexible plic_irq_toggle() Anup Patel 2018-10-22 11:45 ` Anup Patel 2018-11-09 8:43 ` Christoph Hellwig 2018-11-09 8:43 ` Christoph Hellwig 2018-11-12 12:33 ` Anup Patel 2018-11-12 12:33 ` Anup Patel 2018-10-22 11:45 ` Anup Patel [this message] 2018-10-22 11:45 ` [PATCH 3/4] irqchip: sifive-plic: Differentiate between PLIC handler and context Anup Patel 2018-10-22 11:45 ` [PATCH 4/4] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host Anup Patel 2018-10-22 11:45 ` Anup Patel
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