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From: anup@brainfault.org (Anup Patel)
To: linux-riscv@lists.infradead.org
Subject: [PATCH 2/4] irqchip: sifive-plic: More flexible plic_irq_toggle()
Date: Mon, 12 Nov 2018 18:03:09 +0530	[thread overview]
Message-ID: <CAAhSdy20zU=GeaePQfYW_FKH-wmsYgvK3-6ouc3S8QpwWH-Z+w@mail.gmail.com> (raw)
In-Reply-To: <20181109084338.GB6508@infradead.org>

On Fri, Nov 9, 2018 at 2:13 PM Christoph Hellwig <hch@infradead.org> wrote:
>
> > -
> >  struct plic_handler {
> >       bool                    present;
> > -     int                     ctxid;
> >       void __iomem            *hart_base;
> >       raw_spinlock_t          enable_lock;
> >       void __iomem            *enable_base;
> >  };
> > -static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
>
> This does not match the changelog at all.

My bad. I should have put this change into separate patch.

I will refactor this patch.

Regards,
Anup

WARNING: multiple messages have this Message-ID
From: Anup Patel <anup@brainfault.org>
To: Christoph Hellwig <hch@infradead.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
	Jason Cooper <jason@lakedaemon.net>,
	Marc Zyngier <marc.zyngier@arm.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	"linux-kernel@vger.kernel.org List"
	<linux-kernel@vger.kernel.org>, Atish Patra <atish.patra@wdc.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Thomas Gleixner <tglx@linutronix.de>,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH 2/4] irqchip: sifive-plic: More flexible plic_irq_toggle()
Date: Mon, 12 Nov 2018 18:03:09 +0530	[thread overview]
Message-ID: <CAAhSdy20zU=GeaePQfYW_FKH-wmsYgvK3-6ouc3S8QpwWH-Z+w@mail.gmail.com> (raw)
Message-ID: <20181112123309.D7DgIuj4XY-t8ODyzWb5ygExeOV4KjroF7-l9LbPVnE@z> (raw)
In-Reply-To: <20181109084338.GB6508@infradead.org>

On Fri, Nov 9, 2018 at 2:13 PM Christoph Hellwig <hch@infradead.org> wrote:
>
> > -
> >  struct plic_handler {
> >       bool                    present;
> > -     int                     ctxid;
> >       void __iomem            *hart_base;
> >       raw_spinlock_t          enable_lock;
> >       void __iomem            *enable_base;
> >  };
> > -static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
>
> This does not match the changelog at all.

My bad. I should have put this change into separate patch.

I will refactor this patch.

Regards,
Anup

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  parent reply	other threads:[~2018-11-12 12:33 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-22 11:45 [PATCH 0/4] IRQ affinity support in PLIC driver Anup Patel
2018-10-22 11:45 ` Anup Patel
2018-10-22 11:45 ` [PATCH 1/4] irqchip: sifive-plic: Pre-compute context hart base and enable base Anup Patel
2018-10-22 11:45   ` Anup Patel
2018-11-09  8:42   ` Christoph Hellwig
2018-11-09  8:42     ` Christoph Hellwig
2018-11-12  4:27     ` Anup Patel
2018-11-12  4:27       ` Anup Patel
2018-10-22 11:45 ` [PATCH 2/4] irqchip: sifive-plic: More flexible plic_irq_toggle() Anup Patel
2018-10-22 11:45   ` Anup Patel
2018-11-09  8:43   ` Christoph Hellwig
2018-11-09  8:43     ` Christoph Hellwig
2018-11-12 12:33     ` Anup Patel [this message]
2018-11-12 12:33       ` Anup Patel
2018-10-22 11:45 ` [PATCH 3/4] irqchip: sifive-plic: Differentiate between PLIC handler and context Anup Patel
2018-10-22 11:45   ` Anup Patel
2018-10-22 11:45 ` [PATCH 4/4] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host Anup Patel
2018-10-22 11:45   ` Anup Patel

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