From: Atish Patra <atish.patra@wdc.com>
To: linux-riscv@lists.infradead.org
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
Damien.LeMoal@wdc.com, alankao@andestech.com, zong@andestech.com,
anup@brainfault.org, palmer@sifive.com,
linux-kernel@vger.kernel.org, hch@infradead.org,
robh+dt@kernel.org, tglx@linutronix.de
Subject: [RFC 0/2] Add RISC-V cpu topology
Date: Thu, 1 Nov 2018 16:04:26 -0700 [thread overview]
Message-ID: <1541113468-22097-1-git-send-email-atish.patra@wdc.com> (raw)
Message-ID: <20181101230426.AP0wY6nEnK4chIw4nbXybObN9jmNXad1Ijx-wysnKxU@z> (raw)
This patch series adds the cpu topology for RISC-V. It contains
both the DT binding and actual source code. It has been tested on
QEMU & Unleashed board.
The idea is based on cpu-map in ARM with changes related to how
we define SMT systems. The reason for adopting a similar approach
to ARM as I feel it provides a very clear way of defining the
topology compared to parsing cache nodes to figure out which cpus
share the same package or core. I am open to any other idea to
implement cpu-topology as well.
Atish Patra (2):
dt-bindings: topology: Add RISC-V cpu topology.
RISC-V: Introduce cpu topology.
.../devicetree/bindings/riscv/topology.txt | 154 ++++++++++++++++
arch/riscv/include/asm/topology.h | 28 +++
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/smpboot.c | 5 +-
arch/riscv/kernel/topology.c | 194 +++++++++++++++++++++
5 files changed, 381 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/riscv/topology.txt
create mode 100644 arch/riscv/include/asm/topology.h
create mode 100644 arch/riscv/kernel/topology.c
--
2.7.4
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next reply other threads:[~2018-11-01 23:04 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-01 23:04 Atish Patra [this message]
2018-11-01 23:04 ` [RFC 0/2] Add RISC-V cpu topology Atish Patra
2018-11-01 23:04 ` [RFC 1/2] dt-bindings: topology: " Atish Patra
2018-11-01 23:04 ` Atish Patra
2018-11-02 13:09 ` Rob Herring
2018-11-02 13:09 ` Rob Herring
2018-11-02 13:31 ` Sudeep Holla
2018-11-02 13:31 ` Sudeep Holla
2018-11-02 15:11 ` Rob Herring
2018-11-02 15:11 ` Rob Herring
2018-11-02 15:50 ` Sudeep Holla
2018-11-02 15:50 ` Sudeep Holla
2018-11-02 20:53 ` Atish Patra
2018-11-02 20:53 ` Atish Patra
2018-11-02 21:08 ` Rob Herring
2018-11-02 21:08 ` Rob Herring
2018-11-02 20:34 ` Atish Patra
2018-11-02 20:34 ` Atish Patra
2018-11-05 19:38 ` Palmer Dabbelt
2018-11-05 19:38 ` Palmer Dabbelt
2018-11-05 20:10 ` Rob Herring
2018-11-05 20:10 ` Rob Herring
2018-11-06 0:12 ` Atish Patra
2018-11-06 0:12 ` Atish Patra
2018-11-06 10:03 ` Nick Kossifidis
2018-11-06 10:03 ` Nick Kossifidis
2018-11-06 11:37 ` Mark Rutland
2018-11-06 11:37 ` Mark Rutland
2018-11-01 23:04 ` [RFC 2/2] RISC-V: Introduce " Atish Patra
2018-11-01 23:04 ` Atish Patra
2018-11-02 18:58 ` [RFC 0/2] Add RISC-V " Nick Kossifidis
2018-11-02 18:58 ` Nick Kossifidis
2018-11-02 21:14 ` Atish Patra
2018-11-02 21:14 ` Atish Patra
2018-11-02 22:18 ` Nick Kossifidis
2018-11-02 22:18 ` Nick Kossifidis
2018-11-06 14:13 ` Sudeep Holla
2018-11-06 14:13 ` Sudeep Holla
2018-11-06 15:26 ` Nick Kossifidis
2018-11-06 15:26 ` Nick Kossifidis
2018-11-06 15:50 ` Sudeep Holla
2018-11-06 15:50 ` Sudeep Holla
2018-11-06 16:20 ` Mark Rutland
2018-11-06 16:20 ` Mark Rutland
2018-11-07 2:31 ` Nick Kossifidis
2018-11-07 2:31 ` Nick Kossifidis
2018-11-07 12:06 ` Mark Rutland
2018-11-07 12:06 ` Mark Rutland
2018-11-08 13:45 ` Nick Kossifidis
2018-11-08 13:45 ` Nick Kossifidis
2018-11-08 15:54 ` Mark Rutland
2018-11-08 15:54 ` Mark Rutland
2018-11-09 3:55 ` Nick Kossifidis
2018-11-09 3:55 ` Nick Kossifidis
2018-11-07 12:28 ` Sudeep Holla
2018-11-07 12:28 ` Sudeep Holla
2018-11-08 14:52 ` Nick Kossifidis
2018-11-08 14:52 ` Nick Kossifidis
2018-11-08 16:48 ` Sudeep Holla
2018-11-08 16:48 ` Sudeep Holla
2018-11-09 2:36 ` Nick Kossifidis
2018-11-09 2:36 ` Nick Kossifidis
2018-11-09 12:33 ` Sudeep Holla
2018-11-09 12:33 ` Sudeep Holla
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