From: sudeep.holla@arm.com (Sudeep Holla) To: linux-riscv@lists.infradead.org Subject: [RFC 1/2] dt-bindings: topology: Add RISC-V cpu topology. Date: Fri, 2 Nov 2018 15:50:38 +0000 [thread overview] Message-ID: <20181102155038.GA21067@e107155-lin> (raw) In-Reply-To: <CAL_JsqLO+cOcHkr41ebPtONwrzOWGhksH1ypph+tihsuOVDOug@mail.gmail.com> On Fri, Nov 02, 2018 at 10:11:38AM -0500, Rob Herring wrote: > On Fri, Nov 2, 2018 at 8:31 AM Sudeep Holla <sudeep.holla@arm.com> wrote: > > > > On Fri, Nov 02, 2018 at 08:09:39AM -0500, Rob Herring wrote: > > > On Thu, Nov 1, 2018 at 6:04 PM Atish Patra <atish.patra@wdc.com> wrote: > > > > > > > > Define a RISC-V cpu topology. This is based on cpu-map in ARM world. > > > > But it doesn't need a separate thread node for defining SMT systems. > > > > Multiple cpu phandle properties can be parsed to identify the sibling > > > > hardware threads. Moreover, we do not have cluster concept in RISC-V. > > > > So package is a better word choice than cluster for RISC-V. > > > > > > There was a proposal to add package info for ARM recently. Not sure > > > what happened to that, but we don't need 2 different ways. > > > > > > > We still need that, I can brush it up and post what Lorenzo had previously > > proposed[1]. We want to keep both DT and ACPI CPU topology story aligned. > > Frankly, I don't care what the ACPI story is. I care whether each cpu Sorry I meant feature parity with ACPI and didn't refer to the mechanics. > arch does its own thing in DT or not. If a package prop works for > RISC-V folks and that happens to align with ACPI, then okay. Though I > tend to prefer a package represented as a node rather than a property > as I think that's more consistent. > Sounds good. One of the reason for making it *optional* property is for backward compatibility. But we should be able to deal with that even with node. > Any comments on the thread aspect (whether it has ever been used)? > Though I think thread as a node level is more consistent with each > topology level being a node (same with package). > Not 100% sure, the only multi threaded core in the market I know is Cavium TX2 which is ACPI. -- Regards, Sudeep
WARNING: multiple messages have this Message-ID (diff)
From: Sudeep Holla <sudeep.holla@arm.com> To: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org, Damien.LeMoal@wdc.com, alankao@andestech.com, Zong Li <zong@andestech.com>, Anup Patel <anup@brainfault.org>, Palmer Dabbelt <palmer@sifive.com>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Christoph Hellwig <hch@infradead.org>, Atish Patra <atish.patra@wdc.com>, Sudeep Holla <sudeep.holla@arm.com>, linux-riscv@lists.infradead.org, Thomas Gleixner <tglx@linutronix.de> Subject: Re: [RFC 1/2] dt-bindings: topology: Add RISC-V cpu topology. Date: Fri, 2 Nov 2018 15:50:38 +0000 [thread overview] Message-ID: <20181102155038.GA21067@e107155-lin> (raw) Message-ID: <20181102155038.ly1eroI5mupGDdYZPMF-9vT1J6tw06b95E_ZRj46sJg@z> (raw) In-Reply-To: <CAL_JsqLO+cOcHkr41ebPtONwrzOWGhksH1ypph+tihsuOVDOug@mail.gmail.com> On Fri, Nov 02, 2018 at 10:11:38AM -0500, Rob Herring wrote: > On Fri, Nov 2, 2018 at 8:31 AM Sudeep Holla <sudeep.holla@arm.com> wrote: > > > > On Fri, Nov 02, 2018 at 08:09:39AM -0500, Rob Herring wrote: > > > On Thu, Nov 1, 2018 at 6:04 PM Atish Patra <atish.patra@wdc.com> wrote: > > > > > > > > Define a RISC-V cpu topology. This is based on cpu-map in ARM world. > > > > But it doesn't need a separate thread node for defining SMT systems. > > > > Multiple cpu phandle properties can be parsed to identify the sibling > > > > hardware threads. Moreover, we do not have cluster concept in RISC-V. > > > > So package is a better word choice than cluster for RISC-V. > > > > > > There was a proposal to add package info for ARM recently. Not sure > > > what happened to that, but we don't need 2 different ways. > > > > > > > We still need that, I can brush it up and post what Lorenzo had previously > > proposed[1]. We want to keep both DT and ACPI CPU topology story aligned. > > Frankly, I don't care what the ACPI story is. I care whether each cpu Sorry I meant feature parity with ACPI and didn't refer to the mechanics. > arch does its own thing in DT or not. If a package prop works for > RISC-V folks and that happens to align with ACPI, then okay. Though I > tend to prefer a package represented as a node rather than a property > as I think that's more consistent. > Sounds good. One of the reason for making it *optional* property is for backward compatibility. But we should be able to deal with that even with node. > Any comments on the thread aspect (whether it has ever been used)? > Though I think thread as a node level is more consistent with each > topology level being a node (same with package). > Not 100% sure, the only multi threaded core in the market I know is Cavium TX2 which is ACPI. -- Regards, Sudeep _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2018-11-02 15:50 UTC|newest] Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-11-01 23:04 [RFC 0/2] Add RISC-V cpu topology Atish Patra 2018-11-01 23:04 ` Atish Patra 2018-11-01 23:04 ` [RFC 1/2] dt-bindings: topology: " Atish Patra 2018-11-01 23:04 ` Atish Patra 2018-11-02 13:09 ` Rob Herring 2018-11-02 13:09 ` Rob Herring 2018-11-02 13:31 ` Sudeep Holla 2018-11-02 13:31 ` Sudeep Holla 2018-11-02 15:11 ` Rob Herring 2018-11-02 15:11 ` Rob Herring 2018-11-02 15:50 ` Sudeep Holla [this message] 2018-11-02 15:50 ` Sudeep Holla 2018-11-02 20:53 ` Atish Patra 2018-11-02 20:53 ` Atish Patra 2018-11-02 21:08 ` Rob Herring 2018-11-02 21:08 ` Rob Herring 2018-11-02 20:34 ` Atish Patra 2018-11-02 20:34 ` Atish Patra 2018-11-05 19:38 ` Palmer Dabbelt 2018-11-05 19:38 ` Palmer Dabbelt 2018-11-05 20:10 ` Rob Herring 2018-11-05 20:10 ` Rob Herring 2018-11-06 0:12 ` Atish Patra 2018-11-06 0:12 ` Atish Patra 2018-11-06 10:03 ` Nick Kossifidis 2018-11-06 10:03 ` Nick Kossifidis 2018-11-06 11:37 ` Mark Rutland 2018-11-06 11:37 ` Mark Rutland 2018-11-01 23:04 ` [RFC 2/2] RISC-V: Introduce " Atish Patra 2018-11-01 23:04 ` Atish Patra 2018-11-02 18:58 ` [RFC 0/2] Add RISC-V " Nick Kossifidis 2018-11-02 18:58 ` Nick Kossifidis 2018-11-02 21:14 ` Atish Patra 2018-11-02 21:14 ` Atish Patra 2018-11-02 22:18 ` Nick Kossifidis 2018-11-02 22:18 ` Nick Kossifidis 2018-11-06 14:13 ` Sudeep Holla 2018-11-06 14:13 ` Sudeep Holla 2018-11-06 15:26 ` Nick Kossifidis 2018-11-06 15:26 ` Nick Kossifidis 2018-11-06 15:50 ` Sudeep Holla 2018-11-06 15:50 ` Sudeep Holla 2018-11-06 16:20 ` Mark Rutland 2018-11-06 16:20 ` Mark Rutland 2018-11-07 2:31 ` Nick Kossifidis 2018-11-07 2:31 ` Nick Kossifidis 2018-11-07 12:06 ` Mark Rutland 2018-11-07 12:06 ` Mark Rutland 2018-11-08 13:45 ` Nick Kossifidis 2018-11-08 13:45 ` Nick Kossifidis 2018-11-08 15:54 ` Mark Rutland 2018-11-08 15:54 ` Mark Rutland 2018-11-09 3:55 ` Nick Kossifidis 2018-11-09 3:55 ` Nick Kossifidis 2018-11-07 12:28 ` Sudeep Holla 2018-11-07 12:28 ` Sudeep Holla 2018-11-08 14:52 ` Nick Kossifidis 2018-11-08 14:52 ` Nick Kossifidis 2018-11-08 16:48 ` Sudeep Holla 2018-11-08 16:48 ` Sudeep Holla 2018-11-09 2:36 ` Nick Kossifidis 2018-11-09 2:36 ` Nick Kossifidis 2018-11-09 12:33 ` Sudeep Holla 2018-11-09 12:33 ` Sudeep Holla
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