* [PATCH] riscv: move sifive_l2_cache.c to drivers/misc @ 2019-08-07 15:10 Christoph Hellwig 2019-08-07 15:22 ` Greg KH 0 siblings, 1 reply; 6+ messages in thread From: Christoph Hellwig @ 2019-08-07 15:10 UTC (permalink / raw) To: palmer, arnd, gregkh; +Cc: linux-riscv, linux-kernel The sifive_l2_cache.c is in no way related to RISC-V architecture memory management. It is a little stub driver working around the fact that the EDAC maintainers prefer their drivers to be structured in a certain way that doesn't fit the SiFive SOCs. Move the file to drivers/misc and only build it when the EDAC_SIFIVE config option is selected. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Christoph Hellwig <hch@lst.de> --- arch/riscv/mm/Makefile | 1 - drivers/misc/Makefile | 1 + {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%) diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index 74055e1d6f21..d2101d0741d4 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -11,6 +11,5 @@ obj-y += extable.o obj-y += ioremap.o obj-y += cacheflush.o obj-y += context.o -obj-y += sifive_l2_cache.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index abd8ae249746..886d48301e8e 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -59,3 +59,4 @@ obj-y += cardreader/ obj-$(CONFIG_PVPANIC) += pvpanic.o obj-$(CONFIG_HABANA_AI) += habanalabs/ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o +obj-$(CONFIG_EDAC_SIFIVE) += sifive_l2_cache.o diff --git a/arch/riscv/mm/sifive_l2_cache.c b/drivers/misc/sifive_l2_cache.c similarity index 100% rename from arch/riscv/mm/sifive_l2_cache.c rename to drivers/misc/sifive_l2_cache.c -- 2.20.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/misc 2019-08-07 15:10 [PATCH] riscv: move sifive_l2_cache.c to drivers/misc Christoph Hellwig @ 2019-08-07 15:22 ` Greg KH 2019-08-07 15:24 ` Christoph Hellwig 0 siblings, 1 reply; 6+ messages in thread From: Greg KH @ 2019-08-07 15:22 UTC (permalink / raw) To: Christoph Hellwig; +Cc: linux-riscv, palmer, linux-kernel, arnd On Wed, Aug 07, 2019 at 06:10:09PM +0300, Christoph Hellwig wrote: > The sifive_l2_cache.c is in no way related to RISC-V architecture > memory management. It is a little stub driver working around the fact > that the EDAC maintainers prefer their drivers to be structured in a > certain way that doesn't fit the SiFive SOCs. > > Move the file to drivers/misc and only build it when the EDAC_SIFIVE > config option is selected. > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") > Signed-off-by: Christoph Hellwig <hch@lst.de> > --- > arch/riscv/mm/Makefile | 1 - > drivers/misc/Makefile | 1 + > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0 > 3 files changed, 1 insertion(+), 1 deletion(-) > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%) Why isn't this in drivers/edac/ ? why is this a misc driver? Seems like it should sit next to the edac stuff. thanks, greg k-h _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/misc 2019-08-07 15:22 ` Greg KH @ 2019-08-07 15:24 ` Christoph Hellwig 2019-08-07 15:40 ` Paul Walmsley 0 siblings, 1 reply; 6+ messages in thread From: Christoph Hellwig @ 2019-08-07 15:24 UTC (permalink / raw) To: Greg KH Cc: arnd, palmer, linux-kernel, james.morse, linux-riscv, mchehab, Christoph Hellwig, linux-edac On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote: > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") > > Signed-off-by: Christoph Hellwig <hch@lst.de> > > --- > > arch/riscv/mm/Makefile | 1 - > > drivers/misc/Makefile | 1 + > > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0 > > 3 files changed, 1 insertion(+), 1 deletion(-) > > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%) > > Why isn't this in drivers/edac/ ? > why is this a misc driver? Seems like it should sit next to the edac > stuff. No idea. EDAC maintainers, would you object to taking what is currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ? _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/misc 2019-08-07 15:24 ` Christoph Hellwig @ 2019-08-07 15:40 ` Paul Walmsley 2019-08-08 7:50 ` Christoph Hellwig 0 siblings, 1 reply; 6+ messages in thread From: Paul Walmsley @ 2019-08-07 15:40 UTC (permalink / raw) To: Christoph Hellwig Cc: arnd, Greg KH, palmer, linux-kernel, james.morse, linux-riscv, mchehab, linux-edac On Wed, 7 Aug 2019, Christoph Hellwig wrote: > On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote: > > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") > > > Signed-off-by: Christoph Hellwig <hch@lst.de> > > > --- > > > arch/riscv/mm/Makefile | 1 - > > > drivers/misc/Makefile | 1 + > > > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0 > > > 3 files changed, 1 insertion(+), 1 deletion(-) > > > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%) > > > > Why isn't this in drivers/edac/ ? > > why is this a misc driver? Seems like it should sit next to the edac > > stuff. > > No idea. EDAC maintainers, would you object to taking what is > currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ? If this driver is moved out of arch/riscv/mm, it should ideally go into some sort of common L2 cache controller driver directory, along with other L2 cache controller drivers like arch/arm/mm/*l2c*. Like many L2 cache controllers, this controller also supports cache flushing operations and SoC-specific way operations. We just don't use those on RISC-V - yet. - Paul _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/misc 2019-08-07 15:40 ` Paul Walmsley @ 2019-08-08 7:50 ` Christoph Hellwig 2019-08-08 8:07 ` Arnd Bergmann 0 siblings, 1 reply; 6+ messages in thread From: Christoph Hellwig @ 2019-08-08 7:50 UTC (permalink / raw) To: Paul Walmsley Cc: arnd, Greg KH, palmer, linux-kernel, james.morse, linux-riscv, mchehab, Christoph Hellwig, linux-edac On Wed, Aug 07, 2019 at 08:40:58AM -0700, Paul Walmsley wrote: > On Wed, 7 Aug 2019, Christoph Hellwig wrote: > > > On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote: > > > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") > > > > Signed-off-by: Christoph Hellwig <hch@lst.de> > > > > --- > > > > arch/riscv/mm/Makefile | 1 - > > > > drivers/misc/Makefile | 1 + > > > > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0 > > > > 3 files changed, 1 insertion(+), 1 deletion(-) > > > > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%) > > > > > > Why isn't this in drivers/edac/ ? > > > why is this a misc driver? Seems like it should sit next to the edac > > > stuff. > > > > No idea. EDAC maintainers, would you object to taking what is > > currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ? > > If this driver is moved out of arch/riscv/mm, it should ideally go into > some sort of common L2 cache controller driver directory, along > with other L2 cache controller drivers like arch/arm/mm/*l2c*. > > Like many L2 cache controllers, this controller also supports cache > flushing operations and SoC-specific way operations. We just don't use > those on RISC-V - yet. Well, another reason to not have it under arch/riscv/ as it is a SOC specific driver, which we all have somewhere else, just like arm64 and new arm ports do. And especially not unconditionally built. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/misc 2019-08-08 7:50 ` Christoph Hellwig @ 2019-08-08 8:07 ` Arnd Bergmann 0 siblings, 0 replies; 6+ messages in thread From: Arnd Bergmann @ 2019-08-08 8:07 UTC (permalink / raw) To: Christoph Hellwig Cc: Greg KH, Palmer Dabbelt, Linux Kernel Mailing List, James Morse, Paul Walmsley, linux-riscv, Mauro Carvalho Chehab, linux-edac On Thu, Aug 8, 2019 at 9:50 AM Christoph Hellwig <hch@lst.de> wrote: > On Wed, Aug 07, 2019 at 08:40:58AM -0700, Paul Walmsley wrote: > > On Wed, 7 Aug 2019, Christoph Hellwig wrote: > > > On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote: > > > > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") > > > > > Signed-off-by: Christoph Hellwig <hch@lst.de> > > > > > --- > > > > > arch/riscv/mm/Makefile | 1 - > > > > > drivers/misc/Makefile | 1 + > > > > > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0 > > > > > 3 files changed, 1 insertion(+), 1 deletion(-) > > > > > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%) > > > > > > > > Why isn't this in drivers/edac/ ? > > > > why is this a misc driver? Seems like it should sit next to the edac > > > > stuff. > > > > > > No idea. EDAC maintainers, would you object to taking what is > > > currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ? > > > > If this driver is moved out of arch/riscv/mm, it should ideally go into > > some sort of common L2 cache controller driver directory, along > > with other L2 cache controller drivers like arch/arm/mm/*l2c*. > > > > Like many L2 cache controllers, this controller also supports cache > > flushing operations and SoC-specific way operations. We just don't use > > those on RISC-V - yet. > > Well, another reason to not have it under arch/riscv/ as it is a SOC > specific driver, which we all have somewhere else, just like arm64 > and new arm ports do. And especially not unconditionally built. soc specific drivers that don't have their own subsystem can go into drivers/soc/$VENDOR/. For this driver, I would also think that the edac subsystem is the best fit. Right now, the driver is split in two halves: there is drivers/edac/sifive_edac.c and arch/riscv/mm/sifive_l2_cache.c, with neither of those working without the other. Moving both into a single file would seem to allow simplifying it as a proper 'platform_driver', which the drivers/edac side today is not (it just registers a platform device in its module_init call). Arnd _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-08-08 8:07 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-08-07 15:10 [PATCH] riscv: move sifive_l2_cache.c to drivers/misc Christoph Hellwig 2019-08-07 15:22 ` Greg KH 2019-08-07 15:24 ` Christoph Hellwig 2019-08-07 15:40 ` Paul Walmsley 2019-08-08 7:50 ` Christoph Hellwig 2019-08-08 8:07 ` Arnd Bergmann
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