From: Heiko Stuebner <heiko@sntech.de>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com
Cc: christoph.muellner@vrull.eu, prabhakar.csengg@gmail.com,
conor@kernel.org, philipp.tomsich@vrull.eu,
ajones@ventanamicro.com, heiko@sntech.de,
emil.renner.berthing@canonical.com, jszhang@kernel.org,
Heiko Stuebner <heiko.stuebner@vrull.eu>,
Conor Dooley <conor.dooley@microchip.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v5 10/12] RISC-V: add rd reg parsing to insn.h header
Date: Fri, 23 Dec 2022 23:13:30 +0100 [thread overview]
Message-ID: <20221223221332.4127602-11-heiko@sntech.de> (raw)
In-Reply-To: <20221223221332.4127602-1-heiko@sntech.de>
From: Heiko Stuebner <heiko.stuebner@vrull.eu>
Add a macro to allow parsing of the rd register from an instruction.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
---
arch/riscv/include/asm/insn.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
index 21ec817abec1..2a23890b4577 100644
--- a/arch/riscv/include/asm/insn.h
+++ b/arch/riscv/include/asm/insn.h
@@ -60,6 +60,7 @@
#define RVG_RS1_OPOFF 15
#define RVG_RS2_OPOFF 20
#define RVG_RD_OPOFF 7
+#define RVG_RD_MASK GENMASK(4, 0)
/* The bit field of immediate value in RVC J instruction */
#define RVC_J_IMM_SIGN_OPOFF 12
@@ -244,6 +245,10 @@ static __always_inline bool riscv_insn_is_branch(u32 code)
#define RV_X(X, s, mask) (((X) >> (s)) & (mask))
#define RVC_X(X, s, mask) RV_X(X, s, mask)
+#define RV_EXTRACT_RD_REG(x) \
+ ({typeof(x) x_ = (x); \
+ (RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
+
#define RV_EXTRACT_UTYPE_IMM(x) \
({typeof(x) x_ = (x); \
(RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
--
2.35.1
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next prev parent reply other threads:[~2022-12-23 22:17 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-23 22:13 [PATCH v5 00/12] Allow calls in alternatives Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 01/12] RISC-V: fix funct4 definition for c.jalr in parse_asm.h Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 02/12] RISC-V: add prefix to all constants/macros " Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 03/12] RISC-V: detach funct-values from their offset Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 04/12] RISC-V: add ebreak instructions to definitions Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 05/12] RISC-V: add auipc elements to parse_asm header Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 06/12] RISC-V: Move riscv_insn_is_* macros into a common header Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 07/12] RISC-V: rename parse_asm.h to insn.h Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 08/12] RISC-V: kprobes: use central defined funct3 constants Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 09/12] RISC-V: add U-type imm parsing to insn.h header Heiko Stuebner
2022-12-23 22:13 ` Heiko Stuebner [this message]
2022-12-23 22:13 ` [PATCH v5 11/12] RISC-V: add helpers for handling immediates in U-type and I-type pairs Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 12/12] RISC-V: fix auipc-jalr addresses in patched alternatives Heiko Stuebner
2022-12-29 15:00 ` [PATCH v5 00/12] Allow calls in alternatives Palmer Dabbelt
2022-12-29 20:10 ` patchwork-bot+linux-riscv
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