From: Heiko Stuebner <heiko@sntech.de>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com
Cc: christoph.muellner@vrull.eu, prabhakar.csengg@gmail.com,
conor@kernel.org, philipp.tomsich@vrull.eu,
ajones@ventanamicro.com, heiko@sntech.de,
emil.renner.berthing@canonical.com, jszhang@kernel.org,
Heiko Stuebner <heiko.stuebner@vrull.eu>,
Conor Dooley <conor.dooley@microchip.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v5 03/12] RISC-V: detach funct-values from their offset
Date: Fri, 23 Dec 2022 23:13:23 +0100 [thread overview]
Message-ID: <20221223221332.4127602-4-heiko@sntech.de> (raw)
In-Reply-To: <20221223221332.4127602-1-heiko@sntech.de>
From: Heiko Stuebner <heiko.stuebner@vrull.eu>
Rather than defining funct3, funct4, etc values pre-shifted to their
target-position in an instruction, define the values themselves and
only shift them where needed.
This allows using these funct-values in other places as well, for example
when decoding functions.
At the same time also reduces the use of magic numbers, one would need
a spec manual to understand.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
---
arch/riscv/include/asm/parse_asm.h | 100 +++++++++++++++++------------
1 file changed, 59 insertions(+), 41 deletions(-)
diff --git a/arch/riscv/include/asm/parse_asm.h b/arch/riscv/include/asm/parse_asm.h
index ea51542e0c65..e3f87da108f4 100644
--- a/arch/riscv/include/asm/parse_asm.h
+++ b/arch/riscv/include/asm/parse_asm.h
@@ -5,6 +5,15 @@
#include <linux/bits.h>
+#define RV_INSN_FUNCT3_MASK GENMASK(14, 12)
+#define RV_INSN_FUNCT3_OPOFF 12
+#define RV_INSN_OPCODE_MASK GENMASK(6, 0)
+#define RV_INSN_OPCODE_OPOFF 0
+#define RV_INSN_FUNCT12_OPOFF 20
+
+#define RV_ENCODE_FUNCT3(f_) (RVG_FUNCT3_##f_ << RV_INSN_FUNCT3_OPOFF)
+#define RV_ENCODE_FUNCT12(f_) (RVG_FUNCT12_##f_ << RV_INSN_FUNCT12_OPOFF)
+
/* The bit field of immediate value in I-type instruction */
#define RV_I_IMM_SIGN_OPOFF 31
#define RV_I_IMM_11_0_OPOFF 20
@@ -84,6 +93,15 @@
#define RVC_B_IMM_2_1_MASK GENMASK(1, 0)
#define RVC_B_IMM_5_MASK GENMASK(0, 0)
+#define RVC_INSN_FUNCT4_MASK GENMASK(15, 12)
+#define RVC_INSN_FUNCT4_OPOFF 12
+#define RVC_INSN_FUNCT3_MASK GENMASK(15, 13)
+#define RVC_INSN_FUNCT3_OPOFF 13
+#define RVC_INSN_J_RS2_MASK GENMASK(6, 2)
+#define RVC_INSN_OPCODE_MASK GENMASK(1, 0)
+#define RVC_ENCODE_FUNCT3(f_) (RVC_FUNCT3_##f_ << RVC_INSN_FUNCT3_OPOFF)
+#define RVC_ENCODE_FUNCT4(f_) (RVC_FUNCT4_##f_ << RVC_INSN_FUNCT4_OPOFF)
+
/* The register offset in RVC op=C0 instruction */
#define RVC_C0_RS1_OPOFF 7
#define RVC_C0_RS2_OPOFF 2
@@ -113,52 +131,52 @@
/* parts of funct3 code for I, M, A extension*/
#define RVG_FUNCT3_JALR 0x0
#define RVG_FUNCT3_BEQ 0x0
-#define RVG_FUNCT3_BNE 0x1000
-#define RVG_FUNCT3_BLT 0x4000
-#define RVG_FUNCT3_BGE 0x5000
-#define RVG_FUNCT3_BLTU 0x6000
-#define RVG_FUNCT3_BGEU 0x7000
+#define RVG_FUNCT3_BNE 0x1
+#define RVG_FUNCT3_BLT 0x4
+#define RVG_FUNCT3_BGE 0x5
+#define RVG_FUNCT3_BLTU 0x6
+#define RVG_FUNCT3_BGEU 0x7
/* parts of funct3 code for C extension*/
-#define RVC_FUNCT3_C_BEQZ 0xc000
-#define RVC_FUNCT3_C_BNEZ 0xe000
-#define RVC_FUNCT3_C_J 0xa000
-#define RVC_FUNCT3_C_JAL 0x2000
-#define RVC_FUNCT4_C_JR 0x8000
-#define RVC_FUNCT4_C_JALR 0x9000
+#define RVC_FUNCT3_C_BEQZ 0x6
+#define RVC_FUNCT3_C_BNEZ 0x7
+#define RVC_FUNCT3_C_J 0x5
+#define RVC_FUNCT3_C_JAL 0x1
+#define RVC_FUNCT4_C_JR 0x8
+#define RVC_FUNCT4_C_JALR 0x9
-#define RVG_FUNCT12_SRET 0x10200000
+#define RVG_FUNCT12_SRET 0x102
-#define RVG_MATCH_JALR (RVG_FUNCT3_JALR | RVG_OPCODE_JALR)
+#define RVG_MATCH_JALR (RV_ENCODE_FUNCT3(JALR) | RVG_OPCODE_JALR)
#define RVG_MATCH_JAL (RVG_OPCODE_JAL)
-#define RVG_MATCH_BEQ (RVG_FUNCT3_BEQ | RVG_OPCODE_BRANCH)
-#define RVG_MATCH_BNE (RVG_FUNCT3_BNE | RVG_OPCODE_BRANCH)
-#define RVG_MATCH_BLT (RVG_FUNCT3_BLT | RVG_OPCODE_BRANCH)
-#define RVG_MATCH_BGE (RVG_FUNCT3_BGE | RVG_OPCODE_BRANCH)
-#define RVG_MATCH_BLTU (RVG_FUNCT3_BLTU | RVG_OPCODE_BRANCH)
-#define RVG_MATCH_BGEU (RVG_FUNCT3_BGEU | RVG_OPCODE_BRANCH)
-#define RVG_MATCH_SRET (RVG_FUNCT12_SRET | RVG_OPCODE_SYSTEM)
-#define RVC_MATCH_C_BEQZ (RVC_FUNCT3_C_BEQZ | RVC_OPCODE_C1)
-#define RVC_MATCH_C_BNEZ (RVC_FUNCT3_C_BNEZ | RVC_OPCODE_C1)
-#define RVC_MATCH_C_J (RVC_FUNCT3_C_J | RVC_OPCODE_C1)
-#define RVC_MATCH_C_JAL (RVC_FUNCT3_C_JAL | RVC_OPCODE_C1)
-#define RVC_MATCH_C_JR (RVC_FUNCT4_C_JR | RVC_OPCODE_C2)
-#define RVC_MATCH_C_JALR (RVC_FUNCT4_C_JALR | RVC_OPCODE_C2)
-
-#define RVG_MASK_JALR 0x707f
-#define RVG_MASK_JAL 0x7f
-#define RVC_MASK_C_JALR 0xf07f
-#define RVC_MASK_C_JR 0xf07f
-#define RVC_MASK_C_JAL 0xe003
-#define RVC_MASK_C_J 0xe003
-#define RVG_MASK_BEQ 0x707f
-#define RVG_MASK_BNE 0x707f
-#define RVG_MASK_BLT 0x707f
-#define RVG_MASK_BGE 0x707f
-#define RVG_MASK_BLTU 0x707f
-#define RVG_MASK_BGEU 0x707f
-#define RVC_MASK_C_BEQZ 0xe003
-#define RVC_MASK_C_BNEZ 0xe003
+#define RVG_MATCH_BEQ (RV_ENCODE_FUNCT3(BEQ) | RVG_OPCODE_BRANCH)
+#define RVG_MATCH_BNE (RV_ENCODE_FUNCT3(BNE) | RVG_OPCODE_BRANCH)
+#define RVG_MATCH_BLT (RV_ENCODE_FUNCT3(BLT) | RVG_OPCODE_BRANCH)
+#define RVG_MATCH_BGE (RV_ENCODE_FUNCT3(BGE) | RVG_OPCODE_BRANCH)
+#define RVG_MATCH_BLTU (RV_ENCODE_FUNCT3(BLTU) | RVG_OPCODE_BRANCH)
+#define RVG_MATCH_BGEU (RV_ENCODE_FUNCT3(BGEU) | RVG_OPCODE_BRANCH)
+#define RVG_MATCH_SRET (RV_ENCODE_FUNCT12(SRET) | RVG_OPCODE_SYSTEM)
+#define RVC_MATCH_C_BEQZ (RVC_ENCODE_FUNCT3(C_BEQZ) | RVC_OPCODE_C1)
+#define RVC_MATCH_C_BNEZ (RVC_ENCODE_FUNCT3(C_BNEZ) | RVC_OPCODE_C1)
+#define RVC_MATCH_C_J (RVC_ENCODE_FUNCT3(C_J) | RVC_OPCODE_C1)
+#define RVC_MATCH_C_JAL (RVC_ENCODE_FUNCT3(C_JAL) | RVC_OPCODE_C1)
+#define RVC_MATCH_C_JR (RVC_ENCODE_FUNCT4(C_JR) | RVC_OPCODE_C2)
+#define RVC_MATCH_C_JALR (RVC_ENCODE_FUNCT4(C_JALR) | RVC_OPCODE_C2)
+
+#define RVG_MASK_JALR (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
+#define RVG_MASK_JAL (RV_INSN_OPCODE_MASK)
+#define RVC_MASK_C_JALR (RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)
+#define RVC_MASK_C_JR (RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)
+#define RVC_MASK_C_JAL (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
+#define RVC_MASK_C_J (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
+#define RVG_MASK_BEQ (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
+#define RVG_MASK_BNE (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
+#define RVG_MASK_BLT (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
+#define RVG_MASK_BGE (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
+#define RVG_MASK_BLTU (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
+#define RVG_MASK_BGEU (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
+#define RVC_MASK_C_BEQZ (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
+#define RVC_MASK_C_BNEZ (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
#define RVG_MASK_SRET 0xffffffff
#define __INSN_LENGTH_MASK _UL(0x3)
--
2.35.1
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next prev parent reply other threads:[~2022-12-23 22:23 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-23 22:13 [PATCH v5 00/12] Allow calls in alternatives Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 01/12] RISC-V: fix funct4 definition for c.jalr in parse_asm.h Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 02/12] RISC-V: add prefix to all constants/macros " Heiko Stuebner
2022-12-23 22:13 ` Heiko Stuebner [this message]
2022-12-23 22:13 ` [PATCH v5 04/12] RISC-V: add ebreak instructions to definitions Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 05/12] RISC-V: add auipc elements to parse_asm header Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 06/12] RISC-V: Move riscv_insn_is_* macros into a common header Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 07/12] RISC-V: rename parse_asm.h to insn.h Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 08/12] RISC-V: kprobes: use central defined funct3 constants Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 09/12] RISC-V: add U-type imm parsing to insn.h header Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 10/12] RISC-V: add rd reg " Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 11/12] RISC-V: add helpers for handling immediates in U-type and I-type pairs Heiko Stuebner
2022-12-23 22:13 ` [PATCH v5 12/12] RISC-V: fix auipc-jalr addresses in patched alternatives Heiko Stuebner
2022-12-29 15:00 ` [PATCH v5 00/12] Allow calls in alternatives Palmer Dabbelt
2022-12-29 20:10 ` patchwork-bot+linux-riscv
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