From: Hal Feng <hal.feng@starfivetech.com>
To: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-riscv@lists.infradead.org>
Cc: Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
"Rob Herring" <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Ben Dooks <ben.dooks@sifive.com>,
"Daniel Lezcano" <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Hal Feng <hal.feng@starfivetech.com>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH v6 15/21] reset: starfive: Add StarFive JH7110 reset driver
Date: Mon, 20 Mar 2023 18:37:44 +0800 [thread overview]
Message-ID: <20230320103750.60295-16-hal.feng@starfivetech.com> (raw)
In-Reply-To: <20230320103750.60295-1-hal.feng@starfivetech.com>
Add auxiliary driver to support StarFive JH7110 system
and always-on resets.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
drivers/reset/starfive/Kconfig | 8 +++
drivers/reset/starfive/Makefile | 1 +
.../reset/starfive/reset-starfive-jh7110.c | 70 +++++++++++++++++++
3 files changed, 79 insertions(+)
create mode 100644 drivers/reset/starfive/reset-starfive-jh7110.c
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
index 1927a5a3b53a..1fa706a2c3dc 100644
--- a/drivers/reset/starfive/Kconfig
+++ b/drivers/reset/starfive/Kconfig
@@ -10,3 +10,11 @@ config RESET_STARFIVE_JH7100
default ARCH_STARFIVE
help
This enables the reset controller driver for the StarFive JH7100 SoC.
+
+config RESET_STARFIVE_JH7110
+ bool "StarFive JH7110 Reset Driver"
+ depends on AUXILIARY_BUS && CLK_STARFIVE_JH7110_SYS
+ select RESET_STARFIVE_JH71X0
+ default ARCH_STARFIVE
+ help
+ This enables the reset controller driver for the StarFive JH7110 SoC.
diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
index f6aa12466fad..7a44b66fb9d5 100644
--- a/drivers/reset/starfive/Makefile
+++ b/drivers/reset/starfive/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
+obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c
new file mode 100644
index 000000000000..4ccb3f72ca83
--- /dev/null
+++ b/drivers/reset/starfive/reset-starfive-jh7110.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Reset driver for the StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/auxiliary_bus.h>
+
+#include "reset-starfive-jh71x0.h"
+
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+struct jh7110_reset_info {
+ unsigned int nr_resets;
+ unsigned int assert_offset;
+ unsigned int status_offset;
+};
+
+static const struct jh7110_reset_info jh7110_sys_info = {
+ .nr_resets = JH7110_SYSRST_END,
+ .assert_offset = 0x2F8,
+ .status_offset = 0x308,
+};
+
+static const struct jh7110_reset_info jh7110_aon_info = {
+ .nr_resets = JH7110_AONRST_END,
+ .assert_offset = 0x38,
+ .status_offset = 0x3C,
+};
+
+static int jh7110_reset_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id)
+{
+ struct jh7110_reset_info *info = (struct jh7110_reset_info *)(id->driver_data);
+ void __iomem **base = (void __iomem **)dev_get_drvdata(adev->dev.parent);
+
+ if (!info || !base)
+ return -ENODEV;
+
+ return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node,
+ *base + info->assert_offset,
+ *base + info->status_offset,
+ NULL,
+ info->nr_resets,
+ NULL);
+}
+
+static const struct auxiliary_device_id jh7110_reset_ids[] = {
+ {
+ .name = "clk_starfive_jh71x0.reset-sys",
+ .driver_data = (kernel_ulong_t)&jh7110_sys_info,
+ },
+ {
+ .name = "clk_starfive_jh71x0.reset-aon",
+ .driver_data = (kernel_ulong_t)&jh7110_aon_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(auxiliary, jh7110_reset_ids);
+
+static struct auxiliary_driver jh7110_reset_driver = {
+ .probe = jh7110_reset_probe,
+ .id_table = jh7110_reset_ids,
+};
+module_auxiliary_driver(jh7110_reset_driver);
+
+MODULE_AUTHOR("Hal Feng <hal.feng@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JH7110 reset driver");
+MODULE_LICENSE("GPL");
--
2.38.1
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next prev parent reply other threads:[~2023-03-20 10:38 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-20 10:37 [PATCH v6 00/21] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
2023-03-20 10:37 ` [PATCH v6 01/21] clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Hal Feng
2023-03-20 10:37 ` [PATCH v6 02/21] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng
2023-03-20 10:37 ` [PATCH v6 03/21] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h Hal Feng
2023-03-20 10:37 ` [PATCH v6 04/21] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-03-20 10:37 ` [PATCH v6 05/21] reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Hal Feng
2023-03-20 10:37 ` [PATCH v6 06/21] reset: Create subdirectory for StarFive drivers Hal Feng
2023-03-20 10:37 ` [PATCH v6 07/21] reset: starfive: Factor out common JH71X0 reset code Hal Feng
2023-03-20 10:37 ` [PATCH v6 08/21] reset: starfive: Extract the " Hal Feng
2023-03-20 10:37 ` [PATCH v6 09/21] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-03-20 10:37 ` [PATCH v6 10/21] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng
2023-03-20 10:37 ` [PATCH v6 11/21] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
2023-03-22 21:53 ` Conor Dooley
2023-03-22 23:57 ` Stephen Boyd
2023-03-23 7:44 ` Hal Feng
2023-03-23 9:01 ` Conor Dooley
2023-03-24 9:39 ` Emil Renner Berthing
2023-03-25 14:26 ` Hal Feng
2023-03-20 10:37 ` [PATCH v6 12/21] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng
2023-03-20 10:37 ` [PATCH v6 13/21] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
2023-03-24 14:39 ` Emil Renner Berthing
2023-03-25 15:54 ` Hal Feng
2023-03-26 20:06 ` Emil Renner Berthing
2023-03-26 20:13 ` Emil Renner Berthing
2023-03-27 18:51 ` Stephen Boyd
2023-03-27 23:08 ` Emil Renner Berthing
2023-03-20 10:37 ` [PATCH v6 14/21] clk: starfive: Add StarFive JH7110 always-on " Hal Feng
2023-03-20 10:37 ` Hal Feng [this message]
2023-03-20 10:37 ` [PATCH v6 16/21] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
2023-03-20 10:37 ` [PATCH v6 17/21] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
2023-03-20 10:37 ` [PATCH v6 18/21] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng
2023-03-20 10:37 ` [PATCH v6 19/21] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
2023-03-22 22:02 ` Conor Dooley
2023-03-23 9:03 ` Conor Dooley
2023-03-24 7:03 ` Hal Feng
2023-03-20 10:37 ` [PATCH v6 20/21] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Hal Feng
2023-03-20 10:37 ` [PATCH v6 21/21] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng
2023-03-21 23:03 ` [PATCH v6 00/21] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Conor Dooley
2023-03-21 23:57 ` Stephen Boyd
2023-03-22 21:06 ` Conor Dooley
2023-03-22 23:53 ` Stephen Boyd
2023-03-27 22:50 ` Conor Dooley
2023-03-28 1:42 ` Hal Feng
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