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From: Hal Feng <hal.feng@starfivetech.com>
To: Conor Dooley <conor.dooley@microchip.com>,
	Conor Dooley <conor@kernel.org>
Cc: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>,
	Stephen Boyd <sboyd@kernel.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Ben Dooks <ben.dooks@sifive.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	"Emil Renner Berthing" <emil.renner.berthing@canonical.com>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 19/21] riscv: dts: starfive: Add initial StarFive JH7110 device tree
Date: Fri, 24 Mar 2023 15:03:40 +0800	[thread overview]
Message-ID: <0c9c19ad-815c-fb0f-3024-96ea55e7c6c0@starfivetech.com> (raw)
In-Reply-To: <6ce5b897-f1c2-4b58-9353-9d9e881ad237@spud>

On Thu, 23 Mar 2023 09:03:23 +0000, Conor Dooley wrote:
> On Wed, Mar 22, 2023 at 10:02:40PM +0000, Conor Dooley wrote:
>> On Mon, Mar 20, 2023 at 06:37:48PM +0800, Hal Feng wrote:
>> > From: Emil Renner Berthing <kernel@esmil.dk>
>> > 
>> > Add initial device tree for the JH7110 RISC-V SoC by StarFive
>> > Technology Ltd.
>> > 
>> > Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
>> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> > Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> > ---
>> 
>> > +		S7_0: cpu@0 {
>> > +			compatible = "sifive,s7", "riscv";
>> > +			reg = <0>;
>> > +			d-cache-block-size = <64>;
>> > +			d-cache-sets = <64>;
>> > +			d-cache-size = <8192>;
>> > +			d-tlb-sets = <1>;
>> > +			d-tlb-size = <40>;
>> > +			device_type = "cpu";
>> > +			i-cache-block-size = <64>;
>> > +			i-cache-sets = <64>;
>> > +			i-cache-size = <16384>;
>> > +			i-tlb-sets = <1>;
>> > +			i-tlb-size = <40>;
>> > +			mmu-type = "riscv,sv39";
>> > +			next-level-cache = <&ccache>;
>> > +			riscv,isa = "rv64imac_zba_zbb";
>> > +			tlb-split;
>> > +			status = "disabled";
>> 
>> Jess pointed out on IRC that this S7 entry looks wrong as it is claiming
>> that the S7 has an mmu. I didn't go looking back in the history of
>> u74-mc core complex manuals, but the latest version does not show an mmu
>> for the S7.
> 
> BTW Hal, if the dt-binding stuff is okay with Emil, I can just remove
> the mmu here if you confirm it is a mistake rather than you needing to
> resubmit to remove it.

I confirm that the S7 core has no L1 data cache and MMU, so some properties
should be deleted. I have submitted a new patch for the correction.

https://lore.kernel.org/all/20230324064651.84670-1-hal.feng@starfivetech.com/

Best regards,
Hal

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  reply	other threads:[~2023-03-24  7:04 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-20 10:37 [PATCH v6 00/21] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
2023-03-20 10:37 ` [PATCH v6 01/21] clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Hal Feng
2023-03-20 10:37 ` [PATCH v6 02/21] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng
2023-03-20 10:37 ` [PATCH v6 03/21] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h Hal Feng
2023-03-20 10:37 ` [PATCH v6 04/21] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-03-20 10:37 ` [PATCH v6 05/21] reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Hal Feng
2023-03-20 10:37 ` [PATCH v6 06/21] reset: Create subdirectory for StarFive drivers Hal Feng
2023-03-20 10:37 ` [PATCH v6 07/21] reset: starfive: Factor out common JH71X0 reset code Hal Feng
2023-03-20 10:37 ` [PATCH v6 08/21] reset: starfive: Extract the " Hal Feng
2023-03-20 10:37 ` [PATCH v6 09/21] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-03-20 10:37 ` [PATCH v6 10/21] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng
2023-03-20 10:37 ` [PATCH v6 11/21] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
2023-03-22 21:53   ` Conor Dooley
2023-03-22 23:57     ` Stephen Boyd
2023-03-23  7:44     ` Hal Feng
2023-03-23  9:01       ` Conor Dooley
2023-03-24  9:39         ` Emil Renner Berthing
2023-03-25 14:26           ` Hal Feng
2023-03-20 10:37 ` [PATCH v6 12/21] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng
2023-03-20 10:37 ` [PATCH v6 13/21] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
2023-03-24 14:39   ` Emil Renner Berthing
2023-03-25 15:54     ` Hal Feng
2023-03-26 20:06       ` Emil Renner Berthing
2023-03-26 20:13   ` Emil Renner Berthing
2023-03-27 18:51   ` Stephen Boyd
2023-03-27 23:08   ` Emil Renner Berthing
2023-03-20 10:37 ` [PATCH v6 14/21] clk: starfive: Add StarFive JH7110 always-on " Hal Feng
2023-03-20 10:37 ` [PATCH v6 15/21] reset: starfive: Add StarFive JH7110 reset driver Hal Feng
2023-03-20 10:37 ` [PATCH v6 16/21] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
2023-03-20 10:37 ` [PATCH v6 17/21] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
2023-03-20 10:37 ` [PATCH v6 18/21] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng
2023-03-20 10:37 ` [PATCH v6 19/21] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
2023-03-22 22:02   ` Conor Dooley
2023-03-23  9:03     ` Conor Dooley
2023-03-24  7:03       ` Hal Feng [this message]
2023-03-20 10:37 ` [PATCH v6 20/21] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Hal Feng
2023-03-20 10:37 ` [PATCH v6 21/21] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng
2023-03-21 23:03 ` [PATCH v6 00/21] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Conor Dooley
2023-03-21 23:57   ` Stephen Boyd
2023-03-22 21:06     ` Conor Dooley
2023-03-22 23:53       ` Stephen Boyd
2023-03-27 22:50 ` Conor Dooley
2023-03-28  1:42   ` Hal Feng

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