From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
To: Hal Feng <hal.feng@starfivetech.com>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Ben Dooks <ben.dooks@sifive.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6 13/21] clk: starfive: Add StarFive JH7110 system clock driver
Date: Sun, 26 Mar 2023 22:06:29 +0200 [thread overview]
Message-ID: <CAJM55Z-GAFO_7sUv0KeX28h=PWRscDie1S2=+kg6O0rZevhBug@mail.gmail.com> (raw)
In-Reply-To: <c7bd699c-77fe-c01b-bbc6-be7ddc511a20@starfivetech.com>
On Sat, 25 Mar 2023 at 16:54, Hal Feng <hal.feng@starfivetech.com> wrote:
> On Fri, 24 Mar 2023 15:39:54 +0100, Emil Renner Berthing wrote:
> > On Mon, 20 Mar 2023 at 11:38, Hal Feng <hal.feng@starfivetech.com> wrote:
> [...]
> >> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> >> new file mode 100644
> >> index 000000000000..f98a508969c3
> >> --- /dev/null
> >> +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> >> @@ -0,0 +1,450 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * StarFive JH7110 System Clock Driver
> >> + *
> >> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> >> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> >> + */
> >> +
> >> +#include <linux/clk.h>
> >> +#include <linux/clk-provider.h>
> >> +#include <linux/init.h>
> >> +#include <linux/io.h>
> >> +#include <linux/platform_device.h>
> >> +
> >> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
> >> +
> >> +#include "clk-starfive-jh71x0.h"
> >> +
> >> +/* external clocks */
> >> +#define JH7110_SYSCLK_OSC (JH7110_SYSCLK_END + 0)
> >> +#define JH7110_SYSCLK_GMAC1_RMII_REFIN (JH7110_SYSCLK_END + 1)
> >> +#define JH7110_SYSCLK_GMAC1_RGMII_RXIN (JH7110_SYSCLK_END + 2)
> >> +#define JH7110_SYSCLK_I2STX_BCLK_EXT (JH7110_SYSCLK_END + 3)
> >> +#define JH7110_SYSCLK_I2STX_LRCK_EXT (JH7110_SYSCLK_END + 4)
> >> +#define JH7110_SYSCLK_I2SRX_BCLK_EXT (JH7110_SYSCLK_END + 5)
> >> +#define JH7110_SYSCLK_I2SRX_LRCK_EXT (JH7110_SYSCLK_END + 6)
> >> +#define JH7110_SYSCLK_TDM_EXT (JH7110_SYSCLK_END + 7)
> >> +#define JH7110_SYSCLK_MCLK_EXT (JH7110_SYSCLK_END + 8)
> >> +#define JH7110_SYSCLK_PLL0_OUT (JH7110_SYSCLK_END + 9)
> >> +#define JH7110_SYSCLK_PLL1_OUT (JH7110_SYSCLK_END + 10)
> >> +#define JH7110_SYSCLK_PLL2_OUT (JH7110_SYSCLK_END + 11)
> >> +
> >> +static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
> >> + /* root */
> >> + JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
> >> + JH7110_SYSCLK_OSC,
> >> + JH7110_SYSCLK_PLL0_OUT),
> >> + JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT),
> [...]
> >> + /* qspi */
> >> + JH71X0_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_AHB1),
> >> + JH71X0_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_APB_BUS),
> >
> > Hi Hal,
> >
> > Thanks for going through clocks marked with CLK_IGNORE_UNUSED and
> > either remove the flags or mark them as critical.. It seems you've
> > missed these two though.
>
> The QSPI module of JH7110 supported by Cadence, requires three
> clocks (qspi_ahb, qspi_apb and qspi_ref), but the Cadence QSPI
> driver only supports one clock. As the StarFive QSPI support
> patches [1] had been accepted, I kept these two flags here.
The QSPI driver obviously needs to be fixed so it doesn't depend on
the bootloader leaving the clocks enabled. I don't think we should add
these flags just to work around that until it gets fixed.
> [1] https://lore.kernel.org/all/20230302105221.197421-1-william.qiu@starfivetech.com/
>
> >
> [...]
> >> diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c
> >> index b372083d11c3..a8c60630ae73 100644
> >> --- a/drivers/clk/starfive/clk-starfive-jh71x0.c
> >> +++ b/drivers/clk/starfive/clk-starfive-jh71x0.c
> >> @@ -5,6 +5,7 @@
> >> * Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
> >> */
> >>
> >> +#include <linux/auxiliary_bus.h>
> >> #include <linux/clk-provider.h>
> >> #include <linux/debugfs.h>
> >> #include <linux/device.h>
> >> @@ -331,3 +332,52 @@ const struct clk_ops *starfive_jh71x0_clk_ops(u32 max)
> >> return &jh71x0_clk_inv_ops;
> >> }
> >> EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops);
> >> +
> >> +#if IS_ENABLED(CONFIG_CLK_STARFIVE_JH7110_SYS)
> >> +
> >> +static void jh7110_reset_unregister_adev(void *_adev)
> >> +{
> >> + struct auxiliary_device *adev = _adev;
> >> +
> >> + auxiliary_device_delete(adev);
> >> +}
> >> +
> >> +static void jh7110_reset_adev_release(struct device *dev)
> >> +{
> >> + struct auxiliary_device *adev = to_auxiliary_dev(dev);
> >> +
> >> + auxiliary_device_uninit(adev);
> >> +}
> >> +
> >> +int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
> >> + const char *adev_name,
> >> + u32 adev_id)
> >> +{
> >> + struct auxiliary_device *adev;
> >> + int ret;
> >> +
> >> + adev = devm_kzalloc(priv->dev, sizeof(*adev), GFP_KERNEL);
> >> + if (!adev)
> >> + return -ENOMEM;
> >> +
> >> + adev->name = adev_name;
> >> + adev->dev.parent = priv->dev;
> >> + adev->dev.release = jh7110_reset_adev_release;
> >> + adev->id = adev_id;
> >> +
> >> + ret = auxiliary_device_init(adev);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + ret = auxiliary_device_add(adev);
> >> + if (ret) {
> >> + auxiliary_device_uninit(adev);
> >> + return ret;
> >> + }
> >> +
> >> + return devm_add_action_or_reset(priv->dev,
> >> + jh7110_reset_unregister_adev, adev);
> >> +}
> >> +EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
> >> +
> >> +#endif
> >
> > Hey, sorry for not noticing this before, but is there a reason these
> > JH7110-specific functions must be added to the generic JH71x0 code?
> > Can't they be added to the JH7110 SYSCRG driver, and then let the
> > other CRG drivers depend on that (which they already do because of
> > clock dependencies)?
>
> It's ok to move these functions to clk-starfive-jh7110-sys.c. By the
> way, could I still keep the declaration in clk-starfive-jh71x0.h?
I'd just add a clk-starfive-jh7110.h file.
> Best regards,
> Hal
>
> >
> >> diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h
> >> index 34bb11c72eb7..cfe69aabd65a 100644
> >> --- a/drivers/clk/starfive/clk-starfive-jh71x0.h
> >> +++ b/drivers/clk/starfive/clk-starfive-jh71x0.h
> >> @@ -120,4 +120,12 @@ struct jh71x0_clk_priv {
> >>
> >> const struct clk_ops *starfive_jh71x0_clk_ops(u32 max);
> >>
> >> +#if IS_ENABLED(CONFIG_CLK_STARFIVE_JH7110_SYS)
> >> +
> >> +int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
> >> + const char *adev_name,
> >> + u32 adev_id);
> >> +
> >> +#endif
> >> +
> >> #endif
> >> --
> >> 2.38.1
> >>
>
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next prev parent reply other threads:[~2023-03-26 20:07 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-20 10:37 [PATCH v6 00/21] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
2023-03-20 10:37 ` [PATCH v6 01/21] clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Hal Feng
2023-03-20 10:37 ` [PATCH v6 02/21] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng
2023-03-20 10:37 ` [PATCH v6 03/21] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h Hal Feng
2023-03-20 10:37 ` [PATCH v6 04/21] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-03-20 10:37 ` [PATCH v6 05/21] reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Hal Feng
2023-03-20 10:37 ` [PATCH v6 06/21] reset: Create subdirectory for StarFive drivers Hal Feng
2023-03-20 10:37 ` [PATCH v6 07/21] reset: starfive: Factor out common JH71X0 reset code Hal Feng
2023-03-20 10:37 ` [PATCH v6 08/21] reset: starfive: Extract the " Hal Feng
2023-03-20 10:37 ` [PATCH v6 09/21] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-03-20 10:37 ` [PATCH v6 10/21] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng
2023-03-20 10:37 ` [PATCH v6 11/21] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
2023-03-22 21:53 ` Conor Dooley
2023-03-22 23:57 ` Stephen Boyd
2023-03-23 7:44 ` Hal Feng
2023-03-23 9:01 ` Conor Dooley
2023-03-24 9:39 ` Emil Renner Berthing
2023-03-25 14:26 ` Hal Feng
2023-03-20 10:37 ` [PATCH v6 12/21] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng
2023-03-20 10:37 ` [PATCH v6 13/21] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
2023-03-24 14:39 ` Emil Renner Berthing
2023-03-25 15:54 ` Hal Feng
2023-03-26 20:06 ` Emil Renner Berthing [this message]
2023-03-26 20:13 ` Emil Renner Berthing
2023-03-27 18:51 ` Stephen Boyd
2023-03-27 23:08 ` Emil Renner Berthing
2023-03-20 10:37 ` [PATCH v6 14/21] clk: starfive: Add StarFive JH7110 always-on " Hal Feng
2023-03-20 10:37 ` [PATCH v6 15/21] reset: starfive: Add StarFive JH7110 reset driver Hal Feng
2023-03-20 10:37 ` [PATCH v6 16/21] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
2023-03-20 10:37 ` [PATCH v6 17/21] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
2023-03-20 10:37 ` [PATCH v6 18/21] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng
2023-03-20 10:37 ` [PATCH v6 19/21] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
2023-03-22 22:02 ` Conor Dooley
2023-03-23 9:03 ` Conor Dooley
2023-03-24 7:03 ` Hal Feng
2023-03-20 10:37 ` [PATCH v6 20/21] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Hal Feng
2023-03-20 10:37 ` [PATCH v6 21/21] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng
2023-03-21 23:03 ` [PATCH v6 00/21] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Conor Dooley
2023-03-21 23:57 ` Stephen Boyd
2023-03-22 21:06 ` Conor Dooley
2023-03-22 23:53 ` Stephen Boyd
2023-03-27 22:50 ` Conor Dooley
2023-03-28 1:42 ` Hal Feng
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