Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller

From: Conor Dooley <conor@kernel.org>
To: Eric Lin <eric.lin@sifive.com>
Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	conor+dt@kernel.org, palmer@dabbelt.com,
	paul.walmsley@sifive.com, will@kernel.org, mark.rutland@arm.com,
	tglx@linutronix.de, peterz@infradead.org,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, zong.li@sifive.com,
	greentime.hu@sifive.com, vincent.chen@sifive.com,
	Nick Hu <nick.hu@sifive.com>
Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Date: Thu, 20 Jul 2023 18:10:51 +0100	[thread overview]
Message-ID: <20230720-slept-guru-216e2803061e@spud> (raw)
In-Reply-To: <20230720135125.21240-2-eric.lin@sifive.com>

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Hey Eric,

On Thu, Jul 20, 2023 at 09:51:19PM +0800, Eric Lin wrote:
> This add YAML DT binding documentation for SiFive Private L2
> cache controller
> 
> Signed-off-by: Eric Lin <eric.lin@sifive.com>
> Reviewed-by: Zong Li <zong.li@sifive.com>
> Reviewed-by: Nick Hu <nick.hu@sifive.com>
> ---
>  .../bindings/cache/sifive,pl2cache.yaml       | 62 +++++++++++++++++++

btw, your $subject should be "dt-bindings: cache: ...." rather than
"riscv: sifive".

>  1 file changed, 62 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> 
> diff --git a/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> new file mode 100644
> index 000000000000..ee8356c5eeee
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright (C) 2023 SiFive, Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SiFive Private L2 Cache Controller
> +
> +maintainers:
> +  - Greentime Hu  <greentime.hu@sifive.com>
> +  - Eric Lin  <eric.lin@sifive.com>

There's extra spaces in these lines for some reason.

> +
> +description:
> +  The SiFive Private L2 Cache Controller is per core and
> +  communicates with both the upstream L1 caches and
> +  downstream L3 cache or memory, enabling a high-performance
> +  cache subsystem.
> +
> +allOf:
> +  - $ref: /schemas/cache-controller.yaml#
> +

I'm pretty sure that I pointed out last time around that you need to add
something like in the ccache driver:

select:
  properties:
    compatible:
      contains:
        enum:
          - sifive,ccache0
          - sifive,fu540-c000-ccache
          - sifive,fu740-c000-ccache

otherwise this binding will be used for anything containing "cache" in
the dt-binding.
For this binding, I think that the following is sufficient:

select:
  properties:
    compatible:
      contains:
          const: sifive,pl2cache1

> +properties:
> +  compatible:
> +    items:
> +      - const: sifive,pl2cache1
> +      - const: cache

You omitted the pl2cache0 from here, that needs to come back! You'll end
up with 2 items entries.
Either way, I can't take this binding without a soc-specific compatible,
per sifive-blocks-ip-versioning.txt..

Thanks,
Conor.

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