From: Conor Dooley <conor.dooley@microchip.com>
To: Conor Dooley <conor@kernel.org>
Cc: Eric Lin <eric.lin@sifive.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
<palmer@dabbelt.com>, <paul.walmsley@sifive.com>,
<will@kernel.org>, <mark.rutland@arm.com>, <tglx@linutronix.de>,
<peterz@infradead.org>, <devicetree@vger.kernel.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<zong.li@sifive.com>, <greentime.hu@sifive.com>,
<vincent.chen@sifive.com>, Nick Hu <nick.hu@sifive.com>
Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Date: Fri, 28 Jul 2023 08:05:46 +0100 [thread overview]
Message-ID: <20230728-facedown-husked-9813fa79d9a0@wendy> (raw)
In-Reply-To: <20230720-slept-guru-216e2803061e@spud>
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On Thu, Jul 20, 2023 at 06:10:51PM +0100, Conor Dooley wrote:
> Hey Eric,
>
> On Thu, Jul 20, 2023 at 09:51:19PM +0800, Eric Lin wrote:
> > This add YAML DT binding documentation for SiFive Private L2
> > cache controller
> >
> > Signed-off-by: Eric Lin <eric.lin@sifive.com>
> > Reviewed-by: Zong Li <zong.li@sifive.com>
> > Reviewed-by: Nick Hu <nick.hu@sifive.com>
> > ---
> > .../bindings/cache/sifive,pl2cache.yaml | 62 +++++++++++++++++++
>
> btw, your $subject should be "dt-bindings: cache: ...." rather than
> "riscv: sifive".
>
> > 1 file changed, 62 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> > new file mode 100644
> > index 000000000000..ee8356c5eeee
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> > @@ -0,0 +1,62 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +# Copyright (C) 2023 SiFive, Inc.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SiFive Private L2 Cache Controller
> > +
> > +maintainers:
> > + - Greentime Hu <greentime.hu@sifive.com>
> > + - Eric Lin <eric.lin@sifive.com>
>
> There's extra spaces in these lines for some reason.
>
> > +
> > +description:
> > + The SiFive Private L2 Cache Controller is per core and
> > + communicates with both the upstream L1 caches and
> > + downstream L3 cache or memory, enabling a high-performance
> > + cache subsystem.
> > +
> > +allOf:
> > + - $ref: /schemas/cache-controller.yaml#
> > +
>
> I'm pretty sure that I pointed out last time around that you need to add
> something like in the ccache driver:
>
> select:
> properties:
> compatible:
> contains:
> enum:
> - sifive,ccache0
> - sifive,fu540-c000-ccache
> - sifive,fu740-c000-ccache
>
> otherwise this binding will be used for anything containing "cache" in
> the dt-binding.
> For this binding, I think that the following is sufficient:
>
> select:
> properties:
> compatible:
> contains:
> const: sifive,pl2cache1
>
> > +properties:
> > + compatible:
> > + items:
> > + - const: sifive,pl2cache1
> > + - const: cache
>
> You omitted the pl2cache0 from here, that needs to come back! You'll end
> up with 2 items entries.
> Either way, I can't take this binding without a soc-specific compatible,
> per sifive-blocks-ip-versioning.txt..
Further, "sifive,perfmon-counters" is an undocumented property.
Thanks,
Conor.
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next prev parent reply other threads:[~2023-07-28 7:06 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-20 13:51 [PATCH v2 0/3] Add SiFive Private L2 cache and PMU driver Eric Lin
2023-07-20 13:51 ` [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Eric Lin
2023-07-20 14:47 ` Rob Herring
2023-07-21 10:21 ` Eric Lin
2023-07-20 17:10 ` Conor Dooley
2023-07-28 7:05 ` Conor Dooley [this message]
2023-07-28 8:24 ` Eric Lin
2023-07-28 11:06 ` Conor Dooley
2023-09-05 15:07 ` Eric Lin
2023-07-21 8:34 ` Krzysztof Kozlowski
2023-07-28 6:01 ` Eric Lin
2023-07-28 6:46 ` Conor Dooley
2023-07-28 7:20 ` Eric Lin
2023-07-28 6:58 ` Krzysztof Kozlowski
2023-07-28 9:04 ` Eric Lin
2023-07-28 9:39 ` Krzysztof Kozlowski
2023-08-01 10:59 ` Eric Lin
2023-07-20 13:51 ` [PATCH v2 2/3] soc: sifive: Add SiFive private L2 cache driver Eric Lin
2023-07-28 7:15 ` Conor Dooley
2023-07-20 13:51 ` [PATCH v2 3/3] soc: sifive: Add SiFive private L2 cache PMU driver Eric Lin
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