From: Eric Lin <eric.lin@sifive.com>
To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, will@kernel.org, mark.rutland@arm.com,
tglx@linutronix.de, peterz@infradead.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: zong.li@sifive.com, greentime.hu@sifive.com,
vincent.chen@sifive.com, Eric Lin <eric.lin@sifive.com>,
Nick Hu <nick.hu@sifive.com>
Subject: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Date: Thu, 20 Jul 2023 21:51:19 +0800 [thread overview]
Message-ID: <20230720135125.21240-2-eric.lin@sifive.com> (raw)
In-Reply-To: <20230720135125.21240-1-eric.lin@sifive.com>
This add YAML DT binding documentation for SiFive Private L2
cache controller
Signed-off-by: Eric Lin <eric.lin@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Nick Hu <nick.hu@sifive.com>
---
.../bindings/cache/sifive,pl2cache.yaml | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
diff --git a/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
new file mode 100644
index 000000000000..ee8356c5eeee
--- /dev/null
+++ b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2023 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive Private L2 Cache Controller
+
+maintainers:
+ - Greentime Hu <greentime.hu@sifive.com>
+ - Eric Lin <eric.lin@sifive.com>
+
+description:
+ The SiFive Private L2 Cache Controller is per core and
+ communicates with both the upstream L1 caches and
+ downstream L3 cache or memory, enabling a high-performance
+ cache subsystem.
+
+allOf:
+ - $ref: /schemas/cache-controller.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: sifive,pl2cache1
+ - const: cache
+
+ cache-block-size: true
+ cache-level: true
+ cache-sets: true
+ cache-size: true
+ cache-unified: true
+
+ reg:
+ maxItems: 1
+
+ next-level-cache: true
+
+required:
+ - compatible
+ - cache-block-size
+ - cache-level
+ - cache-sets
+ - cache-size
+ - cache-unified
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ cache-controller@10104000 {
+ compatible = "sifive,pl2cache1","cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ reg = <0x10104000 0x4000>;
+ next-level-cache = <&L4>;
+ };
--
2.40.1
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next prev parent reply other threads:[~2023-07-20 13:52 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-20 13:51 [PATCH v2 0/3] Add SiFive Private L2 cache and PMU driver Eric Lin
2023-07-20 13:51 ` Eric Lin [this message]
2023-07-20 14:47 ` [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Rob Herring
2023-07-21 10:21 ` Eric Lin
2023-07-20 17:10 ` Conor Dooley
2023-07-28 7:05 ` Conor Dooley
2023-07-28 8:24 ` Eric Lin
2023-07-28 11:06 ` Conor Dooley
2023-09-05 15:07 ` Eric Lin
2023-07-21 8:34 ` Krzysztof Kozlowski
2023-07-28 6:01 ` Eric Lin
2023-07-28 6:46 ` Conor Dooley
2023-07-28 7:20 ` Eric Lin
2023-07-28 6:58 ` Krzysztof Kozlowski
2023-07-28 9:04 ` Eric Lin
2023-07-28 9:39 ` Krzysztof Kozlowski
2023-08-01 10:59 ` Eric Lin
2023-07-20 13:51 ` [PATCH v2 2/3] soc: sifive: Add SiFive private L2 cache driver Eric Lin
2023-07-28 7:15 ` Conor Dooley
2023-07-20 13:51 ` [PATCH v2 3/3] soc: sifive: Add SiFive private L2 cache PMU driver Eric Lin
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