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From: Eric Lin <eric.lin@sifive.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	conor+dt@kernel.org,  devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org,  linux-kernel@vger.kernel.org,
	zong.li@sifive.com, greentime.hu@sifive.com,
	 vincent.chen@sifive.com
Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Date: Tue, 1 Aug 2023 18:59:34 +0800	[thread overview]
Message-ID: <CAPqJEFrYrbH2H5F=V4D4-exLjmnuJybj8L2GKPzqhTrDsqe-gA@mail.gmail.com> (raw)
In-Reply-To: <f7df407e-1deb-f667-912c-81415fffcbfd@linaro.org>

On Fri, Jul 28, 2023 at 5:39 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 28/07/2023 11:04, Eric Lin wrote:
> > On Fri, Jul 28, 2023 at 2:58 PM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 28/07/2023 08:01, Eric Lin wrote:
> >>> Hi Krzysztof,
> >>>
> >>> On Fri, Jul 21, 2023 at 4:35 PM Krzysztof Kozlowski
> >>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>
> >>>> On 20/07/2023 15:51, Eric Lin wrote:
> >>>>> This add YAML DT binding documentation for SiFive Private L2
> >>>>> cache controller
> >>>>>
> >>>>> Signed-off-by: Eric Lin <eric.lin@sifive.com>
> >>>>> Reviewed-by: Zong Li <zong.li@sifive.com>
> >>>>> Reviewed-by: Nick Hu <nick.hu@sifive.com>
> >>>>
> >>>>
> >>>> ...
> >>>>
> >>>>> +properties:
> >>>>> +  compatible:
> >>>>> +    items:
> >>>>> +      - const: sifive,pl2cache1
> >>>>
> >>>> I still have doubts that it is not used in any SoC. This is what you
> >>>> said last time: "is not part of any SoC."
> >>>> If not part of any SoC, then where is it? Why are you adding it to the
> >>>> kernel?
> >>>>
> >>>
> >>> Sorry for the late reply. I didn't describe it clearly last time.
> >>> Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1.
> >>> The pl2cache0 is used in unmatched board SoC. The pl2cache1 is
> >>> utilized in our internal FPGA platform for evaluation; it's our core
> >>> IP.
> >>
> >> And why do you add bindings for some internal FPGA IP block which does
> >> not interface with any SW?
> >>
> >
> > Hi Krzysztof,
> > The pl2cache has mmio interface for SW. Thanks.
>
> Then did you mean that FPGA represented some model of your SoC? If so,
> what are other bindings for that FPGA components?
>
Hi Krzysztof,

Sorry for the late reply.
Yes, here are the devices dt-binding that we use on the internal FPGA
SoC platform. Thanks.

uart:
Documentation/devicetree/bindings/serial/sifive-serial.yaml

gpio:
Documentation/devicetree/bindings/gpio/sifive,gpio.yaml

dma:
Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml

spi:
Documentation/devicetree/bindings/spi/spi-sifive.yaml

Best regards,
Eric Lin

> Best regards,
> Krzysztof
>

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  reply	other threads:[~2023-08-01 10:59 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-20 13:51 [PATCH v2 0/3] Add SiFive Private L2 cache and PMU driver Eric Lin
2023-07-20 13:51 ` [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Eric Lin
2023-07-20 14:47   ` Rob Herring
2023-07-21 10:21     ` Eric Lin
2023-07-20 17:10   ` Conor Dooley
2023-07-28  7:05     ` Conor Dooley
2023-07-28  8:24       ` Eric Lin
2023-07-28 11:06         ` Conor Dooley
2023-09-05 15:07     ` Eric Lin
2023-07-21  8:34   ` Krzysztof Kozlowski
2023-07-28  6:01     ` Eric Lin
2023-07-28  6:46       ` Conor Dooley
2023-07-28  7:20         ` Eric Lin
2023-07-28  6:58       ` Krzysztof Kozlowski
2023-07-28  9:04         ` Eric Lin
2023-07-28  9:39           ` Krzysztof Kozlowski
2023-08-01 10:59             ` Eric Lin [this message]
2023-07-20 13:51 ` [PATCH v2 2/3] soc: sifive: Add SiFive private L2 cache driver Eric Lin
2023-07-28  7:15   ` Conor Dooley
2023-07-20 13:51 ` [PATCH v2 3/3] soc: sifive: Add SiFive private L2 cache PMU driver Eric Lin

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