From: Conor Dooley <conor@kernel.org>
To: Ben Dooks <ben.dooks@codethink.co.uk>,
arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com
Cc: Conor Dooley <conor.dooley@microchip.com>,
ajones@ventanamicro.com, aou@eecs.berkeley.edu,
apatel@ventanamicro.com, atishp@rivosinc.com,
biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org,
geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org,
heiko@sntech.de, jszhang@kernel.org,
krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
linux-riscv@lists.infradead.org, magnus.damm@gmail.com,
nathan@kernel.org, paul.walmsley@sifive.com,
philipp.tomsich@vrull.eu,
prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org,
samuel@sholland.org, soc@kernel.org
Subject: Re: [RFC v5.1 6/9] cache,soc: Move SiFive CCache driver & create drivers/cache
Date: Wed, 04 Jan 2023 10:18:53 +0000 [thread overview]
Message-ID: <AA57B670-C952-47FE-9355-B4B1E4305CF6@kernel.org> (raw)
In-Reply-To: <49bd7b4a-b0e1-3213-8aed-9f39604f3935@codethink.co.uk>
On 4 January 2023 09:50:58 GMT, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>On 03/01/2023 21:03, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> The Zicbo* set of extensions for cache maintenance arrived too late &
>> several SoCs exist without them that require non-coherent DMA.
>> As things stand, the StarFive JH7100, Microchip PolarFire SoC & Renesas
>> RZ/Five all require cache maintenance and lack instructions for this
>> purpose.
>> Create a subsystem for cache drivers so that vendor specific behaviour
>> can be isolated from arch code, but keep the interfaces etc consistent.
>> Move the existing SiFive CCache driver to create drivers/cache.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> MAINTAINERS | 15 ++++++++-------
>> drivers/Kconfig | 2 ++
>> drivers/Makefile | 2 ++
>> drivers/{soc/sifive => cache}/Kconfig | 8 +++++++-
>> drivers/{soc/sifive => cache}/Makefile | 0
>> drivers/{soc/sifive => cache}/sifive_ccache.c | 2 +-
>> drivers/edac/sifive_edac.c | 2 +-
>> drivers/soc/Kconfig | 1 -
>> drivers/soc/Makefile | 1 -
>> include/{soc/sifive => cache}/sifive_ccache.h | 0
>> 10 files changed, 21 insertions(+), 12 deletions(-)
>> rename drivers/{soc/sifive => cache}/Kconfig (56%)
>> rename drivers/{soc/sifive => cache}/Makefile (100%)
>> rename drivers/{soc/sifive => cache}/sifive_ccache.c (99%)
>> rename include/{soc/sifive => cache}/sifive_ccache.h (100%)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index f61eb221415b..4437e96a657b 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -19054,13 +19054,6 @@ S: Maintained
>> F: Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
>> F: drivers/dma/sf-pdma/
>> -SIFIVE SOC DRIVERS
>> -M: Conor Dooley <conor@kernel.org>
>> -L: linux-riscv@lists.infradead.org
>> -S: Maintained
>> -T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
>> -F: drivers/soc/sifive/
>> -
>> SILEAD TOUCHSCREEN DRIVER
>> M: Hans de Goede <hdegoede@redhat.com>
>> L: linux-input@vger.kernel.org
>> @@ -19873,6 +19866,14 @@ S: Supported
>> T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git
>> F: drivers/staging/
>> +STANDALONE CACHE CONTROLLER DRIVERS
>> +M: Conor Dooley <conor@kernel.org>
>> +L: linux-riscv@lists.infradead.org
>> +S: Maintained
>> +T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
>> +F: drivers/cache
>> +F: include/cache
>I thought the riscv list was subscribers only?
Shouldn't be. At least, I'm not one on this account and I don't get complaints!
>Maybe if we do the suggestion of other cache drivers here we should
>either use the main kernel one or find some arch non-specific list.
Yah, good point. I just moved the existing one, otherwise my script would yell at me about the maintainers pattern ;)
>
>> +
>> STARFIRE/DURALAN NETWORK DRIVER
>> M: Ion Badulescu <ionut@badula.org>
>> S: Odd Fixes
>> diff --git a/drivers/Kconfig b/drivers/Kconfig
>> index 968bd0a6fd78..e592ba5276ae 100644
>> --- a/drivers/Kconfig
>> +++ b/drivers/Kconfig
>> @@ -241,4 +241,6 @@ source "drivers/peci/Kconfig"
>> source "drivers/hte/Kconfig"
>> +source "drivers/cache/Kconfig"
>> +
>> endmenu
>> diff --git a/drivers/Makefile b/drivers/Makefile
>> index bdf1c66141c9..6ff60cf21823 100644
>> --- a/drivers/Makefile
>> +++ b/drivers/Makefile
>> @@ -38,6 +38,8 @@ obj-y += clk/
>> # really early.
>> obj-$(CONFIG_DMADEVICES) += dma/
>> +obj-y += cache/
>> +
>> # SOC specific infrastructure drivers.
>> obj-y += soc/
>> diff --git a/drivers/soc/sifive/Kconfig b/drivers/cache/Kconfig
>> similarity index 56%
>> rename from drivers/soc/sifive/Kconfig
>> rename to drivers/cache/Kconfig
>> index ed4c571f8771..bc852f005c10 100644
>> --- a/drivers/soc/sifive/Kconfig
>> +++ b/drivers/cache/Kconfig
>> @@ -1,9 +1,15 @@
>> # SPDX-License-Identifier: GPL-2.0
>> -if SOC_SIFIVE
>> +menuconfig CACHE_CONTROLLER
>> + bool "Cache controller driver support"
>> + default y if RISCV
>> +
>> +if CACHE_CONTROLLER
>> config SIFIVE_CCACHE
>> bool "Sifive Composable Cache controller"
>> + depends on RISCV
>> + default y
>> help
>> Support for the composable cache controller on SiFive platforms.
>>
>
>Maybe we should find and move the ARM PL cache controllers and
>have them here too?
What to do there is up to Arnd et al :)
The maintainers entry would certainly have to look significantly different then.
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next prev parent reply other threads:[~2023-01-04 15:18 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-12 11:54 [PATCH v5 0/6] AX45MP: Add support to non-coherent DMA Prabhakar
2022-12-12 11:55 ` [PATCH v5 1/6] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Prabhakar
2022-12-12 12:32 ` Heiko Stuebner
2022-12-13 17:21 ` Geert Uytterhoeven
2022-12-13 17:49 ` Lad, Prabhakar
2022-12-14 14:34 ` Andrew Jones
2022-12-17 21:41 ` Conor Dooley
2022-12-19 11:15 ` Lad, Prabhakar
2022-12-19 16:22 ` Conor Dooley
2022-12-19 16:24 ` Lad, Prabhakar
2022-12-12 11:55 ` [PATCH v5 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2022-12-12 11:55 ` [PATCH v5 3/6] riscv: errata: Add Andes alternative ports Prabhakar
2022-12-17 21:19 ` Conor Dooley
2022-12-19 11:19 ` Lad, Prabhakar
2022-12-19 16:20 ` Conor Dooley
2022-12-21 0:31 ` Lad, Prabhakar
2022-12-12 11:55 ` [PATCH v5 4/6] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Prabhakar
2022-12-13 17:14 ` Geert Uytterhoeven
2022-12-13 17:57 ` Lad, Prabhakar
2022-12-17 20:52 ` Conor Dooley
2022-12-19 11:21 ` Lad, Prabhakar
2022-12-12 11:55 ` [PATCH v5 5/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2022-12-12 17:28 ` Rob Herring
2022-12-12 11:55 ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar
2022-12-15 10:34 ` Geert Uytterhoeven
2022-12-15 11:03 ` Lad, Prabhakar
2022-12-15 11:10 ` Geert Uytterhoeven
2022-12-15 17:46 ` Lad, Prabhakar
2022-12-15 19:54 ` Conor Dooley
2022-12-15 20:17 ` Geert Uytterhoeven
2022-12-15 20:32 ` Conor Dooley
2022-12-15 21:40 ` Palmer Dabbelt
2022-12-16 7:02 ` Christoph Hellwig
2022-12-16 16:32 ` Palmer Dabbelt
2022-12-16 20:04 ` Arnd Bergmann
2022-12-17 22:52 ` Conor Dooley
2022-12-19 12:43 ` Lad, Prabhakar
2022-12-19 16:08 ` Conor Dooley
2022-12-29 14:05 ` Arnd Bergmann
2022-12-29 14:42 ` Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 0/9] Generic function based cache management operations (was Re: [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC) Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 1/9] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 2/9] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 3/9] riscv: errata: Add Andes alternative ports Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 4/9] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 5/9] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 6/9] cache,soc: Move SiFive CCache driver & create drivers/cache Conor Dooley
2023-01-04 9:50 ` Ben Dooks
2023-01-04 10:18 ` Conor Dooley [this message]
2023-01-03 21:03 ` [RFC v5.1 7/9] RISC-V: create a function based cache management interface Conor Dooley
2023-01-03 21:04 ` [RFC v5.1 8/9] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley
2023-01-03 21:04 ` [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability Conor Dooley
2023-01-03 21:25 ` Palmer Dabbelt
2023-01-03 21:28 ` Arnd Bergmann
2023-01-04 0:00 ` Conor Dooley
2023-01-04 8:17 ` Arnd Bergmann
2023-01-04 9:23 ` Conor Dooley
2023-01-04 10:19 ` Arnd Bergmann
2023-01-04 11:56 ` Conor Dooley
2023-01-04 12:18 ` Arnd Bergmann
2023-01-04 13:20 ` Conor Dooley
2023-01-04 14:15 ` Arnd Bergmann
2023-01-04 9:45 ` Ben Dooks
2023-01-04 9:57 ` Conor Dooley
2022-12-17 21:35 ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley
2022-12-28 3:16 ` Samuel Holland
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