Re: [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability

From: Conor Dooley <conor@kernel.org>
To: Arnd Bergmann <arnd@arndb.de>
Cc: "Palmer Dabbelt" <palmer@dabbelt.com>,
	Prabhakar <prabhakar.csengg@gmail.com>,
	"Conor.Dooley" <conor.dooley@microchip.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Anup Patel" <apatel@ventanamicro.com>,
	"Atish Patra" <atishp@rivosinc.com>,
	"Biju Das" <biju.das.jz@bp.renesas.com>,
	devicetree@vger.kernel.org,
	"Geert Uytterhoeven" <geert@linux-m68k.org>,
	guoren <guoren@kernel.org>,
	"Christoph Hellwig" <hch@infradead.org>,
	"Heiko Stübner" <heiko@sntech.de>,
	"Jisheng Zhang" <jszhang@kernel.org>,
	krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	linux-riscv@lists.infradead.org,
	"Magnus Damm" <magnus.damm@gmail.com>,
	"Nathan Chancellor" <nathan@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
	"Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Samuel Holland" <samuel@sholland.org>,
	soc@kernel.org, "Daire McNamara" <daire.mcnamara@microchip.com>
Subject: Re: [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability
Date: Wed, 04 Jan 2023 09:23:14 +0000	[thread overview]
Message-ID: <CFB874A3-3E6F-4C5B-B47D-381EB1E07C02@kernel.org> (raw)
In-Reply-To: <ed198390-1bde-44ec-9f3f-b0e016b4b24c@app.fastmail.com>

On 4 January 2023 08:17:41 GMT, Arnd Bergmann <arnd@arndb.de> wrote:
>On Wed, Jan 4, 2023, at 01:00, Conor Dooley wrote:
>> On Tue, Jan 03, 2023 at 10:28:19PM +0100, Arnd Bergmann wrote:
>>> On Tue, Jan 3, 2023, at 22:04, Conor Dooley wrote:
>>> > From: Daire McNamara <daire.mcnamara@microchip.com>
>>> >
>>> > SiFive L2 cache controller can flush L2 cache. Expose this capability via
>>> > driver.
>>> >
>>> > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
>>> > [Conor: rebase on top of move to cache subsystem]
>>> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>> > ---
>>> > This commit needs more work, and a way to enable it from errata. I've
>>> > not gone and done this as PolarFire SoC has archid etc all set to zero.
>>> > So we need to go figure out a workaround for this, before adding in
>>> > errata enabling code for this. I've included it here as a second user of
>>> > the cache management stuff, since what's currently upstream for the
>>> > ccache driver does not do any cache management.
>>> > ---
>>> >  drivers/cache/sifive_ccache.c | 45 +++++++++++++++++++++++++++++++++++
>>> >  1 file changed, 45 insertions(+)
>>> 
>>> My feeling here is that the cacheflush code is unrelated to the
>>> EDAC code and it should just be a separate file. From what I can
>>> tell, all of the existing contents of this file can simply
>>> get merged into drivers/edac/sifive_edac.c, with the newly
>>> added code becoming a standalone driver.
>>
>> Sure? I'd like to do that independently of whatever is done for the
>> ax45mp CMOs though, don't think it's worth holding up that platform's
>> support on me splitting this out.
>
>Right, no need to touch the existing file as part of this series,
>it probably just gets in the way of defining a good interface here.

Sure. Can leave it where it was & I'll sort it out later when it's errata etc get added.

Btw, would you mind pointing out where you wanted to have that if/else you mentioned on IRC?

Thanks,
Conor.

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