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From: "Arnd Bergmann" <arnd@arndb.de>
To: "Conor Dooley" <conor@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	Prabhakar <prabhakar.csengg@gmail.com>
Cc: "Conor.Dooley" <conor.dooley@microchip.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Anup Patel" <apatel@ventanamicro.com>,
	"Atish Patra" <atishp@rivosinc.com>,
	"Biju Das" <biju.das.jz@bp.renesas.com>,
	devicetree@vger.kernel.org,
	"Geert Uytterhoeven" <geert@linux-m68k.org>,
	guoren <guoren@kernel.org>,
	"Christoph Hellwig" <hch@infradead.org>,
	"Heiko Stübner" <heiko@sntech.de>,
	"Jisheng Zhang" <jszhang@kernel.org>,
	krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	linux-riscv@lists.infradead.org,
	"Magnus Damm" <magnus.damm@gmail.com>,
	"Nathan Chancellor" <nathan@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
	"Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Samuel Holland" <samuel@sholland.org>,
	soc@kernel.org, "Daire McNamara" <daire.mcnamara@microchip.com>
Subject: Re: [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability
Date: Tue, 03 Jan 2023 22:28:19 +0100	[thread overview]
Message-ID: <b5712732-40a2-4e29-b29f-e0ab5516d518@app.fastmail.com> (raw)
In-Reply-To: <20230103210400.3500626-10-conor@kernel.org>

On Tue, Jan 3, 2023, at 22:04, Conor Dooley wrote:
> From: Daire McNamara <daire.mcnamara@microchip.com>
>
> SiFive L2 cache controller can flush L2 cache. Expose this capability via
> driver.
>
> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
> [Conor: rebase on top of move to cache subsystem]
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> This commit needs more work, and a way to enable it from errata. I've
> not gone and done this as PolarFire SoC has archid etc all set to zero.
> So we need to go figure out a workaround for this, before adding in
> errata enabling code for this. I've included it here as a second user of
> the cache management stuff, since what's currently upstream for the
> ccache driver does not do any cache management.
> ---
>  drivers/cache/sifive_ccache.c | 45 +++++++++++++++++++++++++++++++++++
>  1 file changed, 45 insertions(+)

My feeling here is that the cacheflush code is unrelated to the
EDAC code and it should just be a separate file. From what I can
tell, all of the existing contents of this file can simply
get merged into drivers/edac/sifive_edac.c, with the newly
added code becoming a standalone driver.

     Arnd

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  parent reply	other threads:[~2023-01-03 21:30 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-12 11:54 [PATCH v5 0/6] AX45MP: Add support to non-coherent DMA Prabhakar
2022-12-12 11:55 ` [PATCH v5 1/6] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Prabhakar
2022-12-12 12:32   ` Heiko Stuebner
2022-12-13 17:21   ` Geert Uytterhoeven
2022-12-13 17:49     ` Lad, Prabhakar
2022-12-14 14:34       ` Andrew Jones
2022-12-17 21:41   ` Conor Dooley
2022-12-19 11:15     ` Lad, Prabhakar
2022-12-19 16:22       ` Conor Dooley
2022-12-19 16:24         ` Lad, Prabhakar
2022-12-12 11:55 ` [PATCH v5 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2022-12-12 11:55 ` [PATCH v5 3/6] riscv: errata: Add Andes alternative ports Prabhakar
2022-12-17 21:19   ` Conor Dooley
2022-12-19 11:19     ` Lad, Prabhakar
2022-12-19 16:20       ` Conor Dooley
2022-12-21  0:31         ` Lad, Prabhakar
2022-12-12 11:55 ` [PATCH v5 4/6] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Prabhakar
2022-12-13 17:14   ` Geert Uytterhoeven
2022-12-13 17:57     ` Lad, Prabhakar
2022-12-17 20:52   ` Conor Dooley
2022-12-19 11:21     ` Lad, Prabhakar
2022-12-12 11:55 ` [PATCH v5 5/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2022-12-12 17:28   ` Rob Herring
2022-12-12 11:55 ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar
2022-12-15 10:34   ` Geert Uytterhoeven
2022-12-15 11:03     ` Lad, Prabhakar
2022-12-15 11:10       ` Geert Uytterhoeven
2022-12-15 17:46         ` Lad, Prabhakar
2022-12-15 19:54           ` Conor Dooley
2022-12-15 20:17             ` Geert Uytterhoeven
2022-12-15 20:32               ` Conor Dooley
2022-12-15 21:40               ` Palmer Dabbelt
2022-12-16  7:02                 ` Christoph Hellwig
2022-12-16 16:32                   ` Palmer Dabbelt
2022-12-16 20:04                     ` Arnd Bergmann
2022-12-17 22:52                       ` Conor Dooley
2022-12-19 12:43                         ` Lad, Prabhakar
2022-12-19 16:08                           ` Conor Dooley
2022-12-29 14:05                         ` Arnd Bergmann
2022-12-29 14:42                           ` Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 0/9] Generic function based cache management operations (was Re: [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC) Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 1/9] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 2/9] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 3/9] riscv: errata: Add Andes alternative ports Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 4/9] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 5/9] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 6/9] cache,soc: Move SiFive CCache driver & create drivers/cache Conor Dooley
2023-01-04  9:50                               ` Ben Dooks
2023-01-04 10:18                                 ` Conor Dooley
2023-01-03 21:03                             ` [RFC v5.1 7/9] RISC-V: create a function based cache management interface Conor Dooley
2023-01-03 21:04                             ` [RFC v5.1 8/9] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley
2023-01-03 21:04                             ` [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability Conor Dooley
2023-01-03 21:25                               ` Palmer Dabbelt
2023-01-03 21:28                               ` Arnd Bergmann [this message]
2023-01-04  0:00                                 ` Conor Dooley
2023-01-04  8:17                                   ` Arnd Bergmann
2023-01-04  9:23                                     ` Conor Dooley
2023-01-04 10:19                                       ` Arnd Bergmann
2023-01-04 11:56                                         ` Conor Dooley
2023-01-04 12:18                                           ` Arnd Bergmann
2023-01-04 13:20                                             ` Conor Dooley
2023-01-04 14:15                                               ` Arnd Bergmann
2023-01-04  9:45                               ` Ben Dooks
2023-01-04  9:57                                 ` Conor Dooley
2022-12-17 21:35   ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley
2022-12-28  3:16   ` Samuel Holland

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