From: Conor Dooley <conor@kernel.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Heiko Stuebner <heiko@sntech.de>,
Conor Dooley <conor.dooley@microchip.com>,
Samuel Holland <samuel@sholland.org>, Guo Ren <guoren@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Jisheng Zhang <jszhang@kernel.org>,
Atish Patra <atishp@rivosinc.com>,
Anup Patel <apatel@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Nathan Chancellor <nathan@kernel.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v5 4/6] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP()
Date: Sat, 17 Dec 2022 20:52:11 +0000 [thread overview]
Message-ID: <Y54r+5lkSvgA9IxR@spud> (raw)
In-Reply-To: <20221212115505.36770-5-prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hey Prabhakar,
On Mon, Dec 12, 2022 at 11:55:03AM +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Pass direction and operation to ALT_CMO_OP() macro.
>
> Vendors might want to perform different operations based on the direction
> and callbacks (arch_sync_dma_for_device/arch_sync_dma_for_cpu/
> arch_dma_prep_coherent) so to handle such cases pass the direction and
> operation to ALT_CMO_OP() macro. This is in preparation for adding errata
> for the Andes CPU core.
This patch seems to break the build on top of the most recent
linux-next:
......./stuff/linux/arch/riscv/mm/pmem.c:13:53: error: too few arguments provided to function-like macro invocation
ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size);
^
/stuff/linux/arch/riscv/include/asm/errata_list.h:127:9: note: macro 'ALT_CMO_OP' defined here
#define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \
^
.. CC block/partitions/sgi.o
.+...+/stuff/linux/arch/riscv/mm/pmem.c:13:2: error: use of undeclared identifier 'ALT_CMO_OP'
ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size);
^
/stuff/linux/arch/riscv/mm/pmem.c:19:53: error: too few arguments provided to function-like macro invocation
ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size);
^
/stuff/linux/arch/riscv/include/asm/errata_list.h:127:9: note: macro 'ALT_CMO_OP' defined here
#define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \
^
........... AR lib/math/built-in.a
./stuff/linux/arch/riscv/mm/pmem.c:19:2: .error: use of undeclared identifier 'ALT_CMO_OP'
ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size);
^
..4 errors generated.
The pmem stuff is new so that'd be why it has not come up before.
(FWIW, clang allmodconfig)
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v4 -> v5
> * Updated commit message.
>
> RFC v3 -> v4
> * New patch
> ---
> arch/riscv/include/asm/cacheflush.h | 4 ++++
> arch/riscv/include/asm/errata_list.h | 8 ++++++--
> arch/riscv/mm/dma-noncoherent.c | 15 ++++++++++-----
> 3 files changed, 20 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
> index 03e3b95ae6da..e22019668b9e 100644
> --- a/arch/riscv/include/asm/cacheflush.h
> +++ b/arch/riscv/include/asm/cacheflush.h
> @@ -8,6 +8,10 @@
>
> #include <linux/mm.h>
>
> +#define NON_COHERENT_SYNC_DMA_FOR_DEVICE 0
> +#define NON_COHERENT_SYNC_DMA_FOR_CPU 1
> +#define NON_COHERENT_DMA_PREP 2
> +
> static inline void local_flush_icache_all(void)
> {
> asm volatile ("fence.i" ::: "memory");
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 2ba7e6e74540..48e899a8e7a9 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -124,7 +124,7 @@ asm volatile(ALTERNATIVE( \
> #define THEAD_flush_A0 ".long 0x0275000b"
> #define THEAD_SYNC_S ".long 0x0190000b"
>
> -#define ALT_CMO_OP(_op, _start, _size, _cachesize) \
> +#define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \
> asm volatile(ALTERNATIVE_2( \
> __nops(6), \
> "mv a0, %1\n\t" \
> @@ -146,7 +146,11 @@ asm volatile(ALTERNATIVE_2( \
> ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \
> : : "r"(_cachesize), \
> "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \
> - "r"((unsigned long)(_start) + (_size)) \
> + "r"((unsigned long)(_start) + (_size)), \
> + "r"((unsigned long)(_start)), \
> + "r"((unsigned long)(_size)), \
> + "r"((unsigned long)(_dir)), \
> + "r"((unsigned long)(_ops)) \
> : "a0")
>
> #define THEAD_C9XX_RV_IRQ_PMU 17
> diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
> index d919efab6eba..e2b82034f504 100644
> --- a/arch/riscv/mm/dma-noncoherent.c
> +++ b/arch/riscv/mm/dma-noncoherent.c
> @@ -19,13 +19,16 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
>
> switch (dir) {
> case DMA_TO_DEVICE:
> - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
> + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size,
> + dir, NON_COHERENT_SYNC_DMA_FOR_DEVICE);
> break;
> case DMA_FROM_DEVICE:
> - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
> + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size,
> + dir, NON_COHERENT_SYNC_DMA_FOR_DEVICE);
> break;
> case DMA_BIDIRECTIONAL:
> - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
> + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size,
> + dir, NON_COHERENT_SYNC_DMA_FOR_DEVICE);
> break;
> default:
> break;
> @@ -42,7 +45,8 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
> break;
> case DMA_FROM_DEVICE:
> case DMA_BIDIRECTIONAL:
> - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
> + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size,
> + dir, NON_COHERENT_SYNC_DMA_FOR_CPU);
> break;
> default:
> break;
> @@ -53,7 +57,8 @@ void arch_dma_prep_coherent(struct page *page, size_t size)
> {
> void *flush_addr = page_address(page);
>
> - ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
> + ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size,
> + 0, NON_COHERENT_DMA_PREP);
> }
>
> void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
> --
> 2.25.1
>
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next prev parent reply other threads:[~2022-12-17 20:52 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-12 11:54 [PATCH v5 0/6] AX45MP: Add support to non-coherent DMA Prabhakar
2022-12-12 11:55 ` [PATCH v5 1/6] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Prabhakar
2022-12-12 12:32 ` Heiko Stuebner
2022-12-13 17:21 ` Geert Uytterhoeven
2022-12-13 17:49 ` Lad, Prabhakar
2022-12-14 14:34 ` Andrew Jones
2022-12-17 21:41 ` Conor Dooley
2022-12-19 11:15 ` Lad, Prabhakar
2022-12-19 16:22 ` Conor Dooley
2022-12-19 16:24 ` Lad, Prabhakar
2022-12-12 11:55 ` [PATCH v5 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2022-12-12 11:55 ` [PATCH v5 3/6] riscv: errata: Add Andes alternative ports Prabhakar
2022-12-17 21:19 ` Conor Dooley
2022-12-19 11:19 ` Lad, Prabhakar
2022-12-19 16:20 ` Conor Dooley
2022-12-21 0:31 ` Lad, Prabhakar
2022-12-12 11:55 ` [PATCH v5 4/6] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Prabhakar
2022-12-13 17:14 ` Geert Uytterhoeven
2022-12-13 17:57 ` Lad, Prabhakar
2022-12-17 20:52 ` Conor Dooley [this message]
2022-12-19 11:21 ` Lad, Prabhakar
2022-12-12 11:55 ` [PATCH v5 5/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2022-12-12 17:28 ` Rob Herring
2022-12-12 11:55 ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar
2022-12-15 10:34 ` Geert Uytterhoeven
2022-12-15 11:03 ` Lad, Prabhakar
2022-12-15 11:10 ` Geert Uytterhoeven
2022-12-15 17:46 ` Lad, Prabhakar
2022-12-15 19:54 ` Conor Dooley
2022-12-15 20:17 ` Geert Uytterhoeven
2022-12-15 20:32 ` Conor Dooley
2022-12-15 21:40 ` Palmer Dabbelt
2022-12-16 7:02 ` Christoph Hellwig
2022-12-16 16:32 ` Palmer Dabbelt
2022-12-16 20:04 ` Arnd Bergmann
2022-12-17 22:52 ` Conor Dooley
2022-12-19 12:43 ` Lad, Prabhakar
2022-12-19 16:08 ` Conor Dooley
2022-12-29 14:05 ` Arnd Bergmann
2022-12-29 14:42 ` Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 0/9] Generic function based cache management operations (was Re: [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC) Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 1/9] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 2/9] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 3/9] riscv: errata: Add Andes alternative ports Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 4/9] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 5/9] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 6/9] cache,soc: Move SiFive CCache driver & create drivers/cache Conor Dooley
2023-01-04 9:50 ` Ben Dooks
2023-01-04 10:18 ` Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 7/9] RISC-V: create a function based cache management interface Conor Dooley
2023-01-03 21:04 ` [RFC v5.1 8/9] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley
2023-01-03 21:04 ` [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability Conor Dooley
2023-01-03 21:25 ` Palmer Dabbelt
2023-01-03 21:28 ` Arnd Bergmann
2023-01-04 0:00 ` Conor Dooley
2023-01-04 8:17 ` Arnd Bergmann
2023-01-04 9:23 ` Conor Dooley
2023-01-04 10:19 ` Arnd Bergmann
2023-01-04 11:56 ` Conor Dooley
2023-01-04 12:18 ` Arnd Bergmann
2023-01-04 13:20 ` Conor Dooley
2023-01-04 14:15 ` Arnd Bergmann
2023-01-04 9:45 ` Ben Dooks
2023-01-04 9:57 ` Conor Dooley
2022-12-17 21:35 ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley
2022-12-28 3:16 ` Samuel Holland
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