Re: 5.2-rc1 boot on Unleashed

[Troy Benjegerdes <troy.benjegerdes@sifive.com>]

> On May 25, 2019, at 1:09 PM, Paul Walmsley <paul.walmsley@sifive.com> wrote:
> 
> On Fri, 24 May 2019, Troy Benjegerdes wrote:
> 
>> I have no issues updating the PRCI driver DT format if we also have the 
>> rest of the DT entries needed to boot a working system
> 
> Now is the time to fix the U-boot PRCI issue upstream.  Fixing that should 
> be straightforward, and should be enough to boot the system with initramfs 
> and a serial console.  The missing patch is currently blocking others from 
> using U-boot-based boot flows on Aloe.

I suppose we have different opinions on what’s blocking what. 

If https://github.com/sifive/HiFive_U-Boot is not sufficient for U-boot based
development flows, I’d like to hear what it would need to be useful until I
have a full patch set for upstream U-boot that includes mainline-bound DTS
entries that can replicate the functionality the existing legacy u-boot port
has.

>> I just have not seen an example of that other than what I have at 
>> https://github.com/sifive/HiFive_U-Boot/blob/regression/arch/riscv/dts/hifive_u540.dts
> 
> I sent you a pointer to a branch a few days ago that contains the most 
> recent mainline-bound DTS data.  That should be enough to verify that the 
> basic boot works.  If you want to keep up with the ongoing development of 
> that data, the best bet is to subscribe to the linux-riscv mailing list.
> 
> 
> - Paul

I consider ‘basic boot’ to include a bootloader that can load BBL/SBI and
an payload (S-mode uboot, or a kernel/ramdisk/dtb/etc) via the network.

So this would be the time to agree on what the gemgxl/ethernet entries 
should look like, and all of this can get unblocked. What I have now that
I know works (with the legacy u-boot) is this:

                L51: cadence-gemgxl-mgmt@100a0000 {
                        compatible = "sifive,cadencegemgxlmgmt0";
                        reg = <0x0 0x100a0000 0x0 0x1000>;
                        reg-names = "control";
                        #clock-cells = <0>;
                };
                L52: ethernet@10090000 {
                        compatible = "cdns,macb";
                        interrupt-parent = <&L4>;
                        interrupts = <53>;
                        reg = <0x0 0x10090000 0x0 0x2000>;
                        reg-names = "control";

                        local-mac-address = [00 00 00 00 00 00];
                        phy-mode = "gmii";
                        clock-names = "pclk", "hclk", "tx_clk";
                        clocks = <&prci 1>, <&prci 1>, <&L51>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        phy1: ethernet-phy@0 {
                                reg = <0>;
                                reset-gpios = <&L31 12 1>;
                        };
                };
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