From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: "Heiko Stübner" <heiko@sntech.de>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
christoph.muellner@vrull.eu, conor@kernel.org,
philipp.tomsich@vrull.eu, ajones@ventanamicro.com,
emil.renner.berthing@canonical.com
Subject: Re: [PATCH 5/7] RISC-V: fix auipc-jalr addresses in patched alternatives
Date: Mon, 21 Nov 2022 21:31:36 +0000 [thread overview]
Message-ID: <CA+V-a8sqEjLKdGm67Sm5YbYUVRuntAM0Wqw_Gk+V6i9x+b1Exg@mail.gmail.com> (raw)
In-Reply-To: <CA+V-a8vSVY590SUkg81cC8Kq7FjzxdcJ5m2VG=94m0ntis7+8w@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 22090 bytes --]
Hi Heiko,
On Mon, Nov 21, 2022 at 3:06 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> Hi Heiko,
>
> On Mon, Nov 21, 2022 at 11:27 AM Heiko Stübner <heiko@sntech.de> wrote:
> >
> > Hi,
> >
> > Am Montag, 21. November 2022, 10:50:09 CET schrieb Lad, Prabhakar:
> > > On Thu, Nov 10, 2022 at 4:50 PM Heiko Stuebner <heiko@sntech.de> wrote:
> > > >
> > > > From: Heiko Stuebner <heiko.stuebner@vrull.eu>
> > > >
> > > > Alternatives live in a different section, so addresses used by call
> > > > functions will point to wrong locations after the patch got applied.
> > > >
> > > > Similar to arm64, adjust the location to consider that offset.
> > > >
> > > > Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> > > > ---
> >
> > [...]
> >
> > > I have the below assembly code which I have tested without the
> > > alternatives for the RZ/Five CMO,
> > >
> > > #define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \
> > > asm volatile(".option push\n\t\n\t" \
> > > ".option norvc\n\t" \
> > > ".option norelax\n\t" \
> > > "addi sp,sp,-16\n\t" \
> > > "sd s0,0(sp)\n\t" \
> > > "sd ra,8(sp)\n\t" \
> > > "addi s0,sp,16\n\t" \
> > > "mv a4,%6\n\t" \
> > > "mv a3,%5\n\t" \
> > > "mv a2,%4\n\t" \
> > > "mv a1,%3\n\t" \
> > > "mv a0,%0\n\t" \
> > > "call rzfive_cmo\n\t" \
> > > "ld ra,8(sp)\n\t" \
> > > "ld s0,0(sp)\n\t" \
> > > "addi sp,sp,16\n\t" \
> > > ".option pop\n\t" \
> > > : : "r"(_cachesize), \
> > > "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \
> > > "r"((unsigned long)(_start) + (_size)), \
> > > "r"((unsigned long) (_start)), \
> > > "r"((unsigned long) (_size)), \
> > > "r"((unsigned long) (_dir)), \
> > > "r"((unsigned long) (_ops)) \
> > > : "a0", "a1", "a2", "a3", "a4", "memory")
> > >
> > > Now when integrate this with ALTERNATIVE_2() as below,
> > >
> > > #define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \
> > > asm volatile(ALTERNATIVE_2( \
> > > __nops(14), \
> > > "mv a0, %1\n\t" \
> > > "j 2f\n\t" \
> > > "3:\n\t" \
> > > "cbo." __stringify(_op) " (a0)\n\t" \
> > > "add a0, a0, %0\n\t" \
> > > "2:\n\t" \
> > > "bltu a0, %2, 3b\n\t" \
> > > __nops(8), 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \
> > > ".option push\n\t\n\t" \
> > > ".option norvc\n\t" \
> > > ".option norelax\n\t" \
> > > "addi sp,sp,-16\n\t" \
> > > "sd s0,0(sp)\n\t" \
> > > "sd ra,8(sp)\n\t" \
> > > "addi s0,sp,16\n\t" \
> > > "mv a4,%6\n\t" \
> > > "mv a3,%5\n\t" \
> > > "mv a2,%4\n\t" \
> > > "mv a1,%3\n\t" \
> > > "mv a0,%0\n\t" \
> > > "call rzfive_cmo\n\t" \
> > > "ld ra,8(sp)\n\t" \
> > > "ld s0,0(sp)\n\t" \
> > > "addi sp,sp,16\n\t" \
> > > ".option pop\n\t" \
> > > , ANDESTECH_VENDOR_ID, \
> > > ERRATA_ANDESTECH_NO_IOCP, CONFIG_ERRATA_RZFIVE_CMO) \
> > > : : "r"(_cachesize), \
> > > "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \
> > > "r"((unsigned long)(_start) + (_size)), \
> > > "r"((unsigned long) (_start)), \
> > > "r"((unsigned long) (_size)), \
> > > "r"((unsigned long) (_dir)), \
> > > "r"((unsigned long) (_ops)) \
> > > : "a0", "a1", "a2", "a3", "a4", "memory")
> > >
> > > I am seeing kernel panic with this change. Looking at the
> > > riscv_alternative_fix_auipc_jalr() implementation it assumes the rest
> > > of the alternative options are calls too. Is my understanding correct
> > > here?
> >
> > The loop walks through the instructions after the location got patched and
> > checks if an instruction is an auipc and the next one is a jalr and only then
> > adjusts the address accordingly.
> >
> Ok so my understanding was wrong here.
>
> > So it _should_ leave all other (non auipc+jalr) instructions alone.
> > (hopefully)
> >
> Agreed.
>
> >
> > > Do you think this is the correct approach in my case?
> >
> > It does look correct on first glance.
> >
> \o/
>
> > As I had that passing thought, are you actually calling
> > riscv_alternative_fix_auipc_jalr()
> > from your errata/.../foo.c after doing the patching?
> >
> > I.e. with the current patchset, that function is only called from the
> > cpufeature part, but for example not from the other patching locations.
> > [and a future revision should probably change that :-) ]
> >
> >
> I have made a local copy of riscv_alternative_fix_auipc_jalr() and
> then calling it after patch_text_nosync() referring to your patch for
> str functions.
>
> > After making sure that function actually runs, the next thing you could try
> > is to have both the "original" code and the patch be identical, i.e.
> > replace the cbo* part with your code as well and then just output the
> > instructions via printk to check what the addresses do in both.
> >
> > After riscv_alternative_fix_auipc_jalr() ran then both code variants
> > should be identical when using the same code in both areas.
> >
> So I have added debug prints to match the instructions as below after
> and before patching:
>
> static void riscv_alternative_print_inst(unsigned int *alt_ptr,
> unsigned int len)
> {
> int num_instr = len / sizeof(u32);
> int i;
>
> for (i = 0; i < num_instr; i++)
> pr_err("%s instruction: 0x%x\n", __func__, *(alt_ptr + i));
>
> }
>
> void __init_or_module andes_errata_patch_func(struct alt_entry *begin,
> struct alt_entry *end,
> unsigned long archid, unsigned long impid,
> unsigned int stage)
> {
> ....
> if (cpu_req_errata & tmp) {
> pr_err("stage: %x -> %px--> %x %x %x\n", stage, alt, tmp,
> cpu_req_errata, alt->errata_id);
> pr_err("old:%ps alt:%ps len:%lx\n", alt->old_ptr,
> alt->alt_ptr, alt->alt_len);
> pr_err("Print old start\n");
> riscv_alternative_print_inst(alt->old_ptr, alt->alt_len);
> pr_err("Print old end\n");
> patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len);
>
> riscv_alternative_fix_auipc_jalr(alt->old_ptr, alt->alt_len,
> alt->old_ptr - alt->alt_ptr);
> pr_err("Print patch start\n");
> riscv_alternative_print_inst(alt->alt_ptr, alt->alt_len);
> pr_err("Print patch end\n");
> }
> .....
> }
>
> Below is the log:
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] Print new old end
> [ 0.000000] riscv_alternative_fix_auipc_jalr num instruction: 14
> [ 0.000000] Print patch start
> [ 0.000000] riscv_alternative_print_inst instruction: 0xff010113
> [ 0.000000] riscv_alternative_print_inst instruction: 0x813023
> [ 0.000000] riscv_alternative_print_inst instruction: 0x113423
> [ 0.000000] riscv_alternative_print_inst instruction: 0x1010413
> [ 0.000000] riscv_alternative_print_inst instruction: 0xf0713
> [ 0.000000] riscv_alternative_print_inst instruction: 0x78693
> [ 0.000000] riscv_alternative_print_inst instruction: 0x88613
> [ 0.000000] riscv_alternative_print_inst instruction: 0x80593
> [ 0.000000] riscv_alternative_print_inst instruction: 0xe0513
> [ 0.000000] riscv_alternative_print_inst instruction: 0x97
> [ 0.000000] riscv_alternative_print_inst instruction: 0xcba080e7
> [ 0.000000] riscv_alternative_print_inst instruction: 0x813083
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13403
> [ 0.000000] riscv_alternative_print_inst instruction: 0x1010113
> [ 0.000000] Print patch end
> [ 0.000000] stage: 0 -> ffffffff80a2492c--> 1 1 0
> [ 0.000000] old:arch_sync_dma_for_device
> alt:riscv_noncoherent_supported len:38
> [ 0.000000] Print old start
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x970013
> ====================> This instruction doesn't look correct it
> should be 0x13?
> [ 0.000000] Print old end
> [ 0.000000] riscv_alternative_fix_auipc_jalr num instruction: 14
> [ 0.000000] Print patch start
> [ 0.000000] riscv_alternative_print_inst instruction: 0xff010113
> [ 0.000000] riscv_alternative_print_inst instruction: 0x813023
> [ 0.000000] riscv_alternative_print_inst instruction: 0x113423
> [ 0.000000] riscv_alternative_print_inst instruction: 0x1010413
> [ 0.000000] riscv_alternative_print_inst instruction: 0x78713
> [ 0.000000] riscv_alternative_print_inst instruction: 0x78693
> [ 0.000000] riscv_alternative_print_inst instruction: 0x88613
> [ 0.000000] riscv_alternative_print_inst instruction: 0x80593
> [ 0.000000] riscv_alternative_print_inst instruction: 0xe0513
> [ 0.000000] riscv_alternative_print_inst instruction: 0x97
> [ 0.000000] riscv_alternative_print_inst instruction: 0xc82080e7
> ====================> This instruction doesn't look correct comparing
> to objdump output this should be 000080e7 or does it require the
> offset too?
> [ 0.000000] riscv_alternative_print_inst instruction: 0x813083
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13403
> [ 0.000000] riscv_alternative_print_inst instruction: 0x1010113
> [ 0.000000] Print patch end
> [ 0.000000] stage: 0 -> ffffffff80a24950--> 1 1 0
> [ 0.000000] old:arch_sync_dma_for_cpu alt:riscv_noncoherent_supported len:38
> [ 0.000000] Print old start
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x97
> ====================> This instruction doesn't look correct it should
> be 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0xeee080e7
> ====================> This instruction doesn't look correct it
> should be 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] Print old end
> [ 0.000000] riscv_alternative_fix_auipc_jalr num instruction: 14
> [ 0.000000] Print patch start
> [ 0.000000] riscv_alternative_print_inst instruction: 0xff010113
> [ 0.000000] riscv_alternative_print_inst instruction: 0x813023
> [ 0.000000] riscv_alternative_print_inst instruction: 0x113423
> [ 0.000000] riscv_alternative_print_inst instruction: 0x1010413
> [ 0.000000] riscv_alternative_print_inst instruction: 0xf0713
> [ 0.000000] riscv_alternative_print_inst instruction: 0x80693
> [ 0.000000] riscv_alternative_print_inst instruction: 0x88613
> [ 0.000000] riscv_alternative_print_inst instruction: 0x78593
> [ 0.000000] riscv_alternative_print_inst instruction: 0xe0513
> [ 0.000000] riscv_alternative_print_inst instruction: 0x97
> [ 0.000000] riscv_alternative_print_inst instruction: 0xc4a080e7
> ====================> This instruction doesn't look correct comparing
> to objdump output this should be 000080e7 or does it require the
> offset too?
> [ 0.000000] riscv_alternative_print_inst instruction: 0x813083
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13403
> [ 0.000000] riscv_alternative_print_inst instruction: 0x1010113
> [ 0.000000] Print patch end
> [ 0.000000] stage: 0 -> ffffffff80a24974--> 1 1 0
> [ 0.000000] old:arch_dma_prep_coherent alt:riscv_noncoherent_supported len:38
> [ 0.000000] Print old start
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x970013
> ====================> This instruction doesn't look correct it should
> be 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x80e70000
> ====================> This instruction doesn't look correct it should
> be 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0xe720
> ====================> This instruction doesn't look correct it should
> be 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13
> [ 0.000000] Print old end
> [ 0.000000] riscv_alternative_fix_auipc_jalr num instruction: 14
> [ 0.000000] Print patch start
> [ 0.000000] riscv_alternative_print_inst instruction: 0xff010113
> [ 0.000000] riscv_alternative_print_inst instruction: 0x813023
> [ 0.000000] riscv_alternative_print_inst instruction: 0x113423
> [ 0.000000] riscv_alternative_print_inst instruction: 0x1010413
> [ 0.000000] riscv_alternative_print_inst instruction: 0xf0713
> [ 0.000000] riscv_alternative_print_inst instruction: 0xe8693
> [ 0.000000] riscv_alternative_print_inst instruction: 0x88613
> [ 0.000000] riscv_alternative_print_inst instruction: 0x78593
> [ 0.000000] riscv_alternative_print_inst instruction: 0x30513
> [ 0.000000] riscv_alternative_print_inst instruction: 0x97
> [ 0.000000] riscv_alternative_print_inst instruction: 0xc12080e7
> ====================> This instruction doesn't look correct comparing
> to objdump output this should be 000080e7 + offset?
> [ 0.000000] riscv_alternative_print_inst instruction: 0x813083
> [ 0.000000] riscv_alternative_print_inst instruction: 0x13403
> [ 0.000000] riscv_alternative_print_inst instruction: 0x1010113
> [ 0.000000] Print patch end
>
> Here is the output from objdump of the file (dma-noncoherent.o):
>
> 000000000000032e <.L888^B1>:
> 32e: ff010113 addi sp,sp,-16
> 332: 00813023 sd s0,0(sp)
> 336: 00113423 sd ra,8(sp)
> 33a: 01010413 addi s0,sp,16
> 33e: 000f0713 mv a4,t5
> 342: 00078693 mv a3,a5
> 346: 00088613 mv a2,a7
> 34a: 00080593 mv a1,a6
> 34e: 000e0513 mv a0,t3
> 352: 00000097 auipc ra,0x0
> 356: 000080e7 jalr ra # 352 <.L888^B1+0x24>
> 35a: 00813083 ld ra,8(sp)
> 35e: 00013403 ld s0,0(sp)
> 362: 01010113 addi sp,sp,16
>
> 0000000000000366 <.L888^B2>:
> 366: ff010113 addi sp,sp,-16
> 36a: 00813023 sd s0,0(sp)
> 36e: 00113423 sd ra,8(sp)
> 372: 01010413 addi s0,sp,16
> 376: 00078713 mv a4,a5
> 37a: 00078693 mv a3,a5
> 37e: 00088613 mv a2,a7
> 382: 00080593 mv a1,a6
> 386: 000e0513 mv a0,t3
> 38a: 00000097 auipc ra,0x0
> 38e: 000080e7 jalr ra # 38a <.L888^B2+0x24>
> 392: 00813083 ld ra,8(sp)
> 396: 00013403 ld s0,0(sp)
> 39a: 01010113 addi sp,sp,16
>
> 000000000000039e <.L888^B3>:
> 39e: ff010113 addi sp,sp,-16
> 3a2: 00813023 sd s0,0(sp)
> 3a6: 00113423 sd ra,8(sp)
> 3aa: 01010413 addi s0,sp,16
> 3ae: 000f0713 mv a4,t5
> 3b2: 00080693 mv a3,a6
> 3b6: 00088613 mv a2,a7
> 3ba: 00078593 mv a1,a5
> 3be: 000e0513 mv a0,t3
> 3c2: 00000097 auipc ra,0x0
> 3c6: 000080e7 jalr ra # 3c2 <.L888^B3+0x24>
> 3ca: 00813083 ld ra,8(sp)
> 3ce: 00013403 ld s0,0(sp)
> 3d2: 01010113 addi sp,sp,16
>
> 00000000000003d6 <.L888^B4>:
> 3d6: ff010113 addi sp,sp,-16
> 3da: 00813023 sd s0,0(sp)
> 3de: 00113423 sd ra,8(sp)
> 3e2: 01010413 addi s0,sp,16
> 3e6: 000f0713 mv a4,t5
> 3ea: 000e8693 mv a3,t4
> 3ee: 00088613 mv a2,a7
> 3f2: 00078593 mv a1,a5
> 3f6: 00030513 mv a0,t1
> 3fa: 00000097 auipc ra,0x0
> 3fe: 000080e7 jalr ra # 3fa <.L888^B4+0x24>
> 402: 00813083 ld ra,8(sp)
> 406: 00013403 ld s0,0(sp)
> 40a: 01010113 addi sp,sp,16
>
> Disassembly of section __ksymtab_strings:
>
> Any pointers what could be happening?
>
Some more information,
- If I drop the riscv_alternative_fix_auipc_jalr() call after
patch_text_nosync() and then print the alt->old_ptr instructions
before patching I can see the instructions as 0x13 (nop) which is
correct.
- if I call riscv_alternative_fix_auipc_jalr() call after
patch_text_nosync() and then print the alt->old_ptr instructions
before patching I dont see 0x13 (nop) consistently for old
instructions.
- If I replace the nop's in the old instructions with my assembly code
of rz/five cmo and then just use patch_text_nosync() I can see the
correct actual instruction being printed apart from jalr (is some sort
of offset added to it as I see last 4 bits match?) and then is
replaced correctly by the same alt instructions apart from the jalr
(log [0]).
- If I replace the nop's in the old instructions with my assembly code
of rz/five cmo and then use patch_text_nosync() and
riscv_alternative_fix_auipc_jalr() I can see the actual old
instructions differs a bit and again the jalr instruction differs too
in the patched code (log [1]).
[0] https://paste.debian.net/1261412/
[1] https://paste.debian.net/1261413/
Attached is the objump of dma-noncoherent.o for reference.
Note, if I replace the old/orignal instruction to my asm code for
rz/five cmo and replace the errata id's to deadbeef the code works OK.
Cheers,
Prabhakar
[-- Attachment #2: dma-noncoherent.objdump --]
[-- Type: application/octet-stream, Size: 23236 bytes --]
dma-noncoherent.o: file format elf64-littleriscv
Disassembly of section .text:
0000000000000000 <cache_do_nop>:
0: 1141 c.addi sp,-16
2: e422 c.sdsp s0,8(sp)
4: 0800 c.addi4spn s0,sp,16
6: 6422 c.ldsp s0,8(sp)
8: 0141 c.addi sp,16
a: 8082 c.jr ra
000000000000000c <testcall_via_asm_cache>:
c: 4789 c.li a5,2
e: 04f70463 beq a4,a5,56 <.L12>
12: 1141 c.addi sp,-16
14: e022 c.sdsp s0,0(sp)
16: e406 c.sdsp ra,8(sp)
18: 0800 c.addi4spn s0,sp,16
1a: 852e c.mv a0,a1
1c: c719 c.beqz a4,2a <.L16>
1e: 9af5 c.andi a3,-3
20: ca91 c.beqz a3,34 <.L15>
0000000000000022 <.L6>:
22: 60a2 c.ldsp ra,8(sp)
24: 6402 c.ldsp s0,0(sp)
26: 0141 c.addi sp,16
28: 8082 c.jr ra
000000000000002a <.L16>:
2a: 4705 c.li a4,1
2c: 00d75d63 bge a4,a3,46 <.L17>
30: fef699e3 bne a3,a5,22 <.L6>
0000000000000034 <.L15>:
34: 85b2 c.mv a1,a2
36: 00000097 auipc ra,0x0
3a: 000080e7 jalr ra # 36 <.L15+0x2>
3e: 60a2 c.ldsp ra,8(sp)
40: 6402 c.ldsp s0,0(sp)
42: 0141 c.addi sp,16
44: 8082 c.jr ra
0000000000000046 <.L17>:
46: fc06cee3 bltz a3,22 <.L6>
4a: 85b2 c.mv a1,a2
4c: 00000097 auipc ra,0x0
50: 000080e7 jalr ra # 4c <.L17+0x6>
54: b7f9 c.j 22 <.L6>
0000000000000056 <.L12>:
56: 8082 c.jr ra
0000000000000058 <arch_sync_dma_for_device>:
58: 1141 c.addi sp,-16
5a: e422 c.sdsp s0,8(sp)
5c: 0800 c.addi4spn s0,sp,16
5e: 00000817 auipc a6,0x0
62: 00083803 ld a6,0(a6) # 5e <arch_sync_dma_for_device+0x6>
66: 87b2 c.mv a5,a2
68: 88ae c.mv a7,a1
6a: 982a c.add a6,a0
6c: c63d c.beqz a2,da <.L19>
6e: fff6071b addiw a4,a2,-1
72: 4685 c.li a3,1
74: 06e6e063 bltu a3,a4,d4 <.L18>
78: 00000e17 auipc t3,0x0
7c: 000e2e03 lw t3,0(t3) # 78 <arch_sync_dma_for_device+0x20>
80: 020e1313 slli t1,t3,0x20
84: 02035313 srli t1,t1,0x20
88: 02061793 slli a5,a2,0x20
8c: 40600333 neg t1,t1
90: 01037333 and t1,t1,a6
94: 01058eb3 add t4,a1,a6
98: 9381 c.srli a5,0x20
9a: 4f01 c.li t5,0
000000000000009c <.L886^B1>:
9c: ff010113 addi sp,sp,-16
a0: 00813023 sd s0,0(sp)
a4: 00113423 sd ra,8(sp)
a8: 01010413 addi s0,sp,16
ac: 000f0713 mv a4,t5
b0: 00078693 mv a3,a5
b4: 00088613 mv a2,a7
b8: 00080593 mv a1,a6
bc: 000e0513 mv a0,t3
c0: 00000097 auipc ra,0x0
c4: 000080e7 jalr ra # c0 <.L886^B1+0x24>
c8: 00813083 ld ra,8(sp)
cc: 00013403 ld s0,0(sp)
d0: 01010113 addi sp,sp,16
00000000000000d4 <.L18>:
d4: 6422 c.ldsp s0,8(sp)
d6: 0141 c.addi sp,16
d8: 8082 c.jr ra
00000000000000da <.L19>:
da: 00000e17 auipc t3,0x0
de: 000e2e03 lw t3,0(t3) # da <.L19>
e2: 020e1313 slli t1,t3,0x20
e6: 02035313 srli t1,t1,0x20
ea: 40600333 neg t1,t1
ee: 01037333 and t1,t1,a6
f2: 01058eb3 add t4,a1,a6
00000000000000f6 <.L886^B2>:
f6: ff010113 addi sp,sp,-16
fa: 00813023 sd s0,0(sp)
fe: 00113423 sd ra,8(sp)
102: 01010413 addi s0,sp,16
106: 00078713 mv a4,a5
10a: 00078693 mv a3,a5
10e: 00088613 mv a2,a7
112: 00080593 mv a1,a6
116: 000e0513 mv a0,t3
11a: 00000097 auipc ra,0x0
11e: 000080e7 jalr ra # 11a <.L886^B2+0x24>
122: 00813083 ld ra,8(sp)
126: 00013403 ld s0,0(sp)
12a: 01010113 addi sp,sp,16
12e: 6422 c.ldsp s0,8(sp)
130: 0141 c.addi sp,16
132: 8082 c.jr ra
0000000000000134 <arch_sync_dma_for_cpu>:
134: 1141 c.addi sp,-16
136: e422 c.sdsp s0,8(sp)
138: 0800 c.addi4spn s0,sp,16
13a: ffd67793 andi a5,a2,-3
13e: e7b5 c.bnez a5,1aa <.L22>
140: 00000e17 auipc t3,0x0
144: 000e2e03 lw t3,0(t3) # 140 <arch_sync_dma_for_cpu+0xc>
148: 020e1313 slli t1,t3,0x20
14c: 00000797 auipc a5,0x0
150: 0007b783 ld a5,0(a5) # 14c <arch_sync_dma_for_cpu+0x18>
154: 02035313 srli t1,t1,0x20
158: 97aa c.add a5,a0
15a: 02061813 slli a6,a2,0x20
15e: 40600333 neg t1,t1
162: 88ae c.mv a7,a1
164: 00f37333 and t1,t1,a5
168: 00f58eb3 add t4,a1,a5
16c: 02085813 srli a6,a6,0x20
170: 4f05 c.li t5,1
0000000000000172 <.L886^B3>:
172: ff010113 addi sp,sp,-16
176: 00813023 sd s0,0(sp)
17a: 00113423 sd ra,8(sp)
17e: 01010413 addi s0,sp,16
182: 000f0713 mv a4,t5
186: 00080693 mv a3,a6
18a: 00088613 mv a2,a7
18e: 00078593 mv a1,a5
192: 000e0513 mv a0,t3
196: 00000097 auipc ra,0x0
19a: 000080e7 jalr ra # 196 <.L886^B3+0x24>
19e: 00813083 ld ra,8(sp)
1a2: 00013403 ld s0,0(sp)
1a6: 01010113 addi sp,sp,16
00000000000001aa <.L22>:
1aa: 6422 c.ldsp s0,8(sp)
1ac: 0141 c.addi sp,16
1ae: 8082 c.jr ra
00000000000001b0 <arch_dma_prep_coherent>:
1b0: 1141 c.addi sp,-16
1b2: e422 c.sdsp s0,8(sp)
1b4: 0800 c.addi4spn s0,sp,16
1b6: 00000797 auipc a5,0x0
1ba: 0007b783 ld a5,0(a5) # 1b6 <arch_dma_prep_coherent+0x6>
1be: 40f507b3 sub a5,a0,a5
1c2: 00000317 auipc t1,0x0
1c6: 00032303 lw t1,0(t1) # 1c2 <arch_dma_prep_coherent+0x12>
1ca: 00000517 auipc a0,0x0
1ce: 00053503 ld a0,0(a0) # 1ca <arch_dma_prep_coherent+0x1a>
1d2: 8799 c.srai a5,0x6
1d4: 97aa c.add a5,a0
1d6: 02031813 slli a6,t1,0x20
1da: 00000717 auipc a4,0x0
1de: 00073703 ld a4,0(a4) # 1da <arch_dma_prep_coherent+0x2a>
1e2: 07b2 c.slli a5,0xc
1e4: 02085813 srli a6,a6,0x20
1e8: 97ba c.add a5,a4
1ea: 41000833 neg a6,a6
1ee: 88ae c.mv a7,a1
1f0: 00f87833 and a6,a6,a5
1f4: 00f58e33 add t3,a1,a5
1f8: 4e81 c.li t4,0
1fa: 4f09 c.li t5,2
00000000000001fc <.L886^B4>:
1fc: ff010113 addi sp,sp,-16
200: 00813023 sd s0,0(sp)
204: 00113423 sd ra,8(sp)
208: 01010413 addi s0,sp,16
20c: 000f0713 mv a4,t5
210: 000e8693 mv a3,t4
214: 00088613 mv a2,a7
218: 00078593 mv a1,a5
21c: 00030513 mv a0,t1
220: 00000097 auipc ra,0x0
224: 000080e7 jalr ra # 220 <.L886^B4+0x24>
228: 00813083 ld ra,8(sp)
22c: 00013403 ld s0,0(sp)
230: 01010113 addi sp,sp,16
234: 6422 c.ldsp s0,8(sp)
236: 0141 c.addi sp,16
238: 8082 c.jr ra
000000000000023a <arch_setup_dma_ops>:
23a: 7179 c.addi16sp sp,-48
23c: f022 c.sdsp s0,32(sp)
23e: ec26 c.sdsp s1,24(sp)
240: e84a c.sdsp s2,16(sp)
242: f406 c.sdsp ra,40(sp)
244: e44e c.sdsp s3,8(sp)
246: 1800 c.addi4spn s0,sp,48
248: 84ba c.mv s1,a4
24a: 892a c.mv s2,a0
24c: e331 c.bnez a4,290 <.L29>
24e: 00000997 auipc s3,0x0
252: 00098993 mv s3,s3
256: 0009a703 lw a4,0(s3) # 24e <arch_setup_dma_ops+0x14>
25a: 04000793 li a5,64
25e: 04e7e963 bltu a5,a4,2b0 <.L35>
0000000000000262 <.L30>:
262: 00000797 auipc a5,0x0
266: 0007c783 lbu a5,0(a5) # 262 <.L30>
26a: e39d c.bnez a5,290 <.L29>
26c: 854a c.mv a0,s2
26e: 00000097 auipc ra,0x0
272: 000080e7 jalr ra # 26e <.L30+0xc>
276: 05093603 ld a2,80(s2)
27a: c22d c.beqz a2,2dc <.L36>
000000000000027c <.L33>:
27c: 85aa c.mv a1,a0
27e: 00000517 auipc a0,0x0
282: 00050513 mv a0,a0
286: 00000097 auipc ra,0x0
28a: 000080e7 jalr ra # 286 <.L33+0xa>
000000000000028e <.L1^B1>:
28e: 9002 c.ebreak
0000000000000290 <.L29>:
290: 2ec94783 lbu a5,748(s2)
294: 8885 c.andi s1,1
296: 0496 c.slli s1,0x5
298: fdf7f793 andi a5,a5,-33
29c: 8cdd c.or s1,a5
29e: 2e990623 sb s1,748(s2)
2a2: 70a2 c.ldsp ra,40(sp)
2a4: 7402 c.ldsp s0,32(sp)
2a6: 64e2 c.ldsp s1,24(sp)
2a8: 6942 c.ldsp s2,16(sp)
2aa: 69a2 c.ldsp s3,8(sp)
2ac: 6145 c.addi16sp sp,48
2ae: 8082 c.jr ra
00000000000002b0 <.L35>:
2b0: 00000097 auipc ra,0x0
2b4: 000080e7 jalr ra # 2b0 <.L35>
2b8: 05093603 ld a2,80(s2)
2bc: c21d c.beqz a2,2e2 <.L37>
00000000000002be <.L31>:
2be: 0009a703 lw a4,0(s3)
2c2: 85aa c.mv a1,a0
2c4: 04000693 li a3,64
2c8: 00000517 auipc a0,0x0
2cc: 00050513 mv a0,a0
2d0: 00000097 auipc ra,0x0
2d4: 000080e7 jalr ra # 2d0 <.L31+0x12>
00000000000002d8 <.L1^B2>:
2d8: 9002 c.ebreak
2da: b761 c.j 262 <.L30>
00000000000002dc <.L36>:
2dc: 00093603 ld a2,0(s2)
2e0: bf71 c.j 27c <.L33>
00000000000002e2 <.L37>:
2e2: 00093603 ld a2,0(s2)
2e6: bfe1 c.j 2be <.L31>
00000000000002e8 <riscv_noncoherent_supported>:
2e8: 00000797 auipc a5,0x0
2ec: 0007a783 lw a5,0(a5) # 2e8 <riscv_noncoherent_supported>
2f0: c799 c.beqz a5,2fe <.L44>
2f2: 4785 c.li a5,1
2f4: 00000717 auipc a4,0x0
2f8: 00f70023 sb a5,0(a4) # 2f4 <riscv_noncoherent_supported+0xc>
2fc: 8082 c.jr ra
00000000000002fe <.L44>:
2fe: 1141 c.addi sp,-16
300: e406 c.sdsp ra,8(sp)
302: e022 c.sdsp s0,0(sp)
304: 0800 c.addi4spn s0,sp,16
306: 00000517 auipc a0,0x0
30a: 00050513 mv a0,a0
30e: 00000097 auipc ra,0x0
312: 000080e7 jalr ra # 30e <.L44+0x10>
0000000000000316 <.L1^B3>:
316: 9002 c.ebreak
318: 60a2 c.ldsp ra,8(sp)
31a: 6402 c.ldsp s0,0(sp)
31c: 4785 c.li a5,1
31e: 00000717 auipc a4,0x0
322: 00f70023 sb a5,0(a4) # 31e <.L1^B3+0x8>
326: 0141 c.addi sp,16
328: 8082 c.jr ra
000000000000032a <.L888^B1>:
32a: ff010113 addi sp,sp,-16
32e: 00813023 sd s0,0(sp)
332: 00113423 sd ra,8(sp)
336: 01010413 addi s0,sp,16
33a: 000f0713 mv a4,t5
33e: 00078693 mv a3,a5
342: 00088613 mv a2,a7
346: 00080593 mv a1,a6
34a: 000e0513 mv a0,t3
34e: 00000097 auipc ra,0x0
352: 000080e7 jalr ra # 34e <.L888^B1+0x24>
356: 00813083 ld ra,8(sp)
35a: 00013403 ld s0,0(sp)
35e: 01010113 addi sp,sp,16
0000000000000362 <.L888^B2>:
362: ff010113 addi sp,sp,-16
366: 00813023 sd s0,0(sp)
36a: 00113423 sd ra,8(sp)
36e: 01010413 addi s0,sp,16
372: 00078713 mv a4,a5
376: 00078693 mv a3,a5
37a: 00088613 mv a2,a7
37e: 00080593 mv a1,a6
382: 000e0513 mv a0,t3
386: 00000097 auipc ra,0x0
38a: 000080e7 jalr ra # 386 <.L888^B2+0x24>
38e: 00813083 ld ra,8(sp)
392: 00013403 ld s0,0(sp)
396: 01010113 addi sp,sp,16
000000000000039a <.L888^B3>:
39a: ff010113 addi sp,sp,-16
39e: 00813023 sd s0,0(sp)
3a2: 00113423 sd ra,8(sp)
3a6: 01010413 addi s0,sp,16
3aa: 000f0713 mv a4,t5
3ae: 00080693 mv a3,a6
3b2: 00088613 mv a2,a7
3b6: 00078593 mv a1,a5
3ba: 000e0513 mv a0,t3
3be: 00000097 auipc ra,0x0
3c2: 000080e7 jalr ra # 3be <.L888^B3+0x24>
3c6: 00813083 ld ra,8(sp)
3ca: 00013403 ld s0,0(sp)
3ce: 01010113 addi sp,sp,16
00000000000003d2 <.L888^B4>:
3d2: ff010113 addi sp,sp,-16
3d6: 00813023 sd s0,0(sp)
3da: 00113423 sd ra,8(sp)
3de: 01010413 addi s0,sp,16
3e2: 000f0713 mv a4,t5
3e6: 000e8693 mv a3,t4
3ea: 00088613 mv a2,a7
3ee: 00078593 mv a1,a5
3f2: 00030513 mv a0,t1
3f6: 00000097 auipc ra,0x0
3fa: 000080e7 jalr ra # 3f6 <.L888^B4+0x24>
3fe: 00813083 ld ra,8(sp)
402: 00013403 ld s0,0(sp)
406: 01010113 addi sp,sp,16
Disassembly of section __ksymtab_strings:
0000000000000000 <__kstrtab_testcall_via_asm_cache>:
0: 6574 c.ld a3,200(a0)
2: 61637473 csrrci s0,0x616,6
6: 6c6c c.ld a1,216(s0)
8: 765f 6169 615f 0x615f6169765f
e: 635f6d73 csrrsi s10,0x635,30
12: 6361 c.lui t1,0x18
14: 6568 c.ld a0,200(a0)
...
0000000000000017 <__kstrtabns_testcall_via_asm_cache>:
...
0000000000000018 <__kstrtab_cache_do_nop>:
18: 68636163 bltu t1,t1,69a <.L889^B4+0x290>
1c: 5f65 c.li t5,-7
1e: 6f64 c.ld s1,216(a4)
20: 6e5f 706f 0x706f6e5f
0000000000000025 <__kstrtabns_cache_do_nop>:
...
0000000000000026 <__kstrtab_cache_do_zicbom>:
26: 68636163 bltu t1,t1,6a8 <.L889^B4+0x29e>
2a: 5f65 c.li t5,-7
2c: 6f64 c.ld s1,216(a4)
2e: 7a5f 6369 6f62 0x6f6263697a5f
34: 006d c.nop 27
0000000000000036 <__kstrtabns_cache_do_zicbom>:
...
Disassembly of section .rodata.str1.8:
0000000000000000 <.LC0>:
0: 3301 c.addiw t1,-32
2: 7325 c.lui t1,0xfffe9
4: 6320 c.ld s0,64(a4)
6: 7361 c.lui t1,0xffff8
8: 253d c.addiw a0,15
a: 2075 c.jal b6 <.LC3+0x2e>
c: 6176 c.ldsp sp,344(sp)
e: 6464 c.ld s1,200(s0)
10: 3d72 c.fldsp fs10,312(sp)
12: 7025 c.lui zero,0xfffe9
14: 7320 c.ld s0,96(a4)
16: 7a69 c.lui s4,0xffffa
18: 3a65 c.addiw s4,-7
1a: 6c25 c.lui s8,0x9
1c: 0a78 c.addi4spn a4,sp,284
...
0000000000000020 <.LC1>:
20: 7325 c.lui t1,0xfffe9
22: 2520 c.fld fs0,72(a0)
24: 41203a73 csrrc s4,0x412,zero
28: 4352 c.lwsp t1,20(sp)
2a: 5f48 c.lw a0,60(a4)
2c: 4d44 c.lw s1,28(a0)
2e: 5f41 c.li t5,-16
30: 494d c.li s2,19
32: 414e c.lwsp sp,208(sp)
34: 494c c.lw a1,20(a0)
36: 73204e47 fmsub.d ft8,ft0,fs2,fa4,rmm
3a: 616d c.addi16sp sp,240
3c: 6c6c c.ld a1,216(s0)
3e: 7265 c.lui tp,0xffff9
40: 7420 c.ld s0,104(s0)
42: 6168 c.ld a0,192(a0)
44: 206e c.fldsp ft0,216(sp)
46: 6972 c.ldsp s2,280(sp)
48: 2c766373 csrrsi t1,0x2c7,12
4c: 6d6f6263 bltu t5,s6,710 <.L889^B4+0x306>
50: 622d c.lui tp,0xb
52: 6f6c c.ld a1,216(a4)
54: 732d6b63 bltu s10,s2,78a <.L889^B4+0x380>
58: 7a69 c.lui s4,0xffffa
5a: 2065 c.jal 102 <.LC4+0x32>
5c: 2528 c.fld fa0,72(a0)
5e: 2064 c.fld fs1,192(s0)
60: 203c c.fld fa5,64(s0)
62: 6425 c.lui s0,0x9
64: 0029 c.nop 10
...
0000000000000068 <.LC2>:
68: 7261 c.lui tp,0xffff8
6a: 722f6863 bltu t5,sp,79a <.L889^B4+0x390>
6e: 7369 c.lui t1,0xffffa
70: 6d2f7663 bgeu t5,s2,73c <.L889^B4+0x332>
74: 2f6d c.addiw t5,27
76: 6d64 c.ld s1,216(a0)
78: 2d61 c.addiw s10,24
7a: 6f6e c.ldsp t5,216(sp)
7c: 636e c.ldsp t1,216(sp)
7e: 7265686f jal a6,567a4 <.L889^B4+0x5639a>
82: 6e65 c.lui t3,0x19
84: 2e74 c.fld fa3,216(a2)
86: beq a0,s2,7a6 <.L889^B4+0x39c>
0000000000000088 <.LC3>:
88: 7325 c.lui t1,0xfffe9
8a: 2520 c.fld fs0,72(a0)
8c: 64203a73 csrrc s4,0x642,zero
90: 7665 c.lui a2,0xffff9
92: 6369 c.lui t1,0x1a
94: 2065 c.jal 13c <arch_sync_dma_for_cpu+0x8>
96: 6f6e c.ldsp t5,216(sp)
98: 2d6e c.fldsp fs10,216(sp)
9a: 65686f63 bltu a6,s6,6f8 <.L889^B4+0x2ee>
9e: 6572 c.ldsp a0,280(sp)
a0: 746e c.ldsp s0,248(sp)
a2: 6220 c.ld s0,64(a2)
a4: 7475 c.lui s0,0xffffd
a6: 6e20 c.ld s0,88(a2)
a8: 6f6e206f j e279e <.L889^B4+0xe2394>
ac: 2d6e c.fldsp fs10,216(sp)
ae: 65686f63 bltu a6,s6,70c <.L889^B4+0x302>
b2: 6572 c.ldsp a0,280(sp)
b4: 746e c.ldsp s0,248(sp)
b6: 6f20 c.ld s0,88(a4)
b8: 6570 c.ld a2,200(a0)
ba: 6172 c.ldsp sp,280(sp)
bc: 6974 c.ld a3,208(a0)
be: 20736e6f jal t3,36ac4 <.L889^B4+0x366ba>
c2: 70707573 csrrci a0,0x707,0
c6: 6574726f jal tp,47f1c <.L889^B4+0x47b12>
ca: 0064 c.addi4spn s1,sp,12
cc: 0000 unimp
...
00000000000000d0 <.LC4>:
d0: 6f4e c.ldsp t5,208(sp)
d2: 2d6e c.fldsp fs10,216(sp)
d4: 65686f63 bltu a6,s6,732 <.L889^B4+0x328>
d8: 6572 c.ldsp a0,280(sp)
da: 746e c.ldsp s0,248(sp)
dc: 4420 c.lw s0,72(s0)
de: 414d c.li sp,19
e0: 7320 c.ld s0,96(a4)
e2: 7075 c.lui zero,0xffffd
e4: 6f70 c.ld a2,216(a4)
e6: 7472 c.ldsp s0,312(sp)
e8: 6520 c.ld s0,72(a0)
ea: 616e c.ldsp sp,216(sp)
ec: 6c62 c.ldsp s8,24(sp)
ee: 6465 c.lui s0,0x19
f0: 7720 c.ld s0,104(a4)
f2: 7469 c.lui s0,0xffffa
f4: 6f68 c.ld a0,216(a4)
f6: 7475 c.lui s0,0xffffd
f8: 6120 c.ld s0,64(a0)
fa: 6220 c.ld s0,64(a2)
fc: 6f6c c.ld a1,216(a4)
fe: 73206b63 bltu zero,s2,834 <.L889^B4+0x42a>
102: 7a69 c.lui s4,0xffffa
104: 0a65 c.addi s4,25
...
Disassembly of section .text.unlikely:
0000000000000000 <cache_do_zicbom>:
0: 1141 c.addi sp,-16
2: e022 c.sdsp s0,0(sp)
4: e406 c.sdsp ra,8(sp)
6: 0800 c.addi4spn s0,sp,16
8: 86ae c.mv a3,a1
a: 8732 c.mv a4,a2
c: 00000597 auipc a1,0x0
10: 00058593 mv a1,a1
14: 862a c.mv a2,a0
16: 00000517 auipc a0,0x0
1a: 00050513 mv a0,a0
1e: 00000097 auipc ra,0x0
22: 000080e7 jalr ra # 1e <cache_do_zicbom+0x1e>
26: 60a2 c.ldsp ra,8(sp)
28: 6402 c.ldsp s0,0(sp)
2a: 0141 c.addi sp,16
2c: 8082 c.jr ra
Disassembly of section .alternative:
0000000000000000 <.alternative>:
...
10: 031e c.slli t1,0x7
...
32: 0000 unimp
34: 031e c.slli t1,0x7
...
56: 0000 unimp
58: 031e c.slli t1,0x7
...
7a: 0000 unimp
7c: 031e c.slli t1,0x7
...
Disassembly of section __bug_table:
0000000000000000 <__bug_table>:
...
8: 00d9 c.addi ra,22
a: 0209 c.addi tp,2
...
14: 020900d3 fadd.d ft1,fs2,ft0,rne
...
20: 00e2 c.slli ra,0x18
22: 0909 c.addi s2,2
Disassembly of section .rodata:
0000000000000000 <__func__.36886>:
0: 68636163 bltu t1,t1,682 <.L889^B4+0x278>
4: 5f65 c.li t5,-7
6: 6f64 c.ld s1,216(a4)
8: 7a5f 6369 6f62 0x6f6263697a5f
e: 006d c.nop 27
Disassembly of section .sbss:
0000000000000000 <noncoherent_supported>:
...
Disassembly of section ___ksymtab+cache_do_nop:
0000000000000000 <__ksymtab_cache_do_nop>:
...
Disassembly of section ___ksymtab+cache_do_zicbom:
0000000000000000 <__ksymtab_cache_do_zicbom>:
...
Disassembly of section ___ksymtab+testcall_via_asm_cache:
0000000000000000 <__ksymtab_testcall_via_asm_cache>:
...
Disassembly of section .comment:
0000000000000000 <.comment>:
0: 4700 c.lw s0,8(a4)
2: 203a4343 fmadd.s ft6,fs4,ft3,ft4,rmm
6: 5528 c.lw a0,104(a0)
8: 7562 c.ldsp a0,56(sp)
a: 746e c.ldsp s0,248(sp)
c: 2075 c.jal b8 <.L886^B1+0x1c>
e: 2e39 c.addiw t3,14
10: 2e34 c.fld fa3,88(a2)
12: 2d30 c.fld fa2,88(a0)
14: 7531 c.lui a0,0xfffec
16: 7562 c.ldsp a0,56(sp)
18: 746e c.ldsp s0,248(sp)
1a: 3175 c.addiw sp,-3
1c: 327e c.fldsp ft4,504(sp)
1e: 2e30 c.fld fa2,88(a2)
20: 3430 c.fld fa2,104(s0)
22: 2029 c.jal 2c <.L16+0x2>
24: 2e39 c.addiw t3,14
26: 2e34 c.fld fa3,88(a2)
28: 0030 c.addi4spn a2,sp,8
[-- Attachment #3: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-11-21 21:32 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-10 16:49 [PATCH 0/7] Zbb string optimizations and call support in alternatives Heiko Stuebner
2022-11-10 16:49 ` [PATCH 1/7] efi/riscv: libstub: mark when compiling libstub Heiko Stuebner
2022-11-13 17:16 ` Conor Dooley
2022-11-13 17:20 ` Heiko Stübner
2022-11-13 18:06 ` Conor Dooley
2022-11-10 16:49 ` [PATCH 2/7] RISC-V: add auipc elements to parse_asm header Heiko Stuebner
2022-11-13 17:18 ` Conor Dooley
2022-11-10 16:49 ` [PATCH 3/7] RISC-V: add U-type imm parsing " Heiko Stuebner
2022-11-13 19:06 ` Conor Dooley
2022-11-10 16:49 ` [PATCH 4/7] RISC-V: add rd reg " Heiko Stuebner
2022-11-13 19:08 ` Conor Dooley
2022-11-10 16:49 ` [PATCH 5/7] RISC-V: fix auipc-jalr addresses in patched alternatives Heiko Stuebner
2022-11-13 20:31 ` Conor Dooley
2022-11-14 10:57 ` Emil Renner Berthing
2022-11-14 11:35 ` Andrew Jones
2022-11-14 11:38 ` Emil Renner Berthing
2022-11-14 11:38 ` Heiko Stübner
2022-11-14 12:15 ` Andrew Jones
2022-11-14 12:29 ` Emil Renner Berthing
2022-11-14 12:47 ` Philipp Tomsich
2022-11-15 14:28 ` Lad, Prabhakar
2022-11-17 11:51 ` Heiko Stübner
2022-11-21 9:50 ` Lad, Prabhakar
2022-11-21 11:27 ` Heiko Stübner
2022-11-21 15:06 ` Lad, Prabhakar
2022-11-21 21:31 ` Lad, Prabhakar [this message]
2022-11-21 22:17 ` Heiko Stübner
2022-11-21 22:38 ` Heiko Stübner
2022-11-22 0:16 ` Lad, Prabhakar
2022-11-21 23:59 ` Lad, Prabhakar
2022-11-22 10:59 ` Lad, Prabhakar
2022-11-22 11:19 ` Heiko Stübner
2022-11-22 11:37 ` Heiko Stübner
2022-11-22 12:28 ` Lad, Prabhakar
2022-11-10 16:49 ` [PATCH 6/7] RISC-V: add infrastructure to allow different str* implementations Heiko Stuebner
2022-11-13 22:07 ` Conor Dooley
2022-11-10 16:49 ` [PATCH 7/7] RISC-V: add zbb support to string functions Heiko Stuebner
2022-11-13 23:29 ` Conor Dooley
2022-11-13 23:47 ` Heiko Stübner
2022-11-24 22:23 ` Heiko Stübner
2022-11-24 22:32 ` Conor Dooley
2022-11-24 23:51 ` Heiko Stuebner
2022-11-25 7:49 ` Andrew Jones
2022-11-25 8:17 ` Conor.Dooley
[not found] ` <CAEg0e7h9skbWPVDsz9CdB8dATN5XM9eT-uPY0A7xRZmX=qTU6A@mail.gmail.com>
2022-11-25 15:28 ` Andrew Jones
2022-11-25 16:35 ` Christoph Müllner
2022-11-25 16:39 ` Conor Dooley
2022-11-25 17:02 ` Christoph Müllner
2022-11-25 17:11 ` Conor Dooley
2022-11-25 17:42 ` Christoph Müllner
2022-11-25 16:36 ` Conor Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CA+V-a8sqEjLKdGm67Sm5YbYUVRuntAM0Wqw_Gk+V6i9x+b1Exg@mail.gmail.com \
--to=prabhakar.csengg@gmail.com \
--cc=ajones@ventanamicro.com \
--cc=christoph.muellner@vrull.eu \
--cc=conor@kernel.org \
--cc=emil.renner.berthing@canonical.com \
--cc=heiko@sntech.de \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=philipp.tomsich@vrull.eu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).