From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
LKML <linux-kernel@vger.kernel.org>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
Date: Fri, 12 Aug 2022 00:37:42 +0100 [thread overview]
Message-ID: <CA+V-a8tkRJrugewfAunO7CP9H7A8H5OM2=uRQtDfk7=15Zkw4A@mail.gmail.com> (raw)
In-Reply-To: <CAMuHMdWih6XiVfLT0g=k8QrMmVzb2sqv9hxqtGE1t1F1Jvj_QA@mail.gmail.com>
Hi Geert,
On Thu, Aug 11, 2022 at 4:26 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, Jul 27, 2022 at 11:48 AM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Wed, Jul 27, 2022 at 10:31 AM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> > > On 27/07/2022 11:00, Lad, Prabhakar wrote:
> > > > On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
> > > > <krzysztof.kozlowski@linaro.org> wrote:
> > > >> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > > >>> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> > > >>> (RISC-V arch).
> > > >>>
> > > >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >>> ---
> > > >>> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> > > >>> 1 file changed, 9 insertions(+)
> > > >>>
> > > >>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > >>> index ff80152f092f..f646df1a23af 100644
> > > >>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > > >>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > >>> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> > > >>> maintainers:
> > > >>> - Geert Uytterhoeven <geert+renesas@glider.be>
> > > >>>
> > > >>> +# We want to ignore this schema if the board is of RISC-V arch
> > > >>> +select:
> > > >>> + not:
> > > >>> + properties:
> > > >>> + compatible:
> > > >>> + contains:
> > > >>> + items:
> > > >>> + - const: renesas,r9a07g043f01
> > > >>
> > > >> Second issue - why not renesas,r9a07g043?
> > > >>
> > > > We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.
> > > >
> > > > RZ/G2UL ARM64:
> > > > Type-1 Part Number: R9A07G043U11GBG#BC0
> > > > Type-2 Part Number: R9A07G043U12GBG#BC0
> > > >
> > > > RZ/Five RISCV:
> > > > 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
> > > >
> > > > So to differentiate in ARM schema I am using renesas,r9a07g043f01.
> > >
> > > What is the point to keep then r9a07g043 fallback? The two SoCs are not
> > > compatible at all, so they must not use the same fallback.
> > >
> > Agreed, I wanted to keep it consistent with what was done with ARM64
> > (since both the SoCs shared R9A07G043 part number).
> >
> > Geert - What are your thoughts on the above?
>
> "renesas,r9a07g043" is the CPU-less SoC base containing I/O devices.
> "renesas,r9a07g043f01", "renesas,r9a07g043u11", and
> "renesas,r9a07g043u12" are SoCs built by integrating one or more
> RV64 or ARM64 CPU cores and the related interrupt controllers with
> the CPU-less SoC base.
>
That's bang on! which I missed to convenience the DT maintainers.
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-08-11 23:38 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-26 18:06 [PATCH 0/6] Add support for Renesas RZ/Five SoC Lad Prabhakar
2022-07-26 18:06 ` [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch Lad Prabhakar
2022-07-27 8:50 ` Krzysztof Kozlowski
2022-07-27 8:55 ` Lad, Prabhakar
2022-07-27 8:53 ` Krzysztof Kozlowski
2022-07-27 9:00 ` Lad, Prabhakar
2022-07-27 9:31 ` Krzysztof Kozlowski
2022-07-27 9:48 ` Lad, Prabhakar
2022-08-11 15:26 ` Geert Uytterhoeven
2022-08-11 23:37 ` Lad, Prabhakar [this message]
2022-07-27 15:43 ` Rob Herring
2022-07-26 18:06 ` [PATCH 2/6] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
2022-07-27 8:51 ` Krzysztof Kozlowski
2022-07-26 18:06 ` [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
2022-07-27 8:51 ` Krzysztof Kozlowski
2022-07-26 18:06 ` [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK Lad Prabhakar
2022-07-27 8:54 ` Krzysztof Kozlowski
2022-07-27 9:05 ` Lad, Prabhakar
2022-07-27 9:27 ` Biju Das
2022-07-27 9:35 ` Lad, Prabhakar
2022-07-27 9:54 ` Krzysztof Kozlowski
2022-07-27 10:06 ` Lad, Prabhakar
2022-07-27 10:09 ` Krzysztof Kozlowski
2022-07-27 11:37 ` Lad, Prabhakar
2022-07-27 11:44 ` Krzysztof Kozlowski
2022-07-27 12:21 ` Biju Das
2022-07-27 12:36 ` Krzysztof Kozlowski
2022-07-27 12:56 ` Biju Das
2022-07-27 13:00 ` Krzysztof Kozlowski
2022-07-27 13:29 ` Conor.Dooley
2022-07-27 15:32 ` Lad, Prabhakar
2022-08-11 15:42 ` Geert Uytterhoeven
2022-08-12 6:23 ` Krzysztof Kozlowski
2022-08-12 9:49 ` Lad, Prabhakar
2022-08-12 15:10 ` Palmer Dabbelt
2022-07-26 18:06 ` [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar
2022-07-26 18:49 ` Conor.Dooley
2022-07-27 8:19 ` Lad, Prabhakar
2022-07-26 18:06 ` [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
2022-07-26 18:25 ` Conor.Dooley
2022-07-26 18:53 ` Conor.Dooley
2022-07-27 8:09 ` Lad, Prabhakar
2022-07-27 8:21 ` Conor.Dooley
2022-07-27 8:30 ` Lad, Prabhakar
2022-07-27 8:55 ` Krzysztof Kozlowski
2022-07-27 9:08 ` Lad, Prabhakar
2022-07-26 18:51 ` [PATCH 0/6] Add support " Conor.Dooley
2022-07-27 8:00 ` Lad, Prabhakar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CA+V-a8tkRJrugewfAunO7CP9H7A8H5OM2=uRQtDfk7=15Zkw4A@mail.gmail.com' \
--to=prabhakar.csengg@gmail.com \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=biju.das.jz@bp.renesas.com \
--cc=devicetree@vger.kernel.org \
--cc=geert@linux-m68k.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=krzysztof.kozlowski@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=magnus.damm@gmail.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).